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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * RTC driver for the MAX31335
4 *
5 * Copyright (C) 2023 Analog Devices
6 *
7 * Antoniu Miclaus <[email protected]>
8 *
9 */
10
11#include <linux/unaligned.h>
12#include <linux/bcd.h>
13#include <linux/bitfield.h>
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/clk-provider.h>
17#include <linux/hwmon.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/rtc.h>
25#include <linux/util_macros.h>
26
27/* MAX31335 Register Map */
28#define MAX31335_STATUS1 0x00
29#define MAX31335_INT_EN1 0x01
30#define MAX31335_STATUS2 0x02
31#define MAX31335_INT_EN2 0x03
32#define MAX31335_RTC_RESET 0x04
33#define MAX31335_RTC_CONFIG 0x05
34#define MAX31335_RTC_CONFIG2 0x06
35#define MAX31335_TIMESTAMP_CONFIG 0x07
36#define MAX31335_TIMER_CONFIG 0x08
37#define MAX31335_SECONDS_1_128 0x09
38#define MAX31335_SECONDS 0x0A
39#define MAX31335_MINUTES 0x0B
40#define MAX31335_HOURS 0x0C
41#define MAX31335_DAY 0x0D
42#define MAX31335_DATE 0x0E
43#define MAX31335_MONTH 0x0F
44#define MAX31335_YEAR 0x0F
45#define MAX31335_ALM1_SEC 0x11
46#define MAX31335_ALM1_MIN 0x12
47#define MAX31335_ALM1_HRS 0x13
48#define MAX31335_ALM1_DAY_DATE 0x14
49#define MAX31335_ALM1_MON 0x15
50#define MAX31335_ALM1_YEAR 0x16
51#define MAX31335_ALM2_MIN 0x17
52#define MAX31335_ALM2_HRS 0x18
53#define MAX31335_ALM2_DAY_DATE 0x19
54#define MAX31335_TIMER_COUNT 0x1A
55#define MAX31335_TIMER_INIT 0x1B
56#define MAX31335_PWR_MGMT 0x1C
57#define MAX31335_TRICKLE_REG 0x1D
58#define MAX31335_AGING_OFFSET 0x1E
59#define MAX31335_TS_CONFIG 0x30
60#define MAX31335_TEMP_ALARM_HIGH_MSB 0x31
61#define MAX31335_TEMP_ALARM_HIGH_LSB 0x32
62#define MAX31335_TEMP_ALARM_LOW_MSB 0x33
63#define MAX31335_TEMP_ALARM_LOW_LSB 0x34
64#define MAX31335_TEMP_DATA_MSB 0x35
65#define MAX31335_TEMP_DATA_LSB 0x36
66#define MAX31335_TS0_SEC_1_128 0x40
67#define MAX31335_TS0_SEC 0x41
68#define MAX31335_TS0_MIN 0x42
69#define MAX31335_TS0_HOUR 0x43
70#define MAX31335_TS0_DATE 0x44
71#define MAX31335_TS0_MONTH 0x45
72#define MAX31335_TS0_YEAR 0x46
73#define MAX31335_TS0_FLAGS 0x47
74#define MAX31335_TS1_SEC_1_128 0x48
75#define MAX31335_TS1_SEC 0x49
76#define MAX31335_TS1_MIN 0x4A
77#define MAX31335_TS1_HOUR 0x4B
78#define MAX31335_TS1_DATE 0x4C
79#define MAX31335_TS1_MONTH 0x4D
80#define MAX31335_TS1_YEAR 0x4E
81#define MAX31335_TS1_FLAGS 0x4F
82#define MAX31335_TS2_SEC_1_128 0x50
83#define MAX31335_TS2_SEC 0x51
84#define MAX31335_TS2_MIN 0x52
85#define MAX31335_TS2_HOUR 0x53
86#define MAX31335_TS2_DATE 0x54
87#define MAX31335_TS2_MONTH 0x55
88#define MAX31335_TS2_YEAR 0x56
89#define MAX31335_TS2_FLAGS 0x57
90#define MAX31335_TS3_SEC_1_128 0x58
91#define MAX31335_TS3_SEC 0x59
92#define MAX31335_TS3_MIN 0x5A
93#define MAX31335_TS3_HOUR 0x5B
94#define MAX31335_TS3_DATE 0x5C
95#define MAX31335_TS3_MONTH 0x5D
96#define MAX31335_TS3_YEAR 0x5E
97#define MAX31335_TS3_FLAGS 0x5F
98
99/* MAX31335_STATUS1 Bit Definitions */
100#define MAX31335_STATUS1_PSDECT BIT(7)
101#define MAX31335_STATUS1_OSF BIT(6)
102#define MAX31335_STATUS1_PFAIL BIT(5)
103#define MAX31335_STATUS1_VBATLOW BIT(4)
104#define MAX31335_STATUS1_DIF BIT(3)
105#define MAX31335_STATUS1_TIF BIT(2)
106#define MAX31335_STATUS1_A2F BIT(1)
107#define MAX31335_STATUS1_A1F BIT(0)
108
109/* MAX31335_INT_EN1 Bit Definitions */
110#define MAX31335_INT_EN1_DOSF BIT(6)
111#define MAX31335_INT_EN1_PFAILE BIT(5)
112#define MAX31335_INT_EN1_VBATLOWE BIT(4)
113#define MAX31335_INT_EN1_DIE BIT(3)
114#define MAX31335_INT_EN1_TIE BIT(2)
115#define MAX31335_INT_EN1_A2IE BIT(1)
116#define MAX31335_INT_EN1_A1IE BIT(0)
117
118/* MAX31335_STATUS2 Bit Definitions */
119#define MAX31335_STATUS2_TEMP_RDY BIT(2)
120#define MAX31335_STATUS2_OTF BIT(1)
121#define MAX31335_STATUS2_UTF BIT(0)
122
123/* MAX31335_INT_EN2 Bit Definitions */
124#define MAX31335_INT_EN2_TEMP_RDY_EN BIT(2)
125#define MAX31335_INT_EN2_OTIE BIT(1)
126#define MAX31335_INT_EN2_UTIE BIT(0)
127
128/* MAX31335_RTC_RESET Bit Definitions */
129#define MAX31335_RTC_RESET_SWRST BIT(0)
130
131/* MAX31335_RTC_CONFIG1 Bit Definitions */
132#define MAX31335_RTC_CONFIG1_EN_IO BIT(6)
133#define MAX31335_RTC_CONFIG1_A1AC GENMASK(5, 4)
134#define MAX31335_RTC_CONFIG1_DIP BIT(3)
135#define MAX31335_RTC_CONFIG1_I2C_TIMEOUT BIT(1)
136#define MAX31335_RTC_CONFIG1_EN_OSC BIT(0)
137
138/* MAX31335_RTC_CONFIG2 Bit Definitions */
139#define MAX31335_RTC_CONFIG2_ENCLKO BIT(2)
140#define MAX31335_RTC_CONFIG2_CLKO_HZ GENMASK(1, 0)
141
142/* MAX31335_TIMESTAMP_CONFIG Bit Definitions */
143#define MAX31335_TIMESTAMP_CONFIG_TSVLOW BIT(5)
144#define MAX31335_TIMESTAMP_CONFIG_TSPWM BIT(4)
145#define MAX31335_TIMESTAMP_CONFIG_TSDIN BIT(3)
146#define MAX31335_TIMESTAMP_CONFIG_TSOW BIT(2)
147#define MAX31335_TIMESTAMP_CONFIG_TSR BIT(1)
148#define MAX31335_TIMESTAMP_CONFIG_TSE BIT(0)
149
150/* MAX31335_TIMER_CONFIG Bit Definitions */
151#define MAX31335_TIMER_CONFIG_TE BIT(4)
152#define MAX31335_TIMER_CONFIG_TPAUSE BIT(3)
153#define MAX31335_TIMER_CONFIG_TRPT BIT(2)
154#define MAX31335_TIMER_CONFIG_TFS GENMASK(1, 0)
155
156/* MAX31335_HOURS Bit Definitions */
157#define MAX31335_HOURS_F_24_12 BIT(6)
158#define MAX31335_HOURS_HR_20_AM_PM BIT(5)
159
160/* MAX31335_MONTH Bit Definitions */
161#define MAX31335_MONTH_CENTURY BIT(7)
162
163/* MAX31335_PWR_MGMT Bit Definitions */
164#define MAX31335_PWR_MGMT_PFVT BIT(0)
165
166/* MAX31335_TRICKLE_REG Bit Definitions */
167#define MAX31335_TRICKLE_REG_TRICKLE GENMASK(3, 1)
168#define MAX31335_TRICKLE_REG_EN_TRICKLE BIT(0)
169
170/* MAX31335_TS_CONFIG Bit Definitions */
171#define MAX31335_TS_CONFIG_AUTO BIT(4)
172#define MAX31335_TS_CONFIG_CONVERT_T BIT(3)
173#define MAX31335_TS_CONFIG_TSINT GENMASK(2, 0)
174
175/* MAX31335_TS_FLAGS Bit Definitions */
176#define MAX31335_TS_FLAGS_VLOWF BIT(3)
177#define MAX31335_TS_FLAGS_VBATF BIT(2)
178#define MAX31335_TS_FLAGS_VCCF BIT(1)
179#define MAX31335_TS_FLAGS_DINF BIT(0)
180
181/* MAX31335 Miscellaneous Definitions */
182#define MAX31335_TRICKLE_SCHOTTKY_DIODE 1
183#define MAX31335_TRICKLE_STANDARD_DIODE 4
184#define MAX31335_RAM_SIZE 32
185#define MAX31335_TIME_SIZE 0x07
186
187/* MAX31331 Register Map */
188#define MAX31331_RTC_CONFIG2 0x04
189
190#define clk_hw_to_max31335(_hw) container_of(_hw, struct max31335_data, clkout)
191
192/* Supported Maxim RTC */
193enum max_rtc_ids {
194 ID_MAX31331,
195 ID_MAX31335,
196 MAX_RTC_ID_NR
197};
198
199struct chip_desc {
200 u8 sec_reg;
201 u8 alarm1_sec_reg;
202
203 u8 int_en_reg;
204 u8 int_status_reg;
205
206 u8 ram_reg;
207 u8 ram_size;
208
209 u8 temp_reg;
210
211 u8 trickle_reg;
212
213 u8 clkout_reg;
214
215 enum max_rtc_ids id;
216};
217
218struct max31335_data {
219 struct regmap *regmap;
220 struct rtc_device *rtc;
221 struct clk_hw clkout;
222 struct clk *clkin;
223 const struct chip_desc *chip;
224 int irq;
225};
226
227static const int max31335_clkout_freq[] = { 1, 64, 1024, 32768 };
228
229static const struct chip_desc chip[MAX_RTC_ID_NR] = {
230 [ID_MAX31331] = {
231 .id = ID_MAX31331,
232 .int_en_reg = 0x01,
233 .int_status_reg = 0x00,
234 .sec_reg = 0x08,
235 .alarm1_sec_reg = 0x0F,
236 .ram_reg = 0x20,
237 .ram_size = 32,
238 .trickle_reg = 0x1B,
239 .clkout_reg = 0x04,
240 },
241 [ID_MAX31335] = {
242 .id = ID_MAX31335,
243 .int_en_reg = 0x01,
244 .int_status_reg = 0x00,
245 .sec_reg = 0x0A,
246 .alarm1_sec_reg = 0x11,
247 .ram_reg = 0x40,
248 .ram_size = 32,
249 .temp_reg = 0x35,
250 .trickle_reg = 0x1D,
251 .clkout_reg = 0x06,
252 },
253};
254
255static const u16 max31335_trickle_resistors[] = {3000, 6000, 11000};
256
257static bool max31335_volatile_reg(struct device *dev, unsigned int reg)
258{
259 struct max31335_data *max31335 = dev_get_drvdata(dev);
260 const struct chip_desc *chip = max31335->chip;
261
262 /* time keeping registers */
263 if (reg >= chip->sec_reg && reg < chip->sec_reg + MAX31335_TIME_SIZE)
264 return true;
265
266 /* interrupt status register */
267 if (reg == chip->int_status_reg)
268 return true;
269
270 /* temperature registers if valid */
271 if (chip->temp_reg && (reg == chip->temp_reg || reg == chip->temp_reg + 1))
272 return true;
273
274 return false;
275}
276
277static const struct regmap_config regmap_config = {
278 .reg_bits = 8,
279 .val_bits = 8,
280 .max_register = 0x5F,
281 .volatile_reg = max31335_volatile_reg,
282};
283
284static int max31335_read_time(struct device *dev, struct rtc_time *tm)
285{
286 struct max31335_data *max31335 = dev_get_drvdata(dev);
287 u8 date[7];
288 int ret;
289
290 ret = regmap_bulk_read(max31335->regmap, max31335->chip->sec_reg, date,
291 sizeof(date));
292 if (ret)
293 return ret;
294
295 tm->tm_sec = bcd2bin(date[0] & 0x7f);
296 tm->tm_min = bcd2bin(date[1] & 0x7f);
297 tm->tm_hour = bcd2bin(date[2] & 0x3f);
298 tm->tm_wday = bcd2bin(date[3] & 0x7) - 1;
299 tm->tm_mday = bcd2bin(date[4] & 0x3f);
300 tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1;
301 tm->tm_year = bcd2bin(date[6]) + 100;
302
303 if (FIELD_GET(MAX31335_MONTH_CENTURY, date[5]))
304 tm->tm_year += 100;
305
306 return 0;
307}
308
309static int max31335_set_time(struct device *dev, struct rtc_time *tm)
310{
311 struct max31335_data *max31335 = dev_get_drvdata(dev);
312 u8 date[7];
313
314 date[0] = bin2bcd(tm->tm_sec);
315 date[1] = bin2bcd(tm->tm_min);
316 date[2] = bin2bcd(tm->tm_hour);
317 date[3] = bin2bcd(tm->tm_wday + 1);
318 date[4] = bin2bcd(tm->tm_mday);
319 date[5] = bin2bcd(tm->tm_mon + 1);
320 date[6] = bin2bcd(tm->tm_year % 100);
321
322 if (tm->tm_year >= 200)
323 date[5] |= FIELD_PREP(MAX31335_MONTH_CENTURY, 1);
324
325 return regmap_bulk_write(max31335->regmap, max31335->chip->sec_reg, date,
326 sizeof(date));
327}
328
329static int max31335_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
330{
331 struct max31335_data *max31335 = dev_get_drvdata(dev);
332 int ret, ctrl, status;
333 struct rtc_time time;
334 u8 regs[6];
335
336 ret = regmap_bulk_read(max31335->regmap, max31335->chip->alarm1_sec_reg, regs,
337 sizeof(regs));
338 if (ret)
339 return ret;
340
341 alrm->time.tm_sec = bcd2bin(regs[0] & 0x7f);
342 alrm->time.tm_min = bcd2bin(regs[1] & 0x7f);
343 alrm->time.tm_hour = bcd2bin(regs[2] & 0x3f);
344 alrm->time.tm_mday = bcd2bin(regs[3] & 0x3f);
345 alrm->time.tm_mon = bcd2bin(regs[4] & 0x1f) - 1;
346 alrm->time.tm_year = bcd2bin(regs[5]) + 100;
347
348 ret = max31335_read_time(dev, &time);
349 if (ret)
350 return ret;
351
352 if (time.tm_year >= 200)
353 alrm->time.tm_year += 100;
354
355 ret = regmap_read(max31335->regmap, max31335->chip->int_en_reg, &ctrl);
356 if (ret)
357 return ret;
358
359 ret = regmap_read(max31335->regmap, max31335->chip->int_status_reg, &status);
360 if (ret)
361 return ret;
362
363 alrm->enabled = FIELD_GET(MAX31335_INT_EN1_A1IE, ctrl);
364 alrm->pending = FIELD_GET(MAX31335_STATUS1_A1F, status);
365
366 return 0;
367}
368
369static int max31335_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
370{
371 struct max31335_data *max31335 = dev_get_drvdata(dev);
372 unsigned int reg;
373 u8 regs[6];
374 int ret;
375
376 regs[0] = bin2bcd(alrm->time.tm_sec);
377 regs[1] = bin2bcd(alrm->time.tm_min);
378 regs[2] = bin2bcd(alrm->time.tm_hour);
379 regs[3] = bin2bcd(alrm->time.tm_mday);
380 regs[4] = bin2bcd(alrm->time.tm_mon + 1);
381 regs[5] = bin2bcd(alrm->time.tm_year % 100);
382
383 ret = regmap_bulk_write(max31335->regmap, max31335->chip->alarm1_sec_reg,
384 regs, sizeof(regs));
385 if (ret)
386 return ret;
387
388 reg = FIELD_PREP(MAX31335_INT_EN1_A1IE, alrm->enabled);
389 ret = regmap_update_bits(max31335->regmap, max31335->chip->int_en_reg,
390 MAX31335_INT_EN1_A1IE, reg);
391 if (ret)
392 return ret;
393
394 return regmap_update_bits(max31335->regmap, max31335->chip->int_status_reg,
395 MAX31335_STATUS1_A1F, 0);
396}
397
398static int max31335_alarm_irq_enable(struct device *dev, unsigned int enabled)
399{
400 struct max31335_data *max31335 = dev_get_drvdata(dev);
401
402 return regmap_update_bits(max31335->regmap, max31335->chip->int_en_reg,
403 MAX31335_INT_EN1_A1IE, enabled);
404}
405
406static irqreturn_t max31335_handle_irq(int irq, void *dev_id)
407{
408 struct max31335_data *max31335 = dev_id;
409 struct mutex *lock = &max31335->rtc->ops_lock;
410 int ret, status;
411
412 mutex_lock(lock);
413
414 ret = regmap_read(max31335->regmap, max31335->chip->int_status_reg, &status);
415 if (ret)
416 goto exit;
417
418 if (FIELD_GET(MAX31335_STATUS1_A1F, status)) {
419 ret = regmap_update_bits(max31335->regmap, max31335->chip->int_status_reg,
420 MAX31335_STATUS1_A1F, 0);
421 if (ret)
422 goto exit;
423
424 rtc_update_irq(max31335->rtc, 1, RTC_AF | RTC_IRQF);
425 }
426
427exit:
428 mutex_unlock(lock);
429
430 return IRQ_HANDLED;
431}
432
433static const struct rtc_class_ops max31335_rtc_ops = {
434 .read_time = max31335_read_time,
435 .set_time = max31335_set_time,
436 .read_alarm = max31335_read_alarm,
437 .set_alarm = max31335_set_alarm,
438 .alarm_irq_enable = max31335_alarm_irq_enable,
439};
440
441static int max31335_trickle_charger_setup(struct device *dev,
442 struct max31335_data *max31335)
443{
444 u32 ohms, chargeable;
445 int i, trickle_cfg;
446 const char *diode;
447
448 if (device_property_read_u32(dev, "aux-voltage-chargeable",
449 &chargeable))
450 return 0;
451
452 if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
453 return 0;
454
455 if (device_property_read_string(dev, "adi,tc-diode", &diode))
456 return 0;
457
458 if (!strcmp(diode, "schottky"))
459 trickle_cfg = MAX31335_TRICKLE_SCHOTTKY_DIODE;
460 else if (!strcmp(diode, "standard+schottky"))
461 trickle_cfg = MAX31335_TRICKLE_STANDARD_DIODE;
462 else
463 return dev_err_probe(dev, -EINVAL,
464 "Invalid tc-diode value: %s\n", diode);
465
466 for (i = 0; i < ARRAY_SIZE(max31335_trickle_resistors); i++)
467 if (ohms == max31335_trickle_resistors[i])
468 break;
469
470 if (i >= ARRAY_SIZE(max31335_trickle_resistors))
471 return 0;
472
473 i = i + trickle_cfg;
474
475 return regmap_write(max31335->regmap, max31335->chip->trickle_reg,
476 FIELD_PREP(MAX31335_TRICKLE_REG_TRICKLE, i) |
477 FIELD_PREP(MAX31335_TRICKLE_REG_EN_TRICKLE,
478 chargeable));
479}
480
481static unsigned long max31335_clkout_recalc_rate(struct clk_hw *hw,
482 unsigned long parent_rate)
483{
484 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
485 unsigned int freq_mask;
486 unsigned int reg;
487 int ret;
488
489 ret = regmap_read(max31335->regmap, max31335->chip->clkout_reg, &reg);
490 if (ret)
491 return 0;
492
493 freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1;
494
495 return max31335_clkout_freq[reg & freq_mask];
496}
497
498static int max31335_clkout_determine_rate(struct clk_hw *hw,
499 struct clk_rate_request *req)
500{
501 int index;
502
503 index = find_closest(req->rate, max31335_clkout_freq,
504 ARRAY_SIZE(max31335_clkout_freq));
505
506 req->rate = max31335_clkout_freq[index];
507
508 return 0;
509}
510
511static int max31335_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
512 unsigned long parent_rate)
513{
514 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
515 unsigned int freq_mask;
516 int index;
517
518 index = find_closest(rate, max31335_clkout_freq,
519 ARRAY_SIZE(max31335_clkout_freq));
520 freq_mask = __roundup_pow_of_two(ARRAY_SIZE(max31335_clkout_freq)) - 1;
521
522 return regmap_update_bits(max31335->regmap, max31335->chip->clkout_reg,
523 freq_mask, index);
524}
525
526static int max31335_clkout_enable(struct clk_hw *hw)
527{
528 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
529
530 return regmap_set_bits(max31335->regmap, max31335->chip->clkout_reg,
531 MAX31335_RTC_CONFIG2_ENCLKO);
532}
533
534static void max31335_clkout_disable(struct clk_hw *hw)
535{
536 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
537
538 regmap_clear_bits(max31335->regmap, max31335->chip->clkout_reg,
539 MAX31335_RTC_CONFIG2_ENCLKO);
540}
541
542static int max31335_clkout_is_enabled(struct clk_hw *hw)
543{
544 struct max31335_data *max31335 = clk_hw_to_max31335(hw);
545 unsigned int reg;
546 int ret;
547
548 ret = regmap_read(max31335->regmap, max31335->chip->clkout_reg, &reg);
549 if (ret)
550 return ret;
551
552 return !!(reg & MAX31335_RTC_CONFIG2_ENCLKO);
553}
554
555static const struct clk_ops max31335_clkout_ops = {
556 .recalc_rate = max31335_clkout_recalc_rate,
557 .determine_rate = max31335_clkout_determine_rate,
558 .set_rate = max31335_clkout_set_rate,
559 .enable = max31335_clkout_enable,
560 .disable = max31335_clkout_disable,
561 .is_enabled = max31335_clkout_is_enabled,
562};
563
564static struct clk_init_data max31335_clk_init = {
565 .name = "max31335-clkout",
566 .ops = &max31335_clkout_ops,
567};
568
569static int max31335_nvmem_reg_read(void *priv, unsigned int offset,
570 void *val, size_t bytes)
571{
572 struct max31335_data *max31335 = priv;
573 unsigned int reg = max31335->chip->ram_reg + offset;
574
575 return regmap_bulk_read(max31335->regmap, reg, val, bytes);
576}
577
578static int max31335_nvmem_reg_write(void *priv, unsigned int offset,
579 void *val, size_t bytes)
580{
581 struct max31335_data *max31335 = priv;
582 unsigned int reg = max31335->chip->ram_reg + offset;
583
584 return regmap_bulk_write(max31335->regmap, reg, val, bytes);
585}
586
587static struct nvmem_config max31335_nvmem_cfg = {
588 .reg_read = max31335_nvmem_reg_read,
589 .reg_write = max31335_nvmem_reg_write,
590 .word_size = 8,
591 .size = MAX31335_RAM_SIZE,
592};
593
594#if IS_REACHABLE(CONFIG_HWMON)
595static int max31335_read_temp(struct device *dev, enum hwmon_sensor_types type,
596 u32 attr, int channel, long *val)
597{
598 struct max31335_data *max31335 = dev_get_drvdata(dev);
599 u8 reg[2];
600 s16 temp;
601 int ret;
602
603 if (type != hwmon_temp || attr != hwmon_temp_input)
604 return -EOPNOTSUPP;
605
606 ret = regmap_bulk_read(max31335->regmap, max31335->chip->temp_reg,
607 reg, 2);
608 if (ret)
609 return ret;
610
611 temp = get_unaligned_be16(reg);
612
613 *val = (temp / 64) * 250;
614
615 return 0;
616}
617
618static umode_t max31335_is_visible(const void *data,
619 enum hwmon_sensor_types type,
620 u32 attr, int channel)
621{
622 if (type == hwmon_temp && attr == hwmon_temp_input)
623 return 0444;
624
625 return 0;
626}
627
628static const struct hwmon_channel_info *max31335_info[] = {
629 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT),
630 NULL
631};
632
633static const struct hwmon_ops max31335_hwmon_ops = {
634 .is_visible = max31335_is_visible,
635 .read = max31335_read_temp,
636};
637
638static const struct hwmon_chip_info max31335_chip_info = {
639 .ops = &max31335_hwmon_ops,
640 .info = max31335_info,
641};
642#endif
643
644static int max31335_clkout_register(struct device *dev)
645{
646 struct max31335_data *max31335 = dev_get_drvdata(dev);
647 int ret;
648
649 if (!device_property_present(dev, "#clock-cells"))
650 return regmap_clear_bits(max31335->regmap, max31335->chip->clkout_reg,
651 MAX31335_RTC_CONFIG2_ENCLKO);
652
653 max31335->clkout.init = &max31335_clk_init;
654
655 ret = devm_clk_hw_register(dev, &max31335->clkout);
656 if (ret)
657 return dev_err_probe(dev, ret, "cannot register clock\n");
658
659 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
660 &max31335->clkout);
661 if (ret)
662 return dev_err_probe(dev, ret, "cannot add hw provider\n");
663
664 max31335->clkout.clk = devm_clk_get_enabled(dev, NULL);
665 if (IS_ERR(max31335->clkout.clk))
666 return dev_err_probe(dev, PTR_ERR(max31335->clkout.clk),
667 "cannot enable clkout\n");
668
669 return 0;
670}
671
672static int max31335_probe(struct i2c_client *client)
673{
674 struct max31335_data *max31335;
675#if IS_REACHABLE(CONFIG_HWMON)
676 struct device *hwmon;
677#endif
678 const struct chip_desc *match;
679 int ret;
680
681 max31335 = devm_kzalloc(&client->dev, sizeof(*max31335), GFP_KERNEL);
682 if (!max31335)
683 return -ENOMEM;
684
685 max31335->regmap = devm_regmap_init_i2c(client, &regmap_config);
686 if (IS_ERR(max31335->regmap))
687 return PTR_ERR(max31335->regmap);
688
689 i2c_set_clientdata(client, max31335);
690 match = i2c_get_match_data(client);
691 if (!match)
692 return -ENODEV;
693 max31335->chip = match;
694 max31335->rtc = devm_rtc_allocate_device(&client->dev);
695 if (IS_ERR(max31335->rtc))
696 return PTR_ERR(max31335->rtc);
697
698 max31335->rtc->ops = &max31335_rtc_ops;
699 max31335->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
700 max31335->rtc->range_max = RTC_TIMESTAMP_END_2199;
701 max31335->rtc->alarm_offset_max = 24 * 60 * 60;
702
703 ret = max31335_clkout_register(&client->dev);
704 if (ret)
705 return ret;
706
707 if (client->irq > 0) {
708 ret = devm_request_threaded_irq(&client->dev, client->irq,
709 NULL, max31335_handle_irq,
710 IRQF_ONESHOT,
711 "max31335", max31335);
712 if (ret) {
713 dev_warn(&client->dev,
714 "unable to request IRQ, alarm max31335 disabled\n");
715 client->irq = 0;
716 } else {
717 max31335->irq = client->irq;
718 }
719 }
720
721 if (!client->irq)
722 clear_bit(RTC_FEATURE_ALARM, max31335->rtc->features);
723
724 max31335_nvmem_cfg.priv = max31335;
725 ret = devm_rtc_nvmem_register(max31335->rtc, &max31335_nvmem_cfg);
726 if (ret)
727 return dev_err_probe(&client->dev, ret,
728 "cannot register rtc nvmem\n");
729
730#if IS_REACHABLE(CONFIG_HWMON)
731 if (max31335->chip->temp_reg) {
732 hwmon = devm_hwmon_device_register_with_info(&client->dev, client->name, max31335,
733 &max31335_chip_info, NULL);
734 if (IS_ERR(hwmon))
735 return dev_err_probe(&client->dev, PTR_ERR(hwmon),
736 "cannot register hwmon device\n");
737 }
738#endif
739
740 ret = max31335_trickle_charger_setup(&client->dev, max31335);
741 if (ret)
742 return ret;
743
744 return devm_rtc_register_device(max31335->rtc);
745}
746
747static const struct i2c_device_id max31335_id[] = {
748 { .name = "max31331", .driver_data = (kernel_ulong_t)&chip[ID_MAX31331] },
749 { .name = "max31335", .driver_data = (kernel_ulong_t)&chip[ID_MAX31335] },
750 { }
751};
752
753MODULE_DEVICE_TABLE(i2c, max31335_id);
754
755static const struct of_device_id max31335_of_match[] = {
756 { .compatible = "adi,max31331", .data = &chip[ID_MAX31331] },
757 { .compatible = "adi,max31335", .data = &chip[ID_MAX31335] },
758 { }
759};
760
761MODULE_DEVICE_TABLE(of, max31335_of_match);
762
763static struct i2c_driver max31335_driver = {
764 .driver = {
765 .name = "rtc-max31335",
766 .of_match_table = max31335_of_match,
767 },
768 .probe = max31335_probe,
769 .id_table = max31335_id,
770};
771module_i2c_driver(max31335_driver);
772
773MODULE_AUTHOR("Antoniu Miclaus <[email protected]>");
774MODULE_AUTHOR("Saket Kumar Purwar <[email protected]>");
775MODULE_DESCRIPTION("MAX31335 RTC driver");
776MODULE_LICENSE("GPL");