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1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* [email protected] */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <[email protected]> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/* 7.12.xx - Use STATIC functions wherever possible */
141/* - Clean up deprecated MODULE_PARM calls */
142/* 7.12.05 - Remove Version Matching per IBM request */
143/*****************************************************************************/
144
145/*
146 * Conditional Compilation directives for this driver:
147 *
148 * IPS_DEBUG - Turn on debugging info
149 *
150 * Parameters:
151 *
152 * debug:<number> - Set debug level to <number>
153 * NOTE: only works when IPS_DEBUG compile directive is used.
154 * 1 - Normal debug messages
155 * 2 - Verbose debug messages
156 * 11 - Method trace (non interrupt)
157 * 12 - Method trace (includes interrupt)
158 *
159 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
160 * nommap - Don't use memory mapped I/O
161 * ioctlsize - Initial size of the IOCTL buffer
162 */
163
164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/hex.h>
171#include <linux/kernel.h>
172#include <linux/ioport.h>
173#include <linux/slab.h>
174#include <linux/delay.h>
175#include <linux/pci.h>
176#include <linux/proc_fs.h>
177#include <linux/reboot.h>
178#include <linux/interrupt.h>
179
180#include <linux/blkdev.h>
181#include <linux/types.h>
182#include <linux/dma-mapping.h>
183
184#include <scsi/scsi.h>
185#include <scsi/scsi_cmnd.h>
186#include <scsi/scsi_device.h>
187#include <scsi/scsi_eh.h>
188#include <scsi/scsi_host.h>
189#include <scsi/scsi_tcq.h>
190#include <scsi/sg.h>
191
192#include "ips.h"
193
194#include <linux/module.h>
195
196#include <linux/stat.h>
197
198#include <linux/spinlock.h>
199#include <linux/init.h>
200
201#include <linux/smp.h>
202
203#ifdef MODULE
204static char *ips = NULL;
205module_param(ips, charp, 0);
206#endif
207
208/*
209 * DRIVER_VER
210 */
211#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
212#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
213
214#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
215 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
216 DMA_BIDIRECTIONAL : \
217 scb->scsi_cmd->sc_data_direction)
218
219#ifdef IPS_DEBUG
220#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
221#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
222#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
223#else
224#define METHOD_TRACE(s, i)
225#define DEBUG(i, s)
226#define DEBUG_VAR(i, s, v...)
227#endif
228
229/*
230 * Function prototypes
231 */
232static int ips_eh_abort(struct scsi_cmnd *);
233static int ips_eh_reset(struct scsi_cmnd *);
234static enum scsi_qc_status ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
235static const char *ips_info(struct Scsi_Host *);
236static irqreturn_t do_ipsintr(int, void *);
237static int ips_hainit(ips_ha_t *);
238static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
239static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
240static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
241static int ips_online(ips_ha_t *, ips_scb_t *);
242static int ips_inquiry(ips_ha_t *, ips_scb_t *);
243static int ips_rdcap(ips_ha_t *, ips_scb_t *);
244static int ips_msense(ips_ha_t *, ips_scb_t *);
245static int ips_reqsen(ips_ha_t *, ips_scb_t *);
246static int ips_deallocatescbs(ips_ha_t *, int);
247static int ips_allocatescbs(ips_ha_t *);
248static int ips_reset_copperhead(ips_ha_t *);
249static int ips_reset_copperhead_memio(ips_ha_t *);
250static int ips_reset_morpheus(ips_ha_t *);
251static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
252static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
253static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
254static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
255static int ips_isintr_copperhead(ips_ha_t *);
256static int ips_isintr_copperhead_memio(ips_ha_t *);
257static int ips_isintr_morpheus(ips_ha_t *);
258static int ips_wait(ips_ha_t *, int, int);
259static int ips_write_driver_status(ips_ha_t *, int);
260static int ips_read_adapter_status(ips_ha_t *, int);
261static int ips_read_subsystem_parameters(ips_ha_t *, int);
262static int ips_read_config(ips_ha_t *, int);
263static int ips_clear_adapter(ips_ha_t *, int);
264static int ips_readwrite_page5(ips_ha_t *, int, int);
265static int ips_init_copperhead(ips_ha_t *);
266static int ips_init_copperhead_memio(ips_ha_t *);
267static int ips_init_morpheus(ips_ha_t *);
268static int ips_isinit_copperhead(ips_ha_t *);
269static int ips_isinit_copperhead_memio(ips_ha_t *);
270static int ips_isinit_morpheus(ips_ha_t *);
271static int ips_erase_bios(ips_ha_t *);
272static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
273static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
274static int ips_erase_bios_memio(ips_ha_t *);
275static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
276static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
277static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
278static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
279static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
280static void ips_free_flash_copperhead(ips_ha_t * ha);
281static void ips_get_bios_version(ips_ha_t *, int);
282static void ips_identify_controller(ips_ha_t *);
283static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
284static void ips_enable_int_copperhead(ips_ha_t *);
285static void ips_enable_int_copperhead_memio(ips_ha_t *);
286static void ips_enable_int_morpheus(ips_ha_t *);
287static int ips_intr_copperhead(ips_ha_t *);
288static int ips_intr_morpheus(ips_ha_t *);
289static void ips_next(ips_ha_t *, int);
290static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
291static void ipsintr_done(ips_ha_t *, struct ips_scb *);
292static void ips_done(ips_ha_t *, ips_scb_t *);
293static void ips_free(ips_ha_t *);
294static void ips_init_scb(ips_ha_t *, ips_scb_t *);
295static void ips_freescb(ips_ha_t *, ips_scb_t *);
296static void ips_setup_funclist(ips_ha_t *);
297static void ips_statinit(ips_ha_t *);
298static void ips_statinit_memio(ips_ha_t *);
299static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t);
300static void ips_ffdc_reset(ips_ha_t *, int);
301static void ips_ffdc_time(ips_ha_t *);
302static uint32_t ips_statupd_copperhead(ips_ha_t *);
303static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
304static uint32_t ips_statupd_morpheus(ips_ha_t *);
305static ips_scb_t *ips_getscb(ips_ha_t *);
306static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
307static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
308static void ips_putq_copp_tail(ips_copp_queue_t *,
309 ips_copp_wait_item_t *);
310static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
311static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
312static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
313static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
314 struct scsi_cmnd *);
315static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
316 ips_copp_wait_item_t *);
317static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
318
319static int ips_is_passthru(struct scsi_cmnd *);
320static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
321static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
322static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
323static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
324 unsigned int count);
325static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
326 unsigned int count);
327
328static int ips_write_info(struct Scsi_Host *, char *, int);
329static int ips_show_info(struct seq_file *, struct Scsi_Host *);
330static int ips_host_info(ips_ha_t *, struct seq_file *);
331static int ips_abort_init(ips_ha_t * ha, int index);
332static int ips_init_phase2(int index);
333
334static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
335static int ips_register_scsi(int index);
336
337static int ips_poll_for_flush_complete(ips_ha_t * ha);
338static void ips_flush_and_reset(ips_ha_t *ha);
339
340/*
341 * global variables
342 */
343static const char ips_name[] = "ips";
344static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
345static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
346static unsigned int ips_next_controller;
347static unsigned int ips_num_controllers;
348static unsigned int ips_released_controllers;
349static int ips_hotplug;
350static int ips_cmd_timeout = 60;
351static int ips_reset_timeout = 60 * 5;
352static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
353static int ips_force_i2o = 1; /* Always use I2O command delivery */
354static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
355static int ips_cd_boot; /* Booting from Manager CD */
356static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
357static dma_addr_t ips_flashbusaddr;
358static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
359static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
360static struct scsi_host_template ips_driver_template = {
361 .info = ips_info,
362 .queuecommand = ips_queue,
363 .eh_abort_handler = ips_eh_abort,
364 .eh_host_reset_handler = ips_eh_reset,
365 .proc_name = "ips",
366 .show_info = ips_show_info,
367 .write_info = ips_write_info,
368 .sdev_configure = ips_sdev_configure,
369 .bios_param = ips_biosparam,
370 .this_id = -1,
371 .sg_tablesize = IPS_MAX_SG,
372 .cmd_per_lun = 3,
373 .no_write_same = 1,
374};
375
376
377/* This table describes all ServeRAID Adapters */
378static struct pci_device_id ips_pci_table[] = {
379 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
380 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
381 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
382 { 0, }
383};
384
385MODULE_DEVICE_TABLE( pci, ips_pci_table );
386
387static char ips_hot_plug_name[] = "ips";
388
389static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
390static void ips_remove_device(struct pci_dev *pci_dev);
391
392static struct pci_driver ips_pci_driver = {
393 .name = ips_hot_plug_name,
394 .id_table = ips_pci_table,
395 .probe = ips_insert_device,
396 .remove = ips_remove_device,
397};
398
399
400/*
401 * Necessary forward function protoypes
402 */
403static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
404
405#define MAX_ADAPTER_NAME 15
406
407static char ips_adapter_name[][30] = {
408 "ServeRAID",
409 "ServeRAID II",
410 "ServeRAID on motherboard",
411 "ServeRAID on motherboard",
412 "ServeRAID 3H",
413 "ServeRAID 3L",
414 "ServeRAID 4H",
415 "ServeRAID 4M",
416 "ServeRAID 4L",
417 "ServeRAID 4Mx",
418 "ServeRAID 4Lx",
419 "ServeRAID 5i",
420 "ServeRAID 5i",
421 "ServeRAID 6M",
422 "ServeRAID 6i",
423 "ServeRAID 7t",
424 "ServeRAID 7k",
425 "ServeRAID 7M"
426};
427
428static struct notifier_block ips_notifier = {
429 ips_halt, NULL, 0
430};
431
432/*
433 * Direction table
434 */
435static char ips_command_direction[] = {
436 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
438 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
441 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
442 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
443 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
444 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
445 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
446 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
447 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
450 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
451 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
470 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
472 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
487};
488
489
490/****************************************************************************/
491/* */
492/* Routine Name: ips_setup */
493/* */
494/* Routine Description: */
495/* */
496/* setup parameters to the driver */
497/* */
498/****************************************************************************/
499static int
500ips_setup(char *ips_str)
501{
502
503 int i;
504 char *key;
505 char *value;
506 static const IPS_OPTION options[] = {
507 {"noi2o", &ips_force_i2o, 0},
508 {"nommap", &ips_force_memio, 0},
509 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
510 {"cdboot", &ips_cd_boot, 0},
511 {"maxcmds", &MaxLiteCmds, 32},
512 };
513
514 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
515 /* Search for value */
516 while ((key = strsep(&ips_str, ",."))) {
517 if (!*key)
518 continue;
519 value = strchr(key, ':');
520 if (value)
521 *value++ = '\0';
522 /*
523 * We now have key/value pairs.
524 * Update the variables
525 */
526 for (i = 0; i < ARRAY_SIZE(options); i++) {
527 if (strncasecmp
528 (key, options[i].option_name,
529 strlen(options[i].option_name)) == 0) {
530 if (value)
531 *options[i].option_flag =
532 simple_strtoul(value, NULL, 0);
533 else
534 *options[i].option_flag =
535 options[i].option_value;
536 break;
537 }
538 }
539 }
540
541 return (1);
542}
543
544__setup("ips=", ips_setup);
545
546/****************************************************************************/
547/* */
548/* Routine Name: ips_detect */
549/* */
550/* Routine Description: */
551/* */
552/* Detect and initialize the driver */
553/* */
554/* NOTE: this routine is called under the io_request_lock spinlock */
555/* */
556/****************************************************************************/
557static int
558ips_detect(struct scsi_host_template * SHT)
559{
560 int i;
561
562 METHOD_TRACE("ips_detect", 1);
563
564#ifdef MODULE
565 if (ips)
566 ips_setup(ips);
567#endif
568
569 for (i = 0; i < ips_num_controllers; i++) {
570 if (ips_register_scsi(i))
571 ips_free(ips_ha[i]);
572 ips_released_controllers++;
573 }
574 ips_hotplug = 1;
575 return (ips_num_controllers);
576}
577
578/****************************************************************************/
579/* configure the function pointers to use the functions that will work */
580/* with the found version of the adapter */
581/****************************************************************************/
582static void
583ips_setup_funclist(ips_ha_t * ha)
584{
585
586 /*
587 * Setup Functions
588 */
589 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
590 /* morpheus / marco / sebring */
591 ha->func.isintr = ips_isintr_morpheus;
592 ha->func.isinit = ips_isinit_morpheus;
593 ha->func.issue = ips_issue_i2o_memio;
594 ha->func.init = ips_init_morpheus;
595 ha->func.statupd = ips_statupd_morpheus;
596 ha->func.reset = ips_reset_morpheus;
597 ha->func.intr = ips_intr_morpheus;
598 ha->func.enableint = ips_enable_int_morpheus;
599 } else if (IPS_USE_MEMIO(ha)) {
600 /* copperhead w/MEMIO */
601 ha->func.isintr = ips_isintr_copperhead_memio;
602 ha->func.isinit = ips_isinit_copperhead_memio;
603 ha->func.init = ips_init_copperhead_memio;
604 ha->func.statupd = ips_statupd_copperhead_memio;
605 ha->func.statinit = ips_statinit_memio;
606 ha->func.reset = ips_reset_copperhead_memio;
607 ha->func.intr = ips_intr_copperhead;
608 ha->func.erasebios = ips_erase_bios_memio;
609 ha->func.programbios = ips_program_bios_memio;
610 ha->func.verifybios = ips_verify_bios_memio;
611 ha->func.enableint = ips_enable_int_copperhead_memio;
612 if (IPS_USE_I2O_DELIVER(ha))
613 ha->func.issue = ips_issue_i2o_memio;
614 else
615 ha->func.issue = ips_issue_copperhead_memio;
616 } else {
617 /* copperhead */
618 ha->func.isintr = ips_isintr_copperhead;
619 ha->func.isinit = ips_isinit_copperhead;
620 ha->func.init = ips_init_copperhead;
621 ha->func.statupd = ips_statupd_copperhead;
622 ha->func.statinit = ips_statinit;
623 ha->func.reset = ips_reset_copperhead;
624 ha->func.intr = ips_intr_copperhead;
625 ha->func.erasebios = ips_erase_bios;
626 ha->func.programbios = ips_program_bios;
627 ha->func.verifybios = ips_verify_bios;
628 ha->func.enableint = ips_enable_int_copperhead;
629
630 if (IPS_USE_I2O_DELIVER(ha))
631 ha->func.issue = ips_issue_i2o;
632 else
633 ha->func.issue = ips_issue_copperhead;
634 }
635}
636
637/****************************************************************************/
638/* */
639/* Routine Name: ips_release */
640/* */
641/* Routine Description: */
642/* */
643/* Remove a driver */
644/* */
645/****************************************************************************/
646static void ips_release(struct Scsi_Host *sh)
647{
648 ips_scb_t *scb;
649 ips_ha_t *ha;
650 int i;
651
652 METHOD_TRACE("ips_release", 1);
653
654 scsi_remove_host(sh);
655
656 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
657
658 if (i == IPS_MAX_ADAPTERS) {
659 printk(KERN_WARNING
660 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
661 BUG();
662 }
663
664 ha = IPS_HA(sh);
665
666 if (!ha)
667 return;
668
669 /* flush the cache on the controller */
670 scb = &ha->scbs[ha->max_cmds - 1];
671
672 ips_init_scb(ha, scb);
673
674 scb->timeout = ips_cmd_timeout;
675 scb->cdb[0] = IPS_CMD_FLUSH;
676
677 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
678 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
679 scb->cmd.flush_cache.state = IPS_NORM_STATE;
680 scb->cmd.flush_cache.reserved = 0;
681 scb->cmd.flush_cache.reserved2 = 0;
682 scb->cmd.flush_cache.reserved3 = 0;
683 scb->cmd.flush_cache.reserved4 = 0;
684
685 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
686
687 /* send command */
688 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
689 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
690
691 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
692
693 ips_sh[i] = NULL;
694 ips_ha[i] = NULL;
695
696 /* free extra memory */
697 ips_free(ha);
698
699 /* free IRQ */
700 free_irq(ha->pcidev->irq, ha);
701
702 scsi_host_put(sh);
703
704 ips_released_controllers++;
705}
706
707/****************************************************************************/
708/* */
709/* Routine Name: ips_halt */
710/* */
711/* Routine Description: */
712/* */
713/* Perform cleanup when the system reboots */
714/* */
715/****************************************************************************/
716static int
717ips_halt(struct notifier_block *nb, ulong event, void *buf)
718{
719 ips_scb_t *scb;
720 ips_ha_t *ha;
721 int i;
722
723 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
724 (event != SYS_POWER_OFF))
725 return (NOTIFY_DONE);
726
727 for (i = 0; i < ips_next_controller; i++) {
728 ha = (ips_ha_t *) ips_ha[i];
729
730 if (!ha)
731 continue;
732
733 if (!ha->active)
734 continue;
735
736 /* flush the cache on the controller */
737 scb = &ha->scbs[ha->max_cmds - 1];
738
739 ips_init_scb(ha, scb);
740
741 scb->timeout = ips_cmd_timeout;
742 scb->cdb[0] = IPS_CMD_FLUSH;
743
744 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
745 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
746 scb->cmd.flush_cache.state = IPS_NORM_STATE;
747 scb->cmd.flush_cache.reserved = 0;
748 scb->cmd.flush_cache.reserved2 = 0;
749 scb->cmd.flush_cache.reserved3 = 0;
750 scb->cmd.flush_cache.reserved4 = 0;
751
752 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
753
754 /* send command */
755 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
756 IPS_FAILURE)
757 IPS_PRINTK(KERN_WARNING, ha->pcidev,
758 "Incomplete Flush.\n");
759 else
760 IPS_PRINTK(KERN_WARNING, ha->pcidev,
761 "Flushing Complete.\n");
762 }
763
764 return (NOTIFY_OK);
765}
766
767/****************************************************************************/
768/* */
769/* Routine Name: ips_eh_abort */
770/* */
771/* Routine Description: */
772/* */
773/* Abort a command (using the new error code stuff) */
774/* Note: this routine is called under the io_request_lock */
775/****************************************************************************/
776int ips_eh_abort(struct scsi_cmnd *SC)
777{
778 ips_ha_t *ha;
779 ips_copp_wait_item_t *item;
780 int ret;
781 struct Scsi_Host *host;
782
783 METHOD_TRACE("ips_eh_abort", 1);
784
785 if (!SC)
786 return (FAILED);
787
788 host = SC->device->host;
789 ha = (ips_ha_t *) SC->device->host->hostdata;
790
791 if (!ha)
792 return (FAILED);
793
794 if (!ha->active)
795 return (FAILED);
796
797 spin_lock(host->host_lock);
798
799 /* See if the command is on the copp queue */
800 item = ha->copp_waitlist.head;
801 while ((item) && (item->scsi_cmd != SC))
802 item = item->next;
803
804 if (item) {
805 /* Found it */
806 ips_removeq_copp(&ha->copp_waitlist, item);
807 ret = (SUCCESS);
808
809 /* See if the command is on the wait queue */
810 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
811 /* command not sent yet */
812 ret = (SUCCESS);
813 } else {
814 /* command must have already been sent */
815 ret = (FAILED);
816 }
817
818 spin_unlock(host->host_lock);
819 return ret;
820}
821
822/****************************************************************************/
823/* */
824/* Routine Name: ips_eh_reset */
825/* */
826/* Routine Description: */
827/* */
828/* Reset the controller (with new eh error code) */
829/* */
830/* NOTE: this routine is called under the io_request_lock spinlock */
831/* */
832/****************************************************************************/
833static int __ips_eh_reset(struct scsi_cmnd *SC)
834{
835 int ret;
836 int i;
837 ips_ha_t *ha;
838 ips_scb_t *scb;
839
840 METHOD_TRACE("ips_eh_reset", 1);
841
842#ifdef NO_IPS_RESET
843 return (FAILED);
844#else
845
846 if (!SC) {
847 DEBUG(1, "Reset called with NULL scsi command");
848
849 return (FAILED);
850 }
851
852 ha = (ips_ha_t *) SC->device->host->hostdata;
853
854 if (!ha) {
855 DEBUG(1, "Reset called with NULL ha struct");
856
857 return (FAILED);
858 }
859
860 if (!ha->active)
861 return (FAILED);
862
863 /* An explanation for the casual observer: */
864 /* Part of the function of a RAID controller is automatic error */
865 /* detection and recovery. As such, the only problem that physically */
866 /* resetting an adapter will ever fix is when, for some reason, */
867 /* the driver is not successfully communicating with the adapter. */
868 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
869 /* then there's no real purpose in a physical reset. This will complete */
870 /* much faster and avoids any problems that might be caused by a */
871 /* physical reset ( such as having to fail all the outstanding I/O's ). */
872
873 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
874 scb = &ha->scbs[ha->max_cmds - 1];
875
876 ips_init_scb(ha, scb);
877
878 scb->timeout = ips_cmd_timeout;
879 scb->cdb[0] = IPS_CMD_FLUSH;
880
881 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
882 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
883 scb->cmd.flush_cache.state = IPS_NORM_STATE;
884 scb->cmd.flush_cache.reserved = 0;
885 scb->cmd.flush_cache.reserved2 = 0;
886 scb->cmd.flush_cache.reserved3 = 0;
887 scb->cmd.flush_cache.reserved4 = 0;
888
889 /* Attempt the flush command */
890 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
891 if (ret == IPS_SUCCESS) {
892 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
893 "Reset Request - Flushed Cache\n");
894 return (SUCCESS);
895 }
896 }
897
898 /* Either we can't communicate with the adapter or it's an IOCTL request */
899 /* from a utility. A physical reset is needed at this point. */
900
901 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
902
903 /*
904 * command must have already been sent
905 * reset the controller
906 */
907 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
908 ret = (*ha->func.reset) (ha);
909
910 if (!ret) {
911 struct scsi_cmnd *scsi_cmd;
912
913 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
914 "Controller reset failed - controller now offline.\n");
915
916 /* Now fail all of the active commands */
917 DEBUG_VAR(1, "(%s%d) Failing active commands",
918 ips_name, ha->host_num);
919
920 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
921 scb->scsi_cmd->result = DID_ERROR << 16;
922 scsi_done(scb->scsi_cmd);
923 ips_freescb(ha, scb);
924 }
925
926 /* Now fail all of the pending commands */
927 DEBUG_VAR(1, "(%s%d) Failing pending commands",
928 ips_name, ha->host_num);
929
930 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
931 scsi_cmd->result = DID_ERROR;
932 scsi_done(scsi_cmd);
933 }
934
935 ha->active = false;
936 return (FAILED);
937 }
938
939 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
940 struct scsi_cmnd *scsi_cmd;
941
942 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
943 "Controller reset failed - controller now offline.\n");
944
945 /* Now fail all of the active commands */
946 DEBUG_VAR(1, "(%s%d) Failing active commands",
947 ips_name, ha->host_num);
948
949 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
950 scb->scsi_cmd->result = DID_ERROR << 16;
951 scsi_done(scb->scsi_cmd);
952 ips_freescb(ha, scb);
953 }
954
955 /* Now fail all of the pending commands */
956 DEBUG_VAR(1, "(%s%d) Failing pending commands",
957 ips_name, ha->host_num);
958
959 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
960 scsi_cmd->result = DID_ERROR << 16;
961 scsi_done(scsi_cmd);
962 }
963
964 ha->active = false;
965 return (FAILED);
966 }
967
968 /* FFDC */
969 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
970 ha->last_ffdc = ktime_get_real_seconds();
971 ha->reset_count++;
972 ips_ffdc_reset(ha, IPS_INTR_IORL);
973 }
974
975 /* Now fail all of the active commands */
976 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
977
978 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
979 scb->scsi_cmd->result = DID_RESET << 16;
980 scsi_done(scb->scsi_cmd);
981 ips_freescb(ha, scb);
982 }
983
984 /* Reset DCDB active command bits */
985 for (i = 1; i < ha->nbus; i++)
986 ha->dcdb_active[i - 1] = 0;
987
988 /* Reset the number of active IOCTLs */
989 ha->num_ioctl = 0;
990
991 ips_next(ha, IPS_INTR_IORL);
992
993 return (SUCCESS);
994#endif /* NO_IPS_RESET */
995
996}
997
998static int ips_eh_reset(struct scsi_cmnd *SC)
999{
1000 int rc;
1001
1002 spin_lock_irq(SC->device->host->host_lock);
1003 rc = __ips_eh_reset(SC);
1004 spin_unlock_irq(SC->device->host->host_lock);
1005
1006 return rc;
1007}
1008
1009/****************************************************************************/
1010/* */
1011/* Routine Name: ips_queue */
1012/* */
1013/* Routine Description: */
1014/* */
1015/* Send a command to the controller */
1016/* */
1017/* NOTE: */
1018/* Linux obtains io_request_lock before calling this function */
1019/* */
1020/****************************************************************************/
1021static enum scsi_qc_status ips_queue_lck(struct scsi_cmnd *SC)
1022{
1023 void (*done)(struct scsi_cmnd *) = scsi_done;
1024 ips_ha_t *ha;
1025 ips_passthru_t *pt;
1026
1027 METHOD_TRACE("ips_queue", 1);
1028
1029 ha = (ips_ha_t *) SC->device->host->hostdata;
1030
1031 if (!ha)
1032 goto out_error;
1033
1034 if (!ha->active)
1035 goto out_error;
1036
1037 if (ips_is_passthru(SC)) {
1038 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1039 SC->result = DID_BUS_BUSY << 16;
1040 done(SC);
1041
1042 return (0);
1043 }
1044 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1045 SC->result = DID_BUS_BUSY << 16;
1046 done(SC);
1047
1048 return (0);
1049 }
1050
1051 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1052 ips_name,
1053 ha->host_num,
1054 SC->cmnd[0],
1055 SC->device->channel, SC->device->id, SC->device->lun);
1056
1057 /* Check for command to initiator IDs */
1058 if ((scmd_channel(SC) > 0)
1059 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1060 SC->result = DID_NO_CONNECT << 16;
1061 done(SC);
1062
1063 return (0);
1064 }
1065
1066 if (ips_is_passthru(SC)) {
1067
1068 ips_copp_wait_item_t *scratch;
1069
1070 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1071 /* There can never be any system activity ( network or disk ), but check */
1072 /* anyway just as a good practice. */
1073 pt = (ips_passthru_t *) scsi_sglist(SC);
1074 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1075 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1076 if (ha->scb_activelist.count != 0) {
1077 SC->result = DID_BUS_BUSY << 16;
1078 done(SC);
1079 return (0);
1080 }
1081 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1082 __ips_eh_reset(SC);
1083 SC->result = DID_OK << 16;
1084 scsi_done(SC);
1085 return (0);
1086 }
1087
1088 /* allocate space for the scribble */
1089 scratch = kmalloc_obj(ips_copp_wait_item_t, GFP_ATOMIC);
1090
1091 if (!scratch) {
1092 SC->result = DID_ERROR << 16;
1093 done(SC);
1094
1095 return (0);
1096 }
1097
1098 scratch->scsi_cmd = SC;
1099 scratch->next = NULL;
1100
1101 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1102 } else {
1103 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1104 }
1105
1106 ips_next(ha, IPS_INTR_IORL);
1107
1108 return (0);
1109out_error:
1110 SC->result = DID_ERROR << 16;
1111 done(SC);
1112
1113 return (0);
1114}
1115
1116static DEF_SCSI_QCMD(ips_queue)
1117
1118/****************************************************************************/
1119/* */
1120/* Routine Name: ips_biosparam */
1121/* */
1122/* Routine Description: */
1123/* */
1124/* Set bios geometry for the controller */
1125/* */
1126/****************************************************************************/
1127static int ips_biosparam(struct scsi_device *sdev, struct gendisk *unused,
1128 sector_t capacity, int geom[])
1129{
1130 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1131 int heads;
1132 int sectors;
1133 int cylinders;
1134
1135 METHOD_TRACE("ips_biosparam", 1);
1136
1137 if (!ha)
1138 /* ?!?! host adater info invalid */
1139 return (0);
1140
1141 if (!ha->active)
1142 return (0);
1143
1144 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1145 /* ?!?! Enquiry command failed */
1146 return (0);
1147
1148 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1149 heads = IPS_NORM_HEADS;
1150 sectors = IPS_NORM_SECTORS;
1151 } else {
1152 heads = IPS_COMP_HEADS;
1153 sectors = IPS_COMP_SECTORS;
1154 }
1155
1156 cylinders = (unsigned long) capacity / (heads * sectors);
1157
1158 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1159 heads, sectors, cylinders);
1160
1161 geom[0] = heads;
1162 geom[1] = sectors;
1163 geom[2] = cylinders;
1164
1165 return (0);
1166}
1167
1168/****************************************************************************/
1169/* */
1170/* Routine Name: ips_sdev_configure */
1171/* */
1172/* Routine Description: */
1173/* */
1174/* Set queue depths on devices once scan is complete */
1175/* */
1176/****************************************************************************/
1177static int
1178ips_sdev_configure(struct scsi_device *SDptr, struct queue_limits *lim)
1179{
1180 ips_ha_t *ha;
1181 int min;
1182
1183 ha = IPS_HA(SDptr->host);
1184 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1185 min = ha->max_cmds / 2;
1186 if (ha->enq->ucLogDriveCount <= 2)
1187 min = ha->max_cmds - 1;
1188 scsi_change_queue_depth(SDptr, min);
1189 }
1190
1191 SDptr->skip_ms_page_8 = 1;
1192 SDptr->skip_ms_page_3f = 1;
1193 return 0;
1194}
1195
1196/****************************************************************************/
1197/* */
1198/* Routine Name: do_ipsintr */
1199/* */
1200/* Routine Description: */
1201/* */
1202/* Wrapper for the interrupt handler */
1203/* */
1204/****************************************************************************/
1205static irqreturn_t
1206do_ipsintr(int irq, void *dev_id)
1207{
1208 ips_ha_t *ha;
1209 struct Scsi_Host *host;
1210 int irqstatus;
1211
1212 METHOD_TRACE("do_ipsintr", 2);
1213
1214 ha = (ips_ha_t *) dev_id;
1215 if (!ha)
1216 return IRQ_NONE;
1217 host = ips_sh[ha->host_num];
1218 /* interrupt during initialization */
1219 if (!host) {
1220 (*ha->func.intr) (ha);
1221 return IRQ_HANDLED;
1222 }
1223
1224 spin_lock(host->host_lock);
1225
1226 if (!ha->active) {
1227 spin_unlock(host->host_lock);
1228 return IRQ_HANDLED;
1229 }
1230
1231 irqstatus = (*ha->func.intr) (ha);
1232
1233 spin_unlock(host->host_lock);
1234
1235 /* start the next command */
1236 ips_next(ha, IPS_INTR_ON);
1237 return IRQ_RETVAL(irqstatus);
1238}
1239
1240/****************************************************************************/
1241/* */
1242/* Routine Name: ips_intr_copperhead */
1243/* */
1244/* Routine Description: */
1245/* */
1246/* Polling interrupt handler */
1247/* */
1248/* ASSUMES interrupts are disabled */
1249/* */
1250/****************************************************************************/
1251int
1252ips_intr_copperhead(ips_ha_t * ha)
1253{
1254 ips_stat_t *sp;
1255 ips_scb_t *scb;
1256 IPS_STATUS cstatus;
1257 int intrstatus;
1258
1259 METHOD_TRACE("ips_intr", 2);
1260
1261 if (!ha)
1262 return 0;
1263
1264 if (!ha->active)
1265 return 0;
1266
1267 intrstatus = (*ha->func.isintr) (ha);
1268
1269 if (!intrstatus) {
1270 /*
1271 * Unexpected/Shared interrupt
1272 */
1273
1274 return 0;
1275 }
1276
1277 while (true) {
1278 sp = &ha->sp;
1279
1280 intrstatus = (*ha->func.isintr) (ha);
1281
1282 if (!intrstatus)
1283 break;
1284 else
1285 cstatus.value = (*ha->func.statupd) (ha);
1286
1287 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1288 /* Spurious Interrupt ? */
1289 continue;
1290 }
1291
1292 ips_chkstatus(ha, &cstatus);
1293 scb = (ips_scb_t *) sp->scb_addr;
1294
1295 /*
1296 * use the callback function to finish things up
1297 * NOTE: interrupts are OFF for this
1298 */
1299 (*scb->callback) (ha, scb);
1300 } /* end while */
1301 return 1;
1302}
1303
1304/****************************************************************************/
1305/* */
1306/* Routine Name: ips_intr_morpheus */
1307/* */
1308/* Routine Description: */
1309/* */
1310/* Polling interrupt handler */
1311/* */
1312/* ASSUMES interrupts are disabled */
1313/* */
1314/****************************************************************************/
1315int
1316ips_intr_morpheus(ips_ha_t * ha)
1317{
1318 ips_stat_t *sp;
1319 ips_scb_t *scb;
1320 IPS_STATUS cstatus;
1321 int intrstatus;
1322
1323 METHOD_TRACE("ips_intr_morpheus", 2);
1324
1325 if (!ha)
1326 return 0;
1327
1328 if (!ha->active)
1329 return 0;
1330
1331 intrstatus = (*ha->func.isintr) (ha);
1332
1333 if (!intrstatus) {
1334 /*
1335 * Unexpected/Shared interrupt
1336 */
1337
1338 return 0;
1339 }
1340
1341 while (true) {
1342 sp = &ha->sp;
1343
1344 intrstatus = (*ha->func.isintr) (ha);
1345
1346 if (!intrstatus)
1347 break;
1348 else
1349 cstatus.value = (*ha->func.statupd) (ha);
1350
1351 if (cstatus.value == 0xffffffff)
1352 /* No more to process */
1353 break;
1354
1355 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1356 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1357 "Spurious interrupt; no ccb.\n");
1358
1359 continue;
1360 }
1361
1362 ips_chkstatus(ha, &cstatus);
1363 scb = (ips_scb_t *) sp->scb_addr;
1364
1365 /*
1366 * use the callback function to finish things up
1367 * NOTE: interrupts are OFF for this
1368 */
1369 (*scb->callback) (ha, scb);
1370 } /* end while */
1371 return 1;
1372}
1373
1374/****************************************************************************/
1375/* */
1376/* Routine Name: ips_info */
1377/* */
1378/* Routine Description: */
1379/* */
1380/* Return info about the driver */
1381/* */
1382/****************************************************************************/
1383static const char *
1384ips_info(struct Scsi_Host *SH)
1385{
1386 static char buffer[256];
1387 char *bp;
1388 ips_ha_t *ha;
1389
1390 METHOD_TRACE("ips_info", 1);
1391
1392 ha = IPS_HA(SH);
1393
1394 if (!ha)
1395 return (NULL);
1396
1397 bp = &buffer[0];
1398 memset(bp, 0, sizeof (buffer));
1399
1400 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1401 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1402
1403 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1404 strcat(bp, " <");
1405 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1406 strcat(bp, ">");
1407 }
1408
1409 return (bp);
1410}
1411
1412static int
1413ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1414{
1415 int i;
1416 ips_ha_t *ha = NULL;
1417
1418 /* Find our host structure */
1419 for (i = 0; i < ips_next_controller; i++) {
1420 if (ips_sh[i]) {
1421 if (ips_sh[i] == host) {
1422 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1423 break;
1424 }
1425 }
1426 }
1427
1428 if (!ha)
1429 return (-EINVAL);
1430
1431 return 0;
1432}
1433
1434static int
1435ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1436{
1437 int i;
1438 ips_ha_t *ha = NULL;
1439
1440 /* Find our host structure */
1441 for (i = 0; i < ips_next_controller; i++) {
1442 if (ips_sh[i]) {
1443 if (ips_sh[i] == host) {
1444 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1445 break;
1446 }
1447 }
1448 }
1449
1450 if (!ha)
1451 return (-EINVAL);
1452
1453 return ips_host_info(ha, m);
1454}
1455
1456/*--------------------------------------------------------------------------*/
1457/* Helper Functions */
1458/*--------------------------------------------------------------------------*/
1459
1460/****************************************************************************/
1461/* */
1462/* Routine Name: ips_is_passthru */
1463/* */
1464/* Routine Description: */
1465/* */
1466/* Determine if the specified SCSI command is really a passthru command */
1467/* */
1468/****************************************************************************/
1469static int ips_is_passthru(struct scsi_cmnd *SC)
1470{
1471 unsigned long flags;
1472
1473 METHOD_TRACE("ips_is_passthru", 1);
1474
1475 if (!SC)
1476 return (0);
1477
1478 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1479 (SC->device->channel == 0) &&
1480 (SC->device->id == IPS_ADAPTER_ID) &&
1481 (SC->device->lun == 0) && scsi_sglist(SC)) {
1482 struct scatterlist *sg = scsi_sglist(SC);
1483 char *buffer;
1484
1485 /* local_irq_save() protects the KM_IRQ0 address slot. */
1486 local_irq_save(flags);
1487 buffer = kmap_local_page(sg_page(sg)) + sg->offset;
1488 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1489 buffer[2] == 'P' && buffer[3] == 'P') {
1490 kunmap_local(buffer);
1491 local_irq_restore(flags);
1492 return 1;
1493 }
1494 kunmap_local(buffer);
1495 local_irq_restore(flags);
1496 }
1497 return 0;
1498}
1499
1500/****************************************************************************/
1501/* */
1502/* Routine Name: ips_alloc_passthru_buffer */
1503/* */
1504/* Routine Description: */
1505/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1506/* is too small or doesn't exist */
1507/****************************************************************************/
1508static int
1509ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1510{
1511 void *bigger_buf;
1512 dma_addr_t dma_busaddr;
1513
1514 if (ha->ioctl_data && length <= ha->ioctl_len)
1515 return 0;
1516 /* there is no buffer or it's not big enough, allocate a new one */
1517 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr,
1518 GFP_KERNEL);
1519 if (bigger_buf) {
1520 /* free the old memory */
1521 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
1522 ha->ioctl_data, ha->ioctl_busaddr);
1523 /* use the new memory */
1524 ha->ioctl_data = (char *) bigger_buf;
1525 ha->ioctl_len = length;
1526 ha->ioctl_busaddr = dma_busaddr;
1527 } else {
1528 return -1;
1529 }
1530 return 0;
1531}
1532
1533/****************************************************************************/
1534/* */
1535/* Routine Name: ips_make_passthru */
1536/* */
1537/* Routine Description: */
1538/* */
1539/* Make a passthru command out of the info in the Scsi block */
1540/* */
1541/****************************************************************************/
1542static int
1543ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1544{
1545 ips_passthru_t *pt;
1546 int length = 0;
1547 int i, ret;
1548 struct scatterlist *sg = scsi_sglist(SC);
1549
1550 METHOD_TRACE("ips_make_passthru", 1);
1551
1552 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1553 length += sg->length;
1554
1555 if (length < sizeof (ips_passthru_t)) {
1556 /* wrong size */
1557 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1558 ips_name, ha->host_num);
1559 return (IPS_FAILURE);
1560 }
1561 if (ips_alloc_passthru_buffer(ha, length)) {
1562 /* allocation failure! If ha->ioctl_data exists, use it to return
1563 some error codes. Return a failed command to the scsi layer. */
1564 if (ha->ioctl_data) {
1565 pt = (ips_passthru_t *) ha->ioctl_data;
1566 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1567 pt->BasicStatus = 0x0B;
1568 pt->ExtendedStatus = 0x00;
1569 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1570 }
1571 return IPS_FAILURE;
1572 }
1573 ha->ioctl_datasize = length;
1574
1575 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1576 pt = (ips_passthru_t *) ha->ioctl_data;
1577
1578 /*
1579 * Some notes about the passthru interface used
1580 *
1581 * IF the scsi op_code == 0x0d then we assume
1582 * that the data came along with/goes with the
1583 * packet we received from the sg driver. In this
1584 * case the CmdBSize field of the pt structure is
1585 * used for the size of the buffer.
1586 */
1587
1588 switch (pt->CoppCmd) {
1589 case IPS_NUMCTRLS:
1590 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1591 &ips_num_controllers, sizeof (int));
1592 ips_scmd_buf_write(SC, ha->ioctl_data,
1593 sizeof (ips_passthru_t) + sizeof (int));
1594 SC->result = DID_OK << 16;
1595
1596 return (IPS_SUCCESS_IMM);
1597
1598 case IPS_COPPUSRCMD:
1599 case IPS_COPPIOCCMD:
1600 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1601 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1602 /* wrong size */
1603 DEBUG_VAR(1,
1604 "(%s%d) Passthru structure wrong size",
1605 ips_name, ha->host_num);
1606
1607 return (IPS_FAILURE);
1608 }
1609
1610 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1611 pt->CoppCP.cmd.flashfw.op_code ==
1612 IPS_CMD_RW_BIOSFW) {
1613 ret = ips_flash_copperhead(ha, pt, scb);
1614 ips_scmd_buf_write(SC, ha->ioctl_data,
1615 sizeof (ips_passthru_t));
1616 return ret;
1617 }
1618 if (ips_usrcmd(ha, pt, scb))
1619 return (IPS_SUCCESS);
1620 else
1621 return (IPS_FAILURE);
1622 }
1623
1624 break;
1625
1626 } /* end switch */
1627
1628 return (IPS_FAILURE);
1629}
1630
1631/****************************************************************************/
1632/* Routine Name: ips_flash_copperhead */
1633/* Routine Description: */
1634/* Flash the BIOS/FW on a Copperhead style controller */
1635/****************************************************************************/
1636static int
1637ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1638{
1639 int datasize;
1640
1641 /* Trombone is the only copperhead that can do packet flash, but only
1642 * for firmware. No one said it had to make sense. */
1643 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1644 if (ips_usrcmd(ha, pt, scb))
1645 return IPS_SUCCESS;
1646 else
1647 return IPS_FAILURE;
1648 }
1649 pt->BasicStatus = 0x0B;
1650 pt->ExtendedStatus = 0;
1651 scb->scsi_cmd->result = DID_OK << 16;
1652 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1653 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1654 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1655 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1656 pt->BasicStatus = 0;
1657 return ips_flash_bios(ha, pt, scb);
1658 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1659 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1660 ha->flash_data = ips_FlashData;
1661 ha->flash_busaddr = ips_flashbusaddr;
1662 ha->flash_len = PAGE_SIZE << 7;
1663 ha->flash_datasize = 0;
1664 } else if (!ha->flash_data) {
1665 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1666 pt->CoppCP.cmd.flashfw.count;
1667 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev,
1668 datasize, &ha->flash_busaddr, GFP_KERNEL);
1669 if (!ha->flash_data){
1670 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1671 return IPS_FAILURE;
1672 }
1673 ha->flash_datasize = 0;
1674 ha->flash_len = datasize;
1675 } else
1676 return IPS_FAILURE;
1677 } else {
1678 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1679 ha->flash_len) {
1680 ips_free_flash_copperhead(ha);
1681 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1682 "failed size sanity check\n");
1683 return IPS_FAILURE;
1684 }
1685 }
1686 if (!ha->flash_data)
1687 return IPS_FAILURE;
1688 pt->BasicStatus = 0;
1689 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1690 pt->CoppCP.cmd.flashfw.count);
1691 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1692 if (pt->CoppCP.cmd.flashfw.packet_num ==
1693 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1694 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1695 return ips_flash_bios(ha, pt, scb);
1696 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1697 return ips_flash_firmware(ha, pt, scb);
1698 }
1699 return IPS_SUCCESS_IMM;
1700}
1701
1702/****************************************************************************/
1703/* Routine Name: ips_flash_bios */
1704/* Routine Description: */
1705/* flashes the bios of a copperhead adapter */
1706/****************************************************************************/
1707static int
1708ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1709{
1710
1711 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1712 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1713 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1714 (!ha->func.verifybios))
1715 goto error;
1716 if ((*ha->func.erasebios) (ha)) {
1717 DEBUG_VAR(1,
1718 "(%s%d) flash bios failed - unable to erase flash",
1719 ips_name, ha->host_num);
1720 goto error;
1721 } else
1722 if ((*ha->func.programbios) (ha,
1723 ha->flash_data +
1724 IPS_BIOS_HEADER,
1725 ha->flash_datasize -
1726 IPS_BIOS_HEADER, 0)) {
1727 DEBUG_VAR(1,
1728 "(%s%d) flash bios failed - unable to flash",
1729 ips_name, ha->host_num);
1730 goto error;
1731 } else
1732 if ((*ha->func.verifybios) (ha,
1733 ha->flash_data +
1734 IPS_BIOS_HEADER,
1735 ha->flash_datasize -
1736 IPS_BIOS_HEADER, 0)) {
1737 DEBUG_VAR(1,
1738 "(%s%d) flash bios failed - unable to verify flash",
1739 ips_name, ha->host_num);
1740 goto error;
1741 }
1742 ips_free_flash_copperhead(ha);
1743 return IPS_SUCCESS_IMM;
1744 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1745 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1746 if (!ha->func.erasebios)
1747 goto error;
1748 if ((*ha->func.erasebios) (ha)) {
1749 DEBUG_VAR(1,
1750 "(%s%d) flash bios failed - unable to erase flash",
1751 ips_name, ha->host_num);
1752 goto error;
1753 }
1754 return IPS_SUCCESS_IMM;
1755 }
1756 error:
1757 pt->BasicStatus = 0x0B;
1758 pt->ExtendedStatus = 0x00;
1759 ips_free_flash_copperhead(ha);
1760 return IPS_FAILURE;
1761}
1762
1763/****************************************************************************/
1764/* */
1765/* Routine Name: ips_fill_scb_sg_single */
1766/* */
1767/* Routine Description: */
1768/* Fill in a single scb sg_list element from an address */
1769/* return a -1 if a breakup occurred */
1770/****************************************************************************/
1771static int
1772ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1773 ips_scb_t * scb, int indx, unsigned int e_len)
1774{
1775
1776 int ret_val = 0;
1777
1778 if ((scb->data_len + e_len) > ha->max_xfer) {
1779 e_len = ha->max_xfer - scb->data_len;
1780 scb->breakup = indx;
1781 ++scb->sg_break;
1782 ret_val = -1;
1783 } else {
1784 scb->breakup = 0;
1785 scb->sg_break = 0;
1786 }
1787 if (IPS_USE_ENH_SGLIST(ha)) {
1788 scb->sg_list.enh_list[indx].address_lo =
1789 cpu_to_le32(lower_32_bits(busaddr));
1790 scb->sg_list.enh_list[indx].address_hi =
1791 cpu_to_le32(upper_32_bits(busaddr));
1792 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1793 } else {
1794 scb->sg_list.std_list[indx].address =
1795 cpu_to_le32(lower_32_bits(busaddr));
1796 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1797 }
1798
1799 ++scb->sg_len;
1800 scb->data_len += e_len;
1801 return ret_val;
1802}
1803
1804/****************************************************************************/
1805/* Routine Name: ips_flash_firmware */
1806/* Routine Description: */
1807/* flashes the firmware of a copperhead adapter */
1808/****************************************************************************/
1809static int
1810ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1811{
1812 IPS_SG_LIST sg_list;
1813 uint32_t cmd_busaddr;
1814
1815 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1816 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1817 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1818 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1819 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1820 } else {
1821 pt->BasicStatus = 0x0B;
1822 pt->ExtendedStatus = 0x00;
1823 ips_free_flash_copperhead(ha);
1824 return IPS_FAILURE;
1825 }
1826 /* Save the S/G list pointer so it doesn't get clobbered */
1827 sg_list.list = scb->sg_list.list;
1828 cmd_busaddr = scb->scb_busaddr;
1829 /* copy in the CP */
1830 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1831 /* FIX stuff that might be wrong */
1832 scb->sg_list.list = sg_list.list;
1833 scb->scb_busaddr = cmd_busaddr;
1834 scb->bus = scb->scsi_cmd->device->channel;
1835 scb->target_id = scb->scsi_cmd->device->id;
1836 scb->lun = scb->scsi_cmd->device->lun;
1837 scb->sg_len = 0;
1838 scb->data_len = 0;
1839 scb->flags = 0;
1840 scb->op_code = 0;
1841 scb->callback = ipsintr_done;
1842 scb->timeout = ips_cmd_timeout;
1843
1844 scb->data_len = ha->flash_datasize;
1845 scb->data_busaddr =
1846 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len,
1847 IPS_DMA_DIR(scb));
1848 scb->flags |= IPS_SCB_MAP_SINGLE;
1849 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1850 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1851 if (pt->TimeOut)
1852 scb->timeout = pt->TimeOut;
1853 scb->scsi_cmd->result = DID_OK << 16;
1854 return IPS_SUCCESS;
1855}
1856
1857/****************************************************************************/
1858/* Routine Name: ips_free_flash_copperhead */
1859/* Routine Description: */
1860/* release the memory resources used to hold the flash image */
1861/****************************************************************************/
1862static void
1863ips_free_flash_copperhead(ips_ha_t * ha)
1864{
1865 if (ha->flash_data == ips_FlashData)
1866 test_and_clear_bit(0, &ips_FlashDataInUse);
1867 else if (ha->flash_data)
1868 dma_free_coherent(&ha->pcidev->dev, ha->flash_len,
1869 ha->flash_data, ha->flash_busaddr);
1870 ha->flash_data = NULL;
1871}
1872
1873/****************************************************************************/
1874/* */
1875/* Routine Name: ips_usrcmd */
1876/* */
1877/* Routine Description: */
1878/* */
1879/* Process a user command and make it ready to send */
1880/* */
1881/****************************************************************************/
1882static int
1883ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1884{
1885 IPS_SG_LIST sg_list;
1886 uint32_t cmd_busaddr;
1887
1888 METHOD_TRACE("ips_usrcmd", 1);
1889
1890 if ((!scb) || (!pt) || (!ha))
1891 return (0);
1892
1893 /* Save the S/G list pointer so it doesn't get clobbered */
1894 sg_list.list = scb->sg_list.list;
1895 cmd_busaddr = scb->scb_busaddr;
1896 /* copy in the CP */
1897 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1898 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1899
1900 /* FIX stuff that might be wrong */
1901 scb->sg_list.list = sg_list.list;
1902 scb->scb_busaddr = cmd_busaddr;
1903 scb->bus = scb->scsi_cmd->device->channel;
1904 scb->target_id = scb->scsi_cmd->device->id;
1905 scb->lun = scb->scsi_cmd->device->lun;
1906 scb->sg_len = 0;
1907 scb->data_len = 0;
1908 scb->flags = 0;
1909 scb->op_code = 0;
1910 scb->callback = ipsintr_done;
1911 scb->timeout = ips_cmd_timeout;
1912 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1913
1914 /* we don't support DCDB/READ/WRITE Scatter Gather */
1915 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1916 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1917 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1918 return (0);
1919
1920 if (pt->CmdBSize) {
1921 scb->data_len = pt->CmdBSize;
1922 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1923 } else {
1924 scb->data_busaddr = 0L;
1925 }
1926
1927 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1928 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1929 (unsigned long) &scb->
1930 dcdb -
1931 (unsigned long) scb);
1932
1933 if (pt->CmdBSize) {
1934 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1935 scb->dcdb.buffer_pointer =
1936 cpu_to_le32(scb->data_busaddr);
1937 else
1938 scb->cmd.basic_io.sg_addr =
1939 cpu_to_le32(scb->data_busaddr);
1940 }
1941
1942 /* set timeouts */
1943 if (pt->TimeOut) {
1944 scb->timeout = pt->TimeOut;
1945
1946 if (pt->TimeOut <= 10)
1947 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1948 else if (pt->TimeOut <= 60)
1949 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1950 else
1951 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1952 }
1953
1954 /* assume success */
1955 scb->scsi_cmd->result = DID_OK << 16;
1956
1957 /* success */
1958 return (1);
1959}
1960
1961/****************************************************************************/
1962/* */
1963/* Routine Name: ips_cleanup_passthru */
1964/* */
1965/* Routine Description: */
1966/* */
1967/* Cleanup after a passthru command */
1968/* */
1969/****************************************************************************/
1970static void
1971ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1972{
1973 ips_passthru_t *pt;
1974
1975 METHOD_TRACE("ips_cleanup_passthru", 1);
1976
1977 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
1978 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
1979 ips_name, ha->host_num);
1980
1981 return;
1982 }
1983 pt = (ips_passthru_t *) ha->ioctl_data;
1984
1985 /* Copy data back to the user */
1986 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
1987 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
1988
1989 pt->BasicStatus = scb->basic_status;
1990 pt->ExtendedStatus = scb->extended_status;
1991 pt->AdapterType = ha->ad_type;
1992
1993 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1994 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
1995 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
1996 ips_free_flash_copperhead(ha);
1997
1998 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
1999}
2000
2001/****************************************************************************/
2002/* */
2003/* Routine Name: ips_host_info */
2004/* */
2005/* Routine Description: */
2006/* */
2007/* The passthru interface for the driver */
2008/* */
2009/****************************************************************************/
2010static int
2011ips_host_info(ips_ha_t *ha, struct seq_file *m)
2012{
2013 METHOD_TRACE("ips_host_info", 1);
2014
2015 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2016
2017 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2018 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2019 seq_printf(m, "\tController Type : %s\n",
2020 ips_adapter_name[ha->ad_type - 1]);
2021 else
2022 seq_puts(m, "\tController Type : Unknown\n");
2023
2024 if (ha->io_addr)
2025 seq_printf(m,
2026 "\tIO region : 0x%x (%d bytes)\n",
2027 ha->io_addr, ha->io_len);
2028
2029 if (ha->mem_addr) {
2030 seq_printf(m,
2031 "\tMemory region : 0x%x (%d bytes)\n",
2032 ha->mem_addr, ha->mem_len);
2033 seq_printf(m,
2034 "\tShared memory address : 0x%lx\n",
2035 (unsigned long)ha->mem_ptr);
2036 }
2037
2038 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2039
2040 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2041 /* That keeps everything happy for "text" operations on the proc file. */
2042
2043 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2044 if (ha->nvram->bios_low[3] == 0) {
2045 seq_printf(m,
2046 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2047 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2048 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2049 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2050 ha->nvram->bios_low[2]);
2051
2052 } else {
2053 seq_printf(m,
2054 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2055 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2056 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2057 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2058 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2059 }
2060
2061 }
2062
2063 if (ha->enq->CodeBlkVersion[7] == 0) {
2064 seq_printf(m,
2065 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2066 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2067 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2068 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2069 ha->enq->CodeBlkVersion[6]);
2070 } else {
2071 seq_printf(m,
2072 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2073 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2074 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2075 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2076 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2077 }
2078
2079 if (ha->enq->BootBlkVersion[7] == 0) {
2080 seq_printf(m,
2081 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2082 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2083 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2084 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2085 ha->enq->BootBlkVersion[6]);
2086 } else {
2087 seq_printf(m,
2088 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2089 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2090 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2091 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2092 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2093 }
2094
2095 seq_printf(m, "\tDriver Version : %s%s\n",
2096 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2097
2098 seq_printf(m, "\tDriver Build : %d\n",
2099 IPS_BUILD_IDENT);
2100
2101 seq_printf(m, "\tMax Physical Devices : %d\n",
2102 ha->enq->ucMaxPhysicalDevices);
2103 seq_printf(m, "\tMax Active Commands : %d\n",
2104 ha->max_cmds);
2105 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2106 ha->scb_waitlist.count);
2107 seq_printf(m, "\tCurrent Active Commands : %d\n",
2108 ha->scb_activelist.count - ha->num_ioctl);
2109 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2110 ha->copp_waitlist.count);
2111 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2112 ha->num_ioctl);
2113
2114 seq_putc(m, '\n');
2115
2116 return 0;
2117}
2118
2119/****************************************************************************/
2120/* */
2121/* Routine Name: ips_identify_controller */
2122/* */
2123/* Routine Description: */
2124/* */
2125/* Identify this controller */
2126/* */
2127/****************************************************************************/
2128static void
2129ips_identify_controller(ips_ha_t * ha)
2130{
2131 METHOD_TRACE("ips_identify_controller", 1);
2132
2133 switch (ha->pcidev->device) {
2134 case IPS_DEVICEID_COPPERHEAD:
2135 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2136 ha->ad_type = IPS_ADTYPE_SERVERAID;
2137 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2138 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2139 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2140 ha->ad_type = IPS_ADTYPE_NAVAJO;
2141 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2142 && (ha->slot_num == 0)) {
2143 ha->ad_type = IPS_ADTYPE_KIOWA;
2144 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2145 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2146 if (ha->enq->ucMaxPhysicalDevices == 15)
2147 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2148 else
2149 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2150 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2151 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2152 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2153 }
2154 break;
2155
2156 case IPS_DEVICEID_MORPHEUS:
2157 switch (ha->pcidev->subsystem_device) {
2158 case IPS_SUBDEVICEID_4L:
2159 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2160 break;
2161
2162 case IPS_SUBDEVICEID_4M:
2163 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2164 break;
2165
2166 case IPS_SUBDEVICEID_4MX:
2167 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2168 break;
2169
2170 case IPS_SUBDEVICEID_4LX:
2171 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2172 break;
2173
2174 case IPS_SUBDEVICEID_5I2:
2175 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2176 break;
2177
2178 case IPS_SUBDEVICEID_5I1:
2179 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2180 break;
2181 }
2182
2183 break;
2184
2185 case IPS_DEVICEID_MARCO:
2186 switch (ha->pcidev->subsystem_device) {
2187 case IPS_SUBDEVICEID_6M:
2188 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2189 break;
2190 case IPS_SUBDEVICEID_6I:
2191 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2192 break;
2193 case IPS_SUBDEVICEID_7k:
2194 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2195 break;
2196 case IPS_SUBDEVICEID_7M:
2197 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2198 break;
2199 }
2200 break;
2201 }
2202}
2203
2204/****************************************************************************/
2205/* */
2206/* Routine Name: ips_get_bios_version */
2207/* */
2208/* Routine Description: */
2209/* */
2210/* Get the BIOS revision number */
2211/* */
2212/****************************************************************************/
2213static void
2214ips_get_bios_version(ips_ha_t * ha, int intr)
2215{
2216 ips_scb_t *scb;
2217 int ret;
2218 uint8_t major;
2219 uint8_t minor;
2220 uint8_t subminor;
2221 uint8_t *buffer;
2222
2223 METHOD_TRACE("ips_get_bios_version", 1);
2224
2225 major = 0;
2226 minor = 0;
2227
2228 memcpy(ha->bios_version, " ?", 8);
2229
2230 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2231 if (IPS_USE_MEMIO(ha)) {
2232 /* Memory Mapped I/O */
2233
2234 /* test 1st byte */
2235 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2236 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2237 udelay(25); /* 25 us */
2238
2239 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2240 return;
2241
2242 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2243 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2244 udelay(25); /* 25 us */
2245
2246 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2247 return;
2248
2249 /* Get Major version */
2250 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2251 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2252 udelay(25); /* 25 us */
2253
2254 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2255
2256 /* Get Minor version */
2257 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2258 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2259 udelay(25); /* 25 us */
2260 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2261
2262 /* Get SubMinor version */
2263 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2264 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2265 udelay(25); /* 25 us */
2266 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2267
2268 } else {
2269 /* Programmed I/O */
2270
2271 /* test 1st byte */
2272 outl(0, ha->io_addr + IPS_REG_FLAP);
2273 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2274 udelay(25); /* 25 us */
2275
2276 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2277 return;
2278
2279 outl(1, ha->io_addr + IPS_REG_FLAP);
2280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2281 udelay(25); /* 25 us */
2282
2283 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2284 return;
2285
2286 /* Get Major version */
2287 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2288 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2289 udelay(25); /* 25 us */
2290
2291 major = inb(ha->io_addr + IPS_REG_FLDP);
2292
2293 /* Get Minor version */
2294 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2295 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2296 udelay(25); /* 25 us */
2297
2298 minor = inb(ha->io_addr + IPS_REG_FLDP);
2299
2300 /* Get SubMinor version */
2301 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2303 udelay(25); /* 25 us */
2304
2305 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2306
2307 }
2308 } else {
2309 /* Morpheus Family - Send Command to the card */
2310
2311 buffer = ha->ioctl_data;
2312
2313 memset(buffer, 0, 0x1000);
2314
2315 scb = &ha->scbs[ha->max_cmds - 1];
2316
2317 ips_init_scb(ha, scb);
2318
2319 scb->timeout = ips_cmd_timeout;
2320 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2321
2322 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2323 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2324 scb->cmd.flashfw.type = 1;
2325 scb->cmd.flashfw.direction = 0;
2326 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2327 scb->cmd.flashfw.total_packets = 1;
2328 scb->cmd.flashfw.packet_num = 0;
2329 scb->data_len = 0x1000;
2330 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2331
2332 /* issue the command */
2333 if (((ret =
2334 ips_send_wait(ha, scb, ips_cmd_timeout,
2335 intr)) == IPS_FAILURE)
2336 || (ret == IPS_SUCCESS_IMM)
2337 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2338 /* Error occurred */
2339
2340 return;
2341 }
2342
2343 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2344 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2345 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2346 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2347 } else {
2348 return;
2349 }
2350 }
2351
2352 ha->bios_version[0] = hex_asc_upper_hi(major);
2353 ha->bios_version[1] = '.';
2354 ha->bios_version[2] = hex_asc_upper_lo(major);
2355 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2356 ha->bios_version[4] = '.';
2357 ha->bios_version[5] = hex_asc_upper_hi(minor);
2358 ha->bios_version[6] = hex_asc_upper_lo(minor);
2359 ha->bios_version[7] = 0;
2360}
2361
2362/****************************************************************************/
2363/* */
2364/* Routine Name: ips_hainit */
2365/* */
2366/* Routine Description: */
2367/* */
2368/* Initialize the controller */
2369/* */
2370/* NOTE: Assumes to be called from with a lock */
2371/* */
2372/****************************************************************************/
2373static int
2374ips_hainit(ips_ha_t * ha)
2375{
2376 int i;
2377
2378 METHOD_TRACE("ips_hainit", 1);
2379
2380 if (!ha)
2381 return (0);
2382
2383 if (ha->func.statinit)
2384 (*ha->func.statinit) (ha);
2385
2386 if (ha->func.enableint)
2387 (*ha->func.enableint) (ha);
2388
2389 /* Send FFDC */
2390 ha->reset_count = 1;
2391 ha->last_ffdc = ktime_get_real_seconds();
2392 ips_ffdc_reset(ha, IPS_INTR_IORL);
2393
2394 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2395 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2396 "unable to read config from controller.\n");
2397
2398 return (0);
2399 }
2400 /* end if */
2401 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2402 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2403 "unable to read controller status.\n");
2404
2405 return (0);
2406 }
2407
2408 /* Identify this controller */
2409 ips_identify_controller(ha);
2410
2411 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2412 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2413 "unable to read subsystem parameters.\n");
2414
2415 return (0);
2416 }
2417
2418 /* write nvram user page 5 */
2419 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2420 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2421 "unable to write driver info to controller.\n");
2422
2423 return (0);
2424 }
2425
2426 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2427 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2428 ips_clear_adapter(ha, IPS_INTR_IORL);
2429
2430 /* set limits on SID, LUN, BUS */
2431 ha->ntargets = IPS_MAX_TARGETS + 1;
2432 ha->nlun = 1;
2433 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2434
2435 switch (ha->conf->logical_drive[0].ucStripeSize) {
2436 case 4:
2437 ha->max_xfer = 0x10000;
2438 break;
2439
2440 case 5:
2441 ha->max_xfer = 0x20000;
2442 break;
2443
2444 case 6:
2445 ha->max_xfer = 0x40000;
2446 break;
2447
2448 case 7:
2449 default:
2450 ha->max_xfer = 0x80000;
2451 break;
2452 }
2453
2454 /* setup max concurrent commands */
2455 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2456 /* Use the new method */
2457 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2458 } else {
2459 /* use the old method */
2460 switch (ha->conf->logical_drive[0].ucStripeSize) {
2461 case 4:
2462 ha->max_cmds = 32;
2463 break;
2464
2465 case 5:
2466 ha->max_cmds = 16;
2467 break;
2468
2469 case 6:
2470 ha->max_cmds = 8;
2471 break;
2472
2473 case 7:
2474 default:
2475 ha->max_cmds = 4;
2476 break;
2477 }
2478 }
2479
2480 /* Limit the Active Commands on a Lite Adapter */
2481 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2482 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2483 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2484 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2485 ha->max_cmds = MaxLiteCmds;
2486 }
2487
2488 /* set controller IDs */
2489 ha->ha_id[0] = IPS_ADAPTER_ID;
2490 for (i = 1; i < ha->nbus; i++) {
2491 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2492 ha->dcdb_active[i - 1] = 0;
2493 }
2494
2495 return (1);
2496}
2497
2498/****************************************************************************/
2499/* */
2500/* Routine Name: ips_next */
2501/* */
2502/* Routine Description: */
2503/* */
2504/* Take the next command off the queue and send it to the controller */
2505/* */
2506/****************************************************************************/
2507static void
2508ips_next(ips_ha_t * ha, int intr)
2509{
2510 ips_scb_t *scb;
2511 struct scsi_cmnd *SC;
2512 struct scsi_cmnd *p;
2513 struct scsi_cmnd *q;
2514 ips_copp_wait_item_t *item;
2515 int ret;
2516 struct Scsi_Host *host;
2517 METHOD_TRACE("ips_next", 1);
2518
2519 if (!ha)
2520 return;
2521 host = ips_sh[ha->host_num];
2522 /*
2523 * Block access to the queue function so
2524 * this command won't time out
2525 */
2526 if (intr == IPS_INTR_ON)
2527 spin_lock(host->host_lock);
2528
2529 if ((ha->subsys->param[3] & 0x300000)
2530 && (ha->scb_activelist.count == 0)) {
2531 time64_t now = ktime_get_real_seconds();
2532 if (now - ha->last_ffdc > IPS_SECS_8HOURS) {
2533 ha->last_ffdc = now;
2534 ips_ffdc_time(ha);
2535 }
2536 }
2537
2538 /*
2539 * Send passthru commands
2540 * These have priority over normal I/O
2541 * but shouldn't affect performance too much
2542 * since we limit the number that can be active
2543 * on the card at any one time
2544 */
2545 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2546 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2547
2548 item = ips_removeq_copp_head(&ha->copp_waitlist);
2549 ha->num_ioctl++;
2550 if (intr == IPS_INTR_ON)
2551 spin_unlock(host->host_lock);
2552 scb->scsi_cmd = item->scsi_cmd;
2553 kfree(item);
2554
2555 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2556
2557 if (intr == IPS_INTR_ON)
2558 spin_lock(host->host_lock);
2559 switch (ret) {
2560 case IPS_FAILURE:
2561 if (scb->scsi_cmd) {
2562 scb->scsi_cmd->result = DID_ERROR << 16;
2563 scsi_done(scb->scsi_cmd);
2564 }
2565
2566 ips_freescb(ha, scb);
2567 break;
2568 case IPS_SUCCESS_IMM:
2569 if (scb->scsi_cmd) {
2570 scb->scsi_cmd->result = DID_OK << 16;
2571 scsi_done(scb->scsi_cmd);
2572 }
2573
2574 ips_freescb(ha, scb);
2575 break;
2576 default:
2577 break;
2578 } /* end case */
2579
2580 if (ret != IPS_SUCCESS) {
2581 ha->num_ioctl--;
2582 continue;
2583 }
2584
2585 ret = ips_send_cmd(ha, scb);
2586
2587 if (ret == IPS_SUCCESS)
2588 ips_putq_scb_head(&ha->scb_activelist, scb);
2589 else
2590 ha->num_ioctl--;
2591
2592 switch (ret) {
2593 case IPS_FAILURE:
2594 if (scb->scsi_cmd) {
2595 scb->scsi_cmd->result = DID_ERROR << 16;
2596 }
2597
2598 ips_freescb(ha, scb);
2599 break;
2600 case IPS_SUCCESS_IMM:
2601 ips_freescb(ha, scb);
2602 break;
2603 default:
2604 break;
2605 } /* end case */
2606
2607 }
2608
2609 /*
2610 * Send "Normal" I/O commands
2611 */
2612
2613 p = ha->scb_waitlist.head;
2614 while ((p) && (scb = ips_getscb(ha))) {
2615 if ((scmd_channel(p) > 0)
2616 && (ha->
2617 dcdb_active[scmd_channel(p) -
2618 1] & (1 << scmd_id(p)))) {
2619 ips_freescb(ha, scb);
2620 p = (struct scsi_cmnd *) p->host_scribble;
2621 continue;
2622 }
2623
2624 q = p;
2625 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2626
2627 if (intr == IPS_INTR_ON)
2628 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */
2629
2630 SC->result = DID_OK;
2631 SC->host_scribble = NULL;
2632
2633 scb->target_id = SC->device->id;
2634 scb->lun = SC->device->lun;
2635 scb->bus = SC->device->channel;
2636 scb->scsi_cmd = SC;
2637 scb->breakup = 0;
2638 scb->data_len = 0;
2639 scb->callback = ipsintr_done;
2640 scb->timeout = ips_cmd_timeout;
2641 memset(&scb->cmd, 0, 16);
2642
2643 /* copy in the CDB */
2644 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2645
2646 scb->sg_count = scsi_dma_map(SC);
2647 BUG_ON(scb->sg_count < 0);
2648 if (scb->sg_count) {
2649 struct scatterlist *sg;
2650 int i;
2651
2652 scb->flags |= IPS_SCB_MAP_SG;
2653
2654 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2655 if (ips_fill_scb_sg_single
2656 (ha, sg_dma_address(sg), scb, i,
2657 sg_dma_len(sg)) < 0)
2658 break;
2659 }
2660 scb->dcdb.transfer_length = scb->data_len;
2661 } else {
2662 scb->data_busaddr = 0L;
2663 scb->sg_len = 0;
2664 scb->data_len = 0;
2665 scb->dcdb.transfer_length = 0;
2666 }
2667
2668 scb->dcdb.cmd_attribute =
2669 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2670
2671 /* Allow a WRITE BUFFER Command to Have no Data */
2672 /* This is Used by Tape Flash Utilites */
2673 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2674 (scb->data_len == 0))
2675 scb->dcdb.cmd_attribute = 0;
2676
2677 if (!(scb->dcdb.cmd_attribute & 0x3))
2678 scb->dcdb.transfer_length = 0;
2679
2680 if (scb->data_len >= IPS_MAX_XFER) {
2681 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2682 scb->dcdb.transfer_length = 0;
2683 }
2684 if (intr == IPS_INTR_ON)
2685 spin_lock(host->host_lock);
2686
2687 ret = ips_send_cmd(ha, scb);
2688
2689 switch (ret) {
2690 case IPS_SUCCESS:
2691 ips_putq_scb_head(&ha->scb_activelist, scb);
2692 break;
2693 case IPS_FAILURE:
2694 if (scb->scsi_cmd) {
2695 scb->scsi_cmd->result = DID_ERROR << 16;
2696 scsi_done(scb->scsi_cmd);
2697 }
2698
2699 if (scb->bus)
2700 ha->dcdb_active[scb->bus - 1] &=
2701 ~(1 << scb->target_id);
2702
2703 ips_freescb(ha, scb);
2704 break;
2705 case IPS_SUCCESS_IMM:
2706 if (scb->scsi_cmd)
2707 scsi_done(scb->scsi_cmd);
2708
2709 if (scb->bus)
2710 ha->dcdb_active[scb->bus - 1] &=
2711 ~(1 << scb->target_id);
2712
2713 ips_freescb(ha, scb);
2714 break;
2715 default:
2716 break;
2717 } /* end case */
2718
2719 p = (struct scsi_cmnd *) p->host_scribble;
2720
2721 } /* end while */
2722
2723 if (intr == IPS_INTR_ON)
2724 spin_unlock(host->host_lock);
2725}
2726
2727/****************************************************************************/
2728/* */
2729/* Routine Name: ips_putq_scb_head */
2730/* */
2731/* Routine Description: */
2732/* */
2733/* Add an item to the head of the queue */
2734/* */
2735/* ASSUMED to be called from within the HA lock */
2736/* */
2737/****************************************************************************/
2738static void
2739ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2740{
2741 METHOD_TRACE("ips_putq_scb_head", 1);
2742
2743 if (!item)
2744 return;
2745
2746 item->q_next = queue->head;
2747 queue->head = item;
2748
2749 if (!queue->tail)
2750 queue->tail = item;
2751
2752 queue->count++;
2753}
2754
2755/****************************************************************************/
2756/* */
2757/* Routine Name: ips_removeq_scb_head */
2758/* */
2759/* Routine Description: */
2760/* */
2761/* Remove the head of the queue */
2762/* */
2763/* ASSUMED to be called from within the HA lock */
2764/* */
2765/****************************************************************************/
2766static ips_scb_t *
2767ips_removeq_scb_head(ips_scb_queue_t * queue)
2768{
2769 ips_scb_t *item;
2770
2771 METHOD_TRACE("ips_removeq_scb_head", 1);
2772
2773 item = queue->head;
2774
2775 if (!item) {
2776 return (NULL);
2777 }
2778
2779 queue->head = item->q_next;
2780 item->q_next = NULL;
2781
2782 if (queue->tail == item)
2783 queue->tail = NULL;
2784
2785 queue->count--;
2786
2787 return (item);
2788}
2789
2790/****************************************************************************/
2791/* */
2792/* Routine Name: ips_removeq_scb */
2793/* */
2794/* Routine Description: */
2795/* */
2796/* Remove an item from a queue */
2797/* */
2798/* ASSUMED to be called from within the HA lock */
2799/* */
2800/****************************************************************************/
2801static ips_scb_t *
2802ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2803{
2804 ips_scb_t *p;
2805
2806 METHOD_TRACE("ips_removeq_scb", 1);
2807
2808 if (!item)
2809 return (NULL);
2810
2811 if (item == queue->head) {
2812 return (ips_removeq_scb_head(queue));
2813 }
2814
2815 p = queue->head;
2816
2817 while ((p) && (item != p->q_next))
2818 p = p->q_next;
2819
2820 if (p) {
2821 /* found a match */
2822 p->q_next = item->q_next;
2823
2824 if (!item->q_next)
2825 queue->tail = p;
2826
2827 item->q_next = NULL;
2828 queue->count--;
2829
2830 return (item);
2831 }
2832
2833 return (NULL);
2834}
2835
2836/****************************************************************************/
2837/* */
2838/* Routine Name: ips_putq_wait_tail */
2839/* */
2840/* Routine Description: */
2841/* */
2842/* Add an item to the tail of the queue */
2843/* */
2844/* ASSUMED to be called from within the HA lock */
2845/* */
2846/****************************************************************************/
2847static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2848{
2849 METHOD_TRACE("ips_putq_wait_tail", 1);
2850
2851 if (!item)
2852 return;
2853
2854 item->host_scribble = NULL;
2855
2856 if (queue->tail)
2857 queue->tail->host_scribble = (char *) item;
2858
2859 queue->tail = item;
2860
2861 if (!queue->head)
2862 queue->head = item;
2863
2864 queue->count++;
2865}
2866
2867/****************************************************************************/
2868/* */
2869/* Routine Name: ips_removeq_wait_head */
2870/* */
2871/* Routine Description: */
2872/* */
2873/* Remove the head of the queue */
2874/* */
2875/* ASSUMED to be called from within the HA lock */
2876/* */
2877/****************************************************************************/
2878static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2879{
2880 struct scsi_cmnd *item;
2881
2882 METHOD_TRACE("ips_removeq_wait_head", 1);
2883
2884 item = queue->head;
2885
2886 if (!item) {
2887 return (NULL);
2888 }
2889
2890 queue->head = (struct scsi_cmnd *) item->host_scribble;
2891 item->host_scribble = NULL;
2892
2893 if (queue->tail == item)
2894 queue->tail = NULL;
2895
2896 queue->count--;
2897
2898 return (item);
2899}
2900
2901/****************************************************************************/
2902/* */
2903/* Routine Name: ips_removeq_wait */
2904/* */
2905/* Routine Description: */
2906/* */
2907/* Remove an item from a queue */
2908/* */
2909/* ASSUMED to be called from within the HA lock */
2910/* */
2911/****************************************************************************/
2912static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2913 struct scsi_cmnd *item)
2914{
2915 struct scsi_cmnd *p;
2916
2917 METHOD_TRACE("ips_removeq_wait", 1);
2918
2919 if (!item)
2920 return (NULL);
2921
2922 if (item == queue->head) {
2923 return (ips_removeq_wait_head(queue));
2924 }
2925
2926 p = queue->head;
2927
2928 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2929 p = (struct scsi_cmnd *) p->host_scribble;
2930
2931 if (p) {
2932 /* found a match */
2933 p->host_scribble = item->host_scribble;
2934
2935 if (!item->host_scribble)
2936 queue->tail = p;
2937
2938 item->host_scribble = NULL;
2939 queue->count--;
2940
2941 return (item);
2942 }
2943
2944 return (NULL);
2945}
2946
2947/****************************************************************************/
2948/* */
2949/* Routine Name: ips_putq_copp_tail */
2950/* */
2951/* Routine Description: */
2952/* */
2953/* Add an item to the tail of the queue */
2954/* */
2955/* ASSUMED to be called from within the HA lock */
2956/* */
2957/****************************************************************************/
2958static void
2959ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2960{
2961 METHOD_TRACE("ips_putq_copp_tail", 1);
2962
2963 if (!item)
2964 return;
2965
2966 item->next = NULL;
2967
2968 if (queue->tail)
2969 queue->tail->next = item;
2970
2971 queue->tail = item;
2972
2973 if (!queue->head)
2974 queue->head = item;
2975
2976 queue->count++;
2977}
2978
2979/****************************************************************************/
2980/* */
2981/* Routine Name: ips_removeq_copp_head */
2982/* */
2983/* Routine Description: */
2984/* */
2985/* Remove the head of the queue */
2986/* */
2987/* ASSUMED to be called from within the HA lock */
2988/* */
2989/****************************************************************************/
2990static ips_copp_wait_item_t *
2991ips_removeq_copp_head(ips_copp_queue_t * queue)
2992{
2993 ips_copp_wait_item_t *item;
2994
2995 METHOD_TRACE("ips_removeq_copp_head", 1);
2996
2997 item = queue->head;
2998
2999 if (!item) {
3000 return (NULL);
3001 }
3002
3003 queue->head = item->next;
3004 item->next = NULL;
3005
3006 if (queue->tail == item)
3007 queue->tail = NULL;
3008
3009 queue->count--;
3010
3011 return (item);
3012}
3013
3014/****************************************************************************/
3015/* */
3016/* Routine Name: ips_removeq_copp */
3017/* */
3018/* Routine Description: */
3019/* */
3020/* Remove an item from a queue */
3021/* */
3022/* ASSUMED to be called from within the HA lock */
3023/* */
3024/****************************************************************************/
3025static ips_copp_wait_item_t *
3026ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3027{
3028 ips_copp_wait_item_t *p;
3029
3030 METHOD_TRACE("ips_removeq_copp", 1);
3031
3032 if (!item)
3033 return (NULL);
3034
3035 if (item == queue->head) {
3036 return (ips_removeq_copp_head(queue));
3037 }
3038
3039 p = queue->head;
3040
3041 while ((p) && (item != p->next))
3042 p = p->next;
3043
3044 if (p) {
3045 /* found a match */
3046 p->next = item->next;
3047
3048 if (!item->next)
3049 queue->tail = p;
3050
3051 item->next = NULL;
3052 queue->count--;
3053
3054 return (item);
3055 }
3056
3057 return (NULL);
3058}
3059
3060/****************************************************************************/
3061/* */
3062/* Routine Name: ipsintr_blocking */
3063/* */
3064/* Routine Description: */
3065/* */
3066/* Finalize an interrupt for internal commands */
3067/* */
3068/****************************************************************************/
3069static void
3070ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3071{
3072 METHOD_TRACE("ipsintr_blocking", 2);
3073
3074 ips_freescb(ha, scb);
3075 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0]) {
3076 ha->waitflag = false;
3077
3078 return;
3079 }
3080}
3081
3082/****************************************************************************/
3083/* */
3084/* Routine Name: ipsintr_done */
3085/* */
3086/* Routine Description: */
3087/* */
3088/* Finalize an interrupt for non-internal commands */
3089/* */
3090/****************************************************************************/
3091static void
3092ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3093{
3094 METHOD_TRACE("ipsintr_done", 2);
3095
3096 if (!scb) {
3097 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3098 "Spurious interrupt; scb NULL.\n");
3099
3100 return;
3101 }
3102
3103 if (scb->scsi_cmd == NULL) {
3104 /* unexpected interrupt */
3105 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3106 "Spurious interrupt; scsi_cmd not set.\n");
3107
3108 return;
3109 }
3110
3111 ips_done(ha, scb);
3112}
3113
3114/****************************************************************************/
3115/* */
3116/* Routine Name: ips_done */
3117/* */
3118/* Routine Description: */
3119/* */
3120/* Do housekeeping on completed commands */
3121/* ASSUMED to be called form within the request lock */
3122/****************************************************************************/
3123static void
3124ips_done(ips_ha_t * ha, ips_scb_t * scb)
3125{
3126 int ret;
3127
3128 METHOD_TRACE("ips_done", 1);
3129
3130 if (!scb)
3131 return;
3132
3133 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3134 ips_cleanup_passthru(ha, scb);
3135 ha->num_ioctl--;
3136 } else {
3137 /*
3138 * Check to see if this command had too much
3139 * data and had to be broke up. If so, queue
3140 * the rest of the data and continue.
3141 */
3142 if ((scb->breakup) || (scb->sg_break)) {
3143 struct scatterlist *sg;
3144 int i, sg_dma_index, ips_sg_index = 0;
3145
3146 /* we had a data breakup */
3147 scb->data_len = 0;
3148
3149 sg = scsi_sglist(scb->scsi_cmd);
3150
3151 /* Spin forward to last dma chunk */
3152 sg_dma_index = scb->breakup;
3153 for (i = 0; i < scb->breakup; i++)
3154 sg = sg_next(sg);
3155
3156 /* Take care of possible partial on last chunk */
3157 ips_fill_scb_sg_single(ha,
3158 sg_dma_address(sg),
3159 scb, ips_sg_index++,
3160 sg_dma_len(sg));
3161
3162 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3163 sg_dma_index++, sg = sg_next(sg)) {
3164 if (ips_fill_scb_sg_single
3165 (ha,
3166 sg_dma_address(sg),
3167 scb, ips_sg_index++,
3168 sg_dma_len(sg)) < 0)
3169 break;
3170 }
3171
3172 scb->dcdb.transfer_length = scb->data_len;
3173 scb->dcdb.cmd_attribute |=
3174 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3175
3176 if (!(scb->dcdb.cmd_attribute & 0x3))
3177 scb->dcdb.transfer_length = 0;
3178
3179 if (scb->data_len >= IPS_MAX_XFER) {
3180 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3181 scb->dcdb.transfer_length = 0;
3182 }
3183
3184 ret = ips_send_cmd(ha, scb);
3185
3186 switch (ret) {
3187 case IPS_FAILURE:
3188 if (scb->scsi_cmd) {
3189 scb->scsi_cmd->result = DID_ERROR << 16;
3190 scsi_done(scb->scsi_cmd);
3191 }
3192
3193 ips_freescb(ha, scb);
3194 break;
3195 case IPS_SUCCESS_IMM:
3196 if (scb->scsi_cmd) {
3197 scb->scsi_cmd->result = DID_ERROR << 16;
3198 scsi_done(scb->scsi_cmd);
3199 }
3200
3201 ips_freescb(ha, scb);
3202 break;
3203 default:
3204 break;
3205 } /* end case */
3206
3207 return;
3208 }
3209 } /* end if passthru */
3210
3211 if (scb->bus) {
3212 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3213 }
3214
3215 scsi_done(scb->scsi_cmd);
3216
3217 ips_freescb(ha, scb);
3218}
3219
3220/****************************************************************************/
3221/* */
3222/* Routine Name: ips_map_status */
3223/* */
3224/* Routine Description: */
3225/* */
3226/* Map Controller Error codes to Linux Error Codes */
3227/* */
3228/****************************************************************************/
3229static int
3230ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3231{
3232 int errcode;
3233 int device_error;
3234 uint32_t transfer_len;
3235 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3236 IPS_SCSI_INQ_DATA inquiryData;
3237
3238 METHOD_TRACE("ips_map_status", 1);
3239
3240 if (scb->bus) {
3241 DEBUG_VAR(2,
3242 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3243 ips_name, ha->host_num,
3244 scb->scsi_cmd->device->channel,
3245 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3246 scb->basic_status, scb->extended_status,
3247 scb->extended_status ==
3248 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3249 scb->extended_status ==
3250 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3251 scb->extended_status ==
3252 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3253 }
3254
3255 /* default driver error */
3256 errcode = DID_ERROR;
3257 device_error = 0;
3258
3259 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3260 case IPS_CMD_TIMEOUT:
3261 errcode = DID_TIME_OUT;
3262 break;
3263
3264 case IPS_INVAL_OPCO:
3265 case IPS_INVAL_CMD_BLK:
3266 case IPS_INVAL_PARM_BLK:
3267 case IPS_LD_ERROR:
3268 case IPS_CMD_CMPLT_WERROR:
3269 break;
3270
3271 case IPS_PHYS_DRV_ERROR:
3272 switch (scb->extended_status) {
3273 case IPS_ERR_SEL_TO:
3274 if (scb->bus)
3275 errcode = DID_NO_CONNECT;
3276
3277 break;
3278
3279 case IPS_ERR_OU_RUN:
3280 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3281 (scb->cmd.dcdb.op_code ==
3282 IPS_CMD_EXTENDED_DCDB_SG)) {
3283 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3284 transfer_len = tapeDCDB->transfer_length;
3285 } else {
3286 transfer_len =
3287 (uint32_t) scb->dcdb.transfer_length;
3288 }
3289
3290 if ((scb->bus) && (transfer_len < scb->data_len)) {
3291 /* Underrun - set default to no error */
3292 errcode = DID_OK;
3293
3294 /* Restrict access to physical DASD */
3295 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3296 ips_scmd_buf_read(scb->scsi_cmd,
3297 &inquiryData, sizeof (inquiryData));
3298 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3299 errcode = DID_TIME_OUT;
3300 break;
3301 }
3302 }
3303 } else
3304 errcode = DID_ERROR;
3305
3306 break;
3307
3308 case IPS_ERR_RECOVERY:
3309 /* don't fail recovered errors */
3310 if (scb->bus)
3311 errcode = DID_OK;
3312
3313 break;
3314
3315 case IPS_ERR_HOST_RESET:
3316 case IPS_ERR_DEV_RESET:
3317 errcode = DID_RESET;
3318 break;
3319
3320 case IPS_ERR_CKCOND:
3321 if (scb->bus) {
3322 if ((scb->cmd.dcdb.op_code ==
3323 IPS_CMD_EXTENDED_DCDB)
3324 || (scb->cmd.dcdb.op_code ==
3325 IPS_CMD_EXTENDED_DCDB_SG)) {
3326 tapeDCDB =
3327 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3328 memcpy_and_pad(scb->scsi_cmd->sense_buffer,
3329 SCSI_SENSE_BUFFERSIZE,
3330 tapeDCDB->sense_info,
3331 sizeof(tapeDCDB->sense_info), 0);
3332 } else {
3333 memcpy_and_pad(scb->scsi_cmd->sense_buffer,
3334 SCSI_SENSE_BUFFERSIZE,
3335 scb->dcdb.sense_info,
3336 sizeof(scb->dcdb.sense_info), 0);
3337 }
3338 device_error = 2; /* check condition */
3339 }
3340
3341 errcode = DID_OK;
3342
3343 break;
3344
3345 default:
3346 errcode = DID_ERROR;
3347 break;
3348
3349 } /* end switch */
3350 } /* end switch */
3351
3352 scb->scsi_cmd->result = device_error | (errcode << 16);
3353
3354 return (1);
3355}
3356
3357/****************************************************************************/
3358/* */
3359/* Routine Name: ips_send_wait */
3360/* */
3361/* Routine Description: */
3362/* */
3363/* Send a command to the controller and wait for it to return */
3364/* */
3365/* The FFDC Time Stamp use this function for the callback, but doesn't */
3366/* actually need to wait. */
3367/****************************************************************************/
3368static int
3369ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3370{
3371 int ret;
3372
3373 METHOD_TRACE("ips_send_wait", 1);
3374
3375 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3376 ha->waitflag = true;
3377 ha->cmd_in_progress = scb->cdb[0];
3378 }
3379 scb->callback = ipsintr_blocking;
3380 ret = ips_send_cmd(ha, scb);
3381
3382 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3383 return (ret);
3384
3385 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3386 ret = ips_wait(ha, timeout, intr);
3387
3388 return (ret);
3389}
3390
3391/****************************************************************************/
3392/* */
3393/* Routine Name: ips_scmd_buf_write */
3394/* */
3395/* Routine Description: */
3396/* Write data to struct scsi_cmnd request_buffer at proper offsets */
3397/****************************************************************************/
3398static void
3399ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3400{
3401 unsigned long flags;
3402
3403 local_irq_save(flags);
3404 scsi_sg_copy_from_buffer(scmd, data, count);
3405 local_irq_restore(flags);
3406}
3407
3408/****************************************************************************/
3409/* */
3410/* Routine Name: ips_scmd_buf_read */
3411/* */
3412/* Routine Description: */
3413/* Copy data from a struct scsi_cmnd to a new, linear buffer */
3414/****************************************************************************/
3415static void
3416ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3417{
3418 unsigned long flags;
3419
3420 local_irq_save(flags);
3421 scsi_sg_copy_to_buffer(scmd, data, count);
3422 local_irq_restore(flags);
3423}
3424
3425/****************************************************************************/
3426/* */
3427/* Routine Name: ips_send_cmd */
3428/* */
3429/* Routine Description: */
3430/* */
3431/* Map SCSI commands to ServeRAID commands for logical drives */
3432/* */
3433/****************************************************************************/
3434static int
3435ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3436{
3437 int ret;
3438 char *sp;
3439 int device_error;
3440 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3441 int TimeOut;
3442
3443 METHOD_TRACE("ips_send_cmd", 1);
3444
3445 ret = IPS_SUCCESS;
3446
3447 if (!scb->scsi_cmd) {
3448 /* internal command */
3449
3450 if (scb->bus > 0) {
3451 /* Controller commands can't be issued */
3452 /* to real devices -- fail them */
3453 if (ha->waitflag && ha->cmd_in_progress == scb->cdb[0])
3454 ha->waitflag = false;
3455
3456 return (1);
3457 }
3458 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3459 /* command to logical bus -- interpret */
3460 ret = IPS_SUCCESS_IMM;
3461
3462 switch (scb->scsi_cmd->cmnd[0]) {
3463 case ALLOW_MEDIUM_REMOVAL:
3464 case REZERO_UNIT:
3465 case ERASE:
3466 case WRITE_FILEMARKS:
3467 case SPACE:
3468 scb->scsi_cmd->result = DID_ERROR << 16;
3469 break;
3470
3471 case START_STOP:
3472 scb->scsi_cmd->result = DID_OK << 16;
3473 break;
3474
3475 case TEST_UNIT_READY:
3476 case INQUIRY:
3477 if (scb->target_id == IPS_ADAPTER_ID) {
3478 /*
3479 * Either we have a TUR
3480 * or we have a SCSI inquiry
3481 */
3482 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3483 scb->scsi_cmd->result = DID_OK << 16;
3484
3485 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3486 IPS_SCSI_INQ_DATA inquiry;
3487
3488 memset(&inquiry, 0,
3489 sizeof (IPS_SCSI_INQ_DATA));
3490
3491 inquiry.DeviceType =
3492 IPS_SCSI_INQ_TYPE_PROCESSOR;
3493 inquiry.DeviceTypeQualifier =
3494 IPS_SCSI_INQ_LU_CONNECTED;
3495 inquiry.Version = IPS_SCSI_INQ_REV2;
3496 inquiry.ResponseDataFormat =
3497 IPS_SCSI_INQ_RD_REV2;
3498 inquiry.AdditionalLength = 31;
3499 inquiry.Flags[0] =
3500 IPS_SCSI_INQ_Address16;
3501 inquiry.Flags[1] =
3502 IPS_SCSI_INQ_WBus16 |
3503 IPS_SCSI_INQ_Sync;
3504 memcpy(inquiry.VendorId, "IBM ",
3505 8);
3506 memcpy(inquiry.ProductId,
3507 "SERVERAID ", 16);
3508 memcpy(inquiry.ProductRevisionLevel,
3509 "1.00", 4);
3510
3511 ips_scmd_buf_write(scb->scsi_cmd,
3512 &inquiry,
3513 sizeof (inquiry));
3514
3515 scb->scsi_cmd->result = DID_OK << 16;
3516 }
3517 } else {
3518 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3519 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3520 scb->cmd.logical_info.reserved = 0;
3521 scb->cmd.logical_info.reserved2 = 0;
3522 scb->data_len = sizeof (IPS_LD_INFO);
3523 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3524 scb->flags = 0;
3525 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3526 ret = IPS_SUCCESS;
3527 }
3528
3529 break;
3530
3531 case REQUEST_SENSE:
3532 ips_reqsen(ha, scb);
3533 scb->scsi_cmd->result = DID_OK << 16;
3534 break;
3535
3536 case READ_6:
3537 case WRITE_6:
3538 if (!scb->sg_len) {
3539 scb->cmd.basic_io.op_code =
3540 (scb->scsi_cmd->cmnd[0] ==
3541 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3542 scb->cmd.basic_io.enhanced_sg = 0;
3543 scb->cmd.basic_io.sg_addr =
3544 cpu_to_le32(scb->data_busaddr);
3545 } else {
3546 scb->cmd.basic_io.op_code =
3547 (scb->scsi_cmd->cmnd[0] ==
3548 READ_6) ? IPS_CMD_READ_SG :
3549 IPS_CMD_WRITE_SG;
3550 scb->cmd.basic_io.enhanced_sg =
3551 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3552 scb->cmd.basic_io.sg_addr =
3553 cpu_to_le32(scb->sg_busaddr);
3554 }
3555
3556 scb->cmd.basic_io.segment_4G = 0;
3557 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3558 scb->cmd.basic_io.log_drv = scb->target_id;
3559 scb->cmd.basic_io.sg_count = scb->sg_len;
3560
3561 if (scb->cmd.basic_io.lba)
3562 le32_add_cpu(&scb->cmd.basic_io.lba,
3563 le16_to_cpu(scb->cmd.basic_io.
3564 sector_count));
3565 else
3566 scb->cmd.basic_io.lba =
3567 (((scb->scsi_cmd->
3568 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3569 cmnd[2] << 8) |
3570 (scb->scsi_cmd->cmnd[3]));
3571
3572 scb->cmd.basic_io.sector_count =
3573 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3574
3575 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3576 scb->cmd.basic_io.sector_count =
3577 cpu_to_le16(256);
3578
3579 ret = IPS_SUCCESS;
3580 break;
3581
3582 case READ_10:
3583 case WRITE_10:
3584 if (!scb->sg_len) {
3585 scb->cmd.basic_io.op_code =
3586 (scb->scsi_cmd->cmnd[0] ==
3587 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3588 scb->cmd.basic_io.enhanced_sg = 0;
3589 scb->cmd.basic_io.sg_addr =
3590 cpu_to_le32(scb->data_busaddr);
3591 } else {
3592 scb->cmd.basic_io.op_code =
3593 (scb->scsi_cmd->cmnd[0] ==
3594 READ_10) ? IPS_CMD_READ_SG :
3595 IPS_CMD_WRITE_SG;
3596 scb->cmd.basic_io.enhanced_sg =
3597 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3598 scb->cmd.basic_io.sg_addr =
3599 cpu_to_le32(scb->sg_busaddr);
3600 }
3601
3602 scb->cmd.basic_io.segment_4G = 0;
3603 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3604 scb->cmd.basic_io.log_drv = scb->target_id;
3605 scb->cmd.basic_io.sg_count = scb->sg_len;
3606
3607 if (scb->cmd.basic_io.lba)
3608 le32_add_cpu(&scb->cmd.basic_io.lba,
3609 le16_to_cpu(scb->cmd.basic_io.
3610 sector_count));
3611 else
3612 scb->cmd.basic_io.lba =
3613 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3614 scsi_cmd->
3615 cmnd[3]
3616 << 16) |
3617 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3618 scsi_cmd->cmnd[5]);
3619
3620 scb->cmd.basic_io.sector_count =
3621 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3622
3623 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3624 /*
3625 * This is a null condition
3626 * we don't have to do anything
3627 * so just return
3628 */
3629 scb->scsi_cmd->result = DID_OK << 16;
3630 } else
3631 ret = IPS_SUCCESS;
3632
3633 break;
3634
3635 case RESERVE_6:
3636 case RELEASE_6:
3637 scb->scsi_cmd->result = DID_OK << 16;
3638 break;
3639
3640 case MODE_SENSE:
3641 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3642 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3643 scb->cmd.basic_io.segment_4G = 0;
3644 scb->cmd.basic_io.enhanced_sg = 0;
3645 scb->data_len = sizeof (*ha->enq);
3646 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3647 ret = IPS_SUCCESS;
3648 break;
3649
3650 case READ_CAPACITY:
3651 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3652 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3653 scb->cmd.logical_info.reserved = 0;
3654 scb->cmd.logical_info.reserved2 = 0;
3655 scb->cmd.logical_info.reserved3 = 0;
3656 scb->data_len = sizeof (IPS_LD_INFO);
3657 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3658 scb->flags = 0;
3659 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3660 ret = IPS_SUCCESS;
3661 break;
3662
3663 case SEND_DIAGNOSTIC:
3664 case REASSIGN_BLOCKS:
3665 case FORMAT_UNIT:
3666 case SEEK_10:
3667 case VERIFY:
3668 case READ_DEFECT_DATA:
3669 case READ_BUFFER:
3670 case WRITE_BUFFER:
3671 scb->scsi_cmd->result = DID_OK << 16;
3672 break;
3673
3674 default:
3675 /* Set the Return Info to appear like the Command was */
3676 /* attempted, a Check Condition occurred, and Sense */
3677 /* Data indicating an Invalid CDB OpCode is returned. */
3678 sp = (char *) scb->scsi_cmd->sense_buffer;
3679
3680 sp[0] = 0x70; /* Error Code */
3681 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3682 sp[7] = 0x0A; /* Additional Sense Length */
3683 sp[12] = 0x20; /* ASC = Invalid OpCode */
3684 sp[13] = 0x00; /* ASCQ */
3685
3686 device_error = 2; /* Indicate Check Condition */
3687 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3688 break;
3689 } /* end switch */
3690 }
3691 /* end if */
3692 if (ret == IPS_SUCCESS_IMM)
3693 return (ret);
3694
3695 /* setup DCDB */
3696 if (scb->bus > 0) {
3697
3698 /* If we already know the Device is Not there, no need to attempt a Command */
3699 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3700 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3701 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3702 return (IPS_SUCCESS_IMM);
3703 }
3704
3705 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3706 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3707 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3708 (unsigned long) &scb->
3709 dcdb -
3710 (unsigned long) scb);
3711 scb->cmd.dcdb.reserved = 0;
3712 scb->cmd.dcdb.reserved2 = 0;
3713 scb->cmd.dcdb.reserved3 = 0;
3714 scb->cmd.dcdb.segment_4G = 0;
3715 scb->cmd.dcdb.enhanced_sg = 0;
3716
3717 TimeOut = scsi_cmd_to_rq(scb->scsi_cmd)->timeout;
3718
3719 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3720 if (!scb->sg_len) {
3721 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3722 } else {
3723 scb->cmd.dcdb.op_code =
3724 IPS_CMD_EXTENDED_DCDB_SG;
3725 scb->cmd.dcdb.enhanced_sg =
3726 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3727 }
3728
3729 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
3730 tapeDCDB->device_address =
3731 ((scb->bus - 1) << 4) | scb->target_id;
3732 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3733 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
3734
3735 if (TimeOut) {
3736 if (TimeOut < (10 * HZ))
3737 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3738 else if (TimeOut < (60 * HZ))
3739 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3740 else if (TimeOut < (1200 * HZ))
3741 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3742 }
3743
3744 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3745 tapeDCDB->reserved_for_LUN = 0;
3746 tapeDCDB->transfer_length = scb->data_len;
3747 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3748 tapeDCDB->buffer_pointer =
3749 cpu_to_le32(scb->sg_busaddr);
3750 else
3751 tapeDCDB->buffer_pointer =
3752 cpu_to_le32(scb->data_busaddr);
3753 tapeDCDB->sg_count = scb->sg_len;
3754 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3755 tapeDCDB->scsi_status = 0;
3756 tapeDCDB->reserved = 0;
3757 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3758 scb->scsi_cmd->cmd_len);
3759 } else {
3760 if (!scb->sg_len) {
3761 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3762 } else {
3763 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3764 scb->cmd.dcdb.enhanced_sg =
3765 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3766 }
3767
3768 scb->dcdb.device_address =
3769 ((scb->bus - 1) << 4) | scb->target_id;
3770 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3771
3772 if (TimeOut) {
3773 if (TimeOut < (10 * HZ))
3774 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
3775 else if (TimeOut < (60 * HZ))
3776 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
3777 else if (TimeOut < (1200 * HZ))
3778 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
3779 }
3780
3781 scb->dcdb.transfer_length = scb->data_len;
3782 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3783 scb->dcdb.transfer_length = 0;
3784 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3785 scb->dcdb.buffer_pointer =
3786 cpu_to_le32(scb->sg_busaddr);
3787 else
3788 scb->dcdb.buffer_pointer =
3789 cpu_to_le32(scb->data_busaddr);
3790 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3791 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3792 scb->dcdb.sg_count = scb->sg_len;
3793 scb->dcdb.reserved = 0;
3794 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3795 scb->scsi_cmd->cmd_len);
3796 scb->dcdb.scsi_status = 0;
3797 scb->dcdb.reserved2[0] = 0;
3798 scb->dcdb.reserved2[1] = 0;
3799 scb->dcdb.reserved2[2] = 0;
3800 }
3801 }
3802
3803 return ((*ha->func.issue) (ha, scb));
3804}
3805
3806/****************************************************************************/
3807/* */
3808/* Routine Name: ips_chk_status */
3809/* */
3810/* Routine Description: */
3811/* */
3812/* Check the status of commands to logical drives */
3813/* Assumed to be called with the HA lock */
3814/****************************************************************************/
3815static void
3816ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3817{
3818 ips_scb_t *scb;
3819 ips_stat_t *sp;
3820 uint8_t basic_status;
3821 uint8_t ext_status;
3822 int errcode;
3823 IPS_SCSI_INQ_DATA inquiryData;
3824
3825 METHOD_TRACE("ips_chkstatus", 1);
3826
3827 scb = &ha->scbs[pstatus->fields.command_id];
3828 scb->basic_status = basic_status =
3829 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3830 scb->extended_status = ext_status = pstatus->fields.extended_status;
3831
3832 sp = &ha->sp;
3833 sp->residue_len = 0;
3834 sp->scb_addr = (void *) scb;
3835
3836 /* Remove the item from the active queue */
3837 ips_removeq_scb(&ha->scb_activelist, scb);
3838
3839 if (!scb->scsi_cmd)
3840 /* internal commands are handled in do_ipsintr */
3841 return;
3842
3843 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3844 ips_name,
3845 ha->host_num,
3846 scb->cdb[0],
3847 scb->cmd.basic_io.command_id,
3848 scb->bus, scb->target_id, scb->lun);
3849
3850 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3851 /* passthru - just returns the raw result */
3852 return;
3853
3854 errcode = DID_OK;
3855
3856 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3857 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3858
3859 if (scb->bus == 0) {
3860 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3861 IPS_CMD_RECOVERED_ERROR) {
3862 DEBUG_VAR(1,
3863 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3864 ips_name, ha->host_num,
3865 scb->cmd.basic_io.op_code,
3866 basic_status, ext_status);
3867 }
3868
3869 switch (scb->scsi_cmd->cmnd[0]) {
3870 case ALLOW_MEDIUM_REMOVAL:
3871 case REZERO_UNIT:
3872 case ERASE:
3873 case WRITE_FILEMARKS:
3874 case SPACE:
3875 errcode = DID_ERROR;
3876 break;
3877
3878 case START_STOP:
3879 break;
3880
3881 case TEST_UNIT_READY:
3882 if (!ips_online(ha, scb)) {
3883 errcode = DID_TIME_OUT;
3884 }
3885 break;
3886
3887 case INQUIRY:
3888 if (ips_online(ha, scb)) {
3889 ips_inquiry(ha, scb);
3890 } else {
3891 errcode = DID_TIME_OUT;
3892 }
3893 break;
3894
3895 case REQUEST_SENSE:
3896 ips_reqsen(ha, scb);
3897 break;
3898
3899 case READ_6:
3900 case WRITE_6:
3901 case READ_10:
3902 case WRITE_10:
3903 case RESERVE_6:
3904 case RELEASE_6:
3905 break;
3906
3907 case MODE_SENSE:
3908 if (!ips_online(ha, scb)
3909 || !ips_msense(ha, scb)) {
3910 errcode = DID_ERROR;
3911 }
3912 break;
3913
3914 case READ_CAPACITY:
3915 if (ips_online(ha, scb))
3916 ips_rdcap(ha, scb);
3917 else {
3918 errcode = DID_TIME_OUT;
3919 }
3920 break;
3921
3922 case SEND_DIAGNOSTIC:
3923 case REASSIGN_BLOCKS:
3924 break;
3925
3926 case FORMAT_UNIT:
3927 errcode = DID_ERROR;
3928 break;
3929
3930 case SEEK_10:
3931 case VERIFY:
3932 case READ_DEFECT_DATA:
3933 case READ_BUFFER:
3934 case WRITE_BUFFER:
3935 break;
3936
3937 default:
3938 errcode = DID_ERROR;
3939 } /* end switch */
3940
3941 scb->scsi_cmd->result = errcode << 16;
3942 } else { /* bus == 0 */
3943 /* restrict access to physical drives */
3944 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3945 ips_scmd_buf_read(scb->scsi_cmd,
3946 &inquiryData, sizeof (inquiryData));
3947 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3948 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3949 }
3950 } /* else */
3951 } else { /* recovered error / success */
3952 if (scb->bus == 0) {
3953 DEBUG_VAR(1,
3954 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3955 ips_name, ha->host_num,
3956 scb->cmd.basic_io.op_code, basic_status,
3957 ext_status);
3958 }
3959
3960 ips_map_status(ha, scb, sp);
3961 } /* else */
3962}
3963
3964/****************************************************************************/
3965/* */
3966/* Routine Name: ips_online */
3967/* */
3968/* Routine Description: */
3969/* */
3970/* Determine if a logical drive is online */
3971/* */
3972/****************************************************************************/
3973static int
3974ips_online(ips_ha_t * ha, ips_scb_t * scb)
3975{
3976 METHOD_TRACE("ips_online", 1);
3977
3978 if (scb->target_id >= IPS_MAX_LD)
3979 return (0);
3980
3981 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
3982 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
3983 return (0);
3984 }
3985
3986 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
3987 IPS_LD_OFFLINE
3988 && ha->logical_drive_info->drive_info[scb->target_id].state !=
3989 IPS_LD_FREE
3990 && ha->logical_drive_info->drive_info[scb->target_id].state !=
3991 IPS_LD_CRS
3992 && ha->logical_drive_info->drive_info[scb->target_id].state !=
3993 IPS_LD_SYS)
3994 return (1);
3995 else
3996 return (0);
3997}
3998
3999/****************************************************************************/
4000/* */
4001/* Routine Name: ips_inquiry */
4002/* */
4003/* Routine Description: */
4004/* */
4005/* Simulate an inquiry command to a logical drive */
4006/* */
4007/****************************************************************************/
4008static int
4009ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4010{
4011 IPS_SCSI_INQ_DATA inquiry;
4012
4013 METHOD_TRACE("ips_inquiry", 1);
4014
4015 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4016
4017 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4018 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4019 inquiry.Version = IPS_SCSI_INQ_REV2;
4020 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4021 inquiry.AdditionalLength = 31;
4022 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4023 inquiry.Flags[1] =
4024 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4025 memcpy(inquiry.VendorId, "IBM ", 8);
4026 memcpy(inquiry.ProductId, "SERVERAID ", 16);
4027 memcpy(inquiry.ProductRevisionLevel, "1.00", 4);
4028
4029 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4030
4031 return (1);
4032}
4033
4034/****************************************************************************/
4035/* */
4036/* Routine Name: ips_rdcap */
4037/* */
4038/* Routine Description: */
4039/* */
4040/* Simulate a read capacity command to a logical drive */
4041/* */
4042/****************************************************************************/
4043static int
4044ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4045{
4046 IPS_SCSI_CAPACITY cap;
4047
4048 METHOD_TRACE("ips_rdcap", 1);
4049
4050 if (scsi_bufflen(scb->scsi_cmd) < 8)
4051 return (0);
4052
4053 cap.lba =
4054 cpu_to_be32(le32_to_cpu
4055 (ha->logical_drive_info->
4056 drive_info[scb->target_id].sector_count) - 1);
4057 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4058
4059 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4060
4061 return (1);
4062}
4063
4064/****************************************************************************/
4065/* */
4066/* Routine Name: ips_msense */
4067/* */
4068/* Routine Description: */
4069/* */
4070/* Simulate a mode sense command to a logical drive */
4071/* */
4072/****************************************************************************/
4073static int
4074ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4075{
4076 uint16_t heads;
4077 uint16_t sectors;
4078 uint32_t cylinders;
4079 IPS_SCSI_MODE_PAGE_DATA mdata;
4080
4081 METHOD_TRACE("ips_msense", 1);
4082
4083 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4084 (ha->enq->ucMiscFlag & 0x8) == 0) {
4085 heads = IPS_NORM_HEADS;
4086 sectors = IPS_NORM_SECTORS;
4087 } else {
4088 heads = IPS_COMP_HEADS;
4089 sectors = IPS_COMP_SECTORS;
4090 }
4091
4092 cylinders =
4093 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4094 1) / (heads * sectors);
4095
4096 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4097
4098 mdata.hdr.BlockDescLength = 8;
4099
4100 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4101 case 0x03: /* page 3 */
4102 mdata.pdata.pg3.PageCode = 3;
4103 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4104 mdata.hdr.DataLength =
4105 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4106 mdata.pdata.pg3.TracksPerZone = 0;
4107 mdata.pdata.pg3.AltSectorsPerZone = 0;
4108 mdata.pdata.pg3.AltTracksPerZone = 0;
4109 mdata.pdata.pg3.AltTracksPerVolume = 0;
4110 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4111 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4112 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4113 mdata.pdata.pg3.TrackSkew = 0;
4114 mdata.pdata.pg3.CylinderSkew = 0;
4115 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4116 break;
4117
4118 case 0x4:
4119 mdata.pdata.pg4.PageCode = 4;
4120 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4121 mdata.hdr.DataLength =
4122 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4123 mdata.pdata.pg4.CylindersHigh =
4124 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4125 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4126 mdata.pdata.pg4.Heads = heads;
4127 mdata.pdata.pg4.WritePrecompHigh = 0;
4128 mdata.pdata.pg4.WritePrecompLow = 0;
4129 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4130 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4131 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4132 mdata.pdata.pg4.LandingZoneHigh = 0;
4133 mdata.pdata.pg4.LandingZoneLow = 0;
4134 mdata.pdata.pg4.flags = 0;
4135 mdata.pdata.pg4.RotationalOffset = 0;
4136 mdata.pdata.pg4.MediumRotationRate = 0;
4137 break;
4138 case 0x8:
4139 mdata.pdata.pg8.PageCode = 8;
4140 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4141 mdata.hdr.DataLength =
4142 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4143 /* everything else is left set to 0 */
4144 break;
4145
4146 default:
4147 return (0);
4148 } /* end switch */
4149
4150 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4151
4152 return (1);
4153}
4154
4155/****************************************************************************/
4156/* */
4157/* Routine Name: ips_reqsen */
4158/* */
4159/* Routine Description: */
4160/* */
4161/* Simulate a request sense command to a logical drive */
4162/* */
4163/****************************************************************************/
4164static int
4165ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4166{
4167 IPS_SCSI_REQSEN reqsen;
4168
4169 METHOD_TRACE("ips_reqsen", 1);
4170
4171 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4172
4173 reqsen.ResponseCode =
4174 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4175 reqsen.AdditionalLength = 10;
4176 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4177 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4178
4179 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4180
4181 return (1);
4182}
4183
4184/****************************************************************************/
4185/* */
4186/* Routine Name: ips_free */
4187/* */
4188/* Routine Description: */
4189/* */
4190/* Free any allocated space for this controller */
4191/* */
4192/****************************************************************************/
4193static void
4194ips_free(ips_ha_t * ha)
4195{
4196
4197 METHOD_TRACE("ips_free", 1);
4198
4199 if (ha) {
4200 if (ha->enq) {
4201 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ),
4202 ha->enq, ha->enq_busaddr);
4203 ha->enq = NULL;
4204 }
4205
4206 kfree(ha->conf);
4207 ha->conf = NULL;
4208
4209 if (ha->adapt) {
4210 dma_free_coherent(&ha->pcidev->dev,
4211 sizeof (IPS_ADAPTER) +
4212 sizeof (IPS_IO_CMD), ha->adapt,
4213 ha->adapt->hw_status_start);
4214 ha->adapt = NULL;
4215 }
4216
4217 if (ha->logical_drive_info) {
4218 dma_free_coherent(&ha->pcidev->dev,
4219 sizeof (IPS_LD_INFO),
4220 ha->logical_drive_info,
4221 ha->logical_drive_info_dma_addr);
4222 ha->logical_drive_info = NULL;
4223 }
4224
4225 kfree(ha->nvram);
4226 ha->nvram = NULL;
4227
4228 kfree(ha->subsys);
4229 ha->subsys = NULL;
4230
4231 if (ha->ioctl_data) {
4232 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len,
4233 ha->ioctl_data, ha->ioctl_busaddr);
4234 ha->ioctl_data = NULL;
4235 ha->ioctl_datasize = 0;
4236 ha->ioctl_len = 0;
4237 }
4238 ips_deallocatescbs(ha, ha->max_cmds);
4239
4240 /* free memory mapped (if applicable) */
4241 if (ha->mem_ptr) {
4242 iounmap(ha->ioremap_ptr);
4243 ha->ioremap_ptr = NULL;
4244 ha->mem_ptr = NULL;
4245 }
4246
4247 ha->mem_addr = 0;
4248
4249 }
4250}
4251
4252/****************************************************************************/
4253/* */
4254/* Routine Name: ips_deallocatescbs */
4255/* */
4256/* Routine Description: */
4257/* */
4258/* Free the command blocks */
4259/* */
4260/****************************************************************************/
4261static int
4262ips_deallocatescbs(ips_ha_t * ha, int cmds)
4263{
4264 if (ha->scbs) {
4265 dma_free_coherent(&ha->pcidev->dev,
4266 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4267 ha->scbs->sg_list.list,
4268 ha->scbs->sg_busaddr);
4269 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds,
4270 ha->scbs, ha->scbs->scb_busaddr);
4271 ha->scbs = NULL;
4272 } /* end if */
4273 return 1;
4274}
4275
4276/****************************************************************************/
4277/* */
4278/* Routine Name: ips_allocatescbs */
4279/* */
4280/* Routine Description: */
4281/* */
4282/* Allocate the command blocks */
4283/* */
4284/****************************************************************************/
4285static int
4286ips_allocatescbs(ips_ha_t * ha)
4287{
4288 ips_scb_t *scb_p;
4289 IPS_SG_LIST ips_sg;
4290 int i;
4291 dma_addr_t command_dma, sg_dma;
4292
4293 METHOD_TRACE("ips_allocatescbs", 1);
4294
4295 /* Allocate memory for the SCBs */
4296 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev,
4297 ha->max_cmds * sizeof (ips_scb_t),
4298 &command_dma, GFP_KERNEL);
4299 if (ha->scbs == NULL)
4300 return 0;
4301 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev,
4302 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds,
4303 &sg_dma, GFP_KERNEL);
4304 if (ips_sg.list == NULL) {
4305 dma_free_coherent(&ha->pcidev->dev,
4306 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4307 command_dma);
4308 return 0;
4309 }
4310
4311 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4312
4313 for (i = 0; i < ha->max_cmds; i++) {
4314 scb_p = &ha->scbs[i];
4315 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4316 /* set up S/G list */
4317 if (IPS_USE_ENH_SGLIST(ha)) {
4318 scb_p->sg_list.enh_list =
4319 ips_sg.enh_list + i * IPS_MAX_SG;
4320 scb_p->sg_busaddr =
4321 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4322 } else {
4323 scb_p->sg_list.std_list =
4324 ips_sg.std_list + i * IPS_MAX_SG;
4325 scb_p->sg_busaddr =
4326 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4327 }
4328
4329 /* add to the free list */
4330 if (i < ha->max_cmds - 1) {
4331 scb_p->q_next = ha->scb_freelist;
4332 ha->scb_freelist = scb_p;
4333 }
4334 }
4335
4336 /* success */
4337 return (1);
4338}
4339
4340/****************************************************************************/
4341/* */
4342/* Routine Name: ips_init_scb */
4343/* */
4344/* Routine Description: */
4345/* */
4346/* Initialize a CCB to default values */
4347/* */
4348/****************************************************************************/
4349static void
4350ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4351{
4352 IPS_SG_LIST sg_list;
4353 uint32_t cmd_busaddr, sg_busaddr;
4354 METHOD_TRACE("ips_init_scb", 1);
4355
4356 if (scb == NULL)
4357 return;
4358
4359 sg_list.list = scb->sg_list.list;
4360 cmd_busaddr = scb->scb_busaddr;
4361 sg_busaddr = scb->sg_busaddr;
4362 /* zero fill */
4363 memset(scb, 0, sizeof (ips_scb_t));
4364 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4365
4366 /* Initialize dummy command bucket */
4367 ha->dummy->op_code = 0xFF;
4368 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4369 + sizeof (IPS_ADAPTER));
4370 ha->dummy->command_id = IPS_MAX_CMDS;
4371
4372 /* set bus address of scb */
4373 scb->scb_busaddr = cmd_busaddr;
4374 scb->sg_busaddr = sg_busaddr;
4375 scb->sg_list.list = sg_list.list;
4376
4377 /* Neptune Fix */
4378 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4379 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4380 + sizeof (IPS_ADAPTER));
4381}
4382
4383/****************************************************************************/
4384/* */
4385/* Routine Name: ips_get_scb */
4386/* */
4387/* Routine Description: */
4388/* */
4389/* Initialize a CCB to default values */
4390/* */
4391/* ASSUMED to be called from within a lock */
4392/* */
4393/****************************************************************************/
4394static ips_scb_t *
4395ips_getscb(ips_ha_t * ha)
4396{
4397 ips_scb_t *scb;
4398
4399 METHOD_TRACE("ips_getscb", 1);
4400
4401 if ((scb = ha->scb_freelist) == NULL) {
4402
4403 return (NULL);
4404 }
4405
4406 ha->scb_freelist = scb->q_next;
4407 scb->flags = 0;
4408 scb->q_next = NULL;
4409
4410 ips_init_scb(ha, scb);
4411
4412 return (scb);
4413}
4414
4415/****************************************************************************/
4416/* */
4417/* Routine Name: ips_free_scb */
4418/* */
4419/* Routine Description: */
4420/* */
4421/* Return an unused CCB back to the free list */
4422/* */
4423/* ASSUMED to be called from within a lock */
4424/* */
4425/****************************************************************************/
4426static void
4427ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4428{
4429
4430 METHOD_TRACE("ips_freescb", 1);
4431 if (scb->flags & IPS_SCB_MAP_SG)
4432 scsi_dma_unmap(scb->scsi_cmd);
4433 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4434 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr,
4435 scb->data_len, IPS_DMA_DIR(scb));
4436
4437 /* check to make sure this is not our "special" scb */
4438 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4439 scb->q_next = ha->scb_freelist;
4440 ha->scb_freelist = scb;
4441 }
4442}
4443
4444/****************************************************************************/
4445/* */
4446/* Routine Name: ips_isinit_copperhead */
4447/* */
4448/* Routine Description: */
4449/* */
4450/* Is controller initialized ? */
4451/* */
4452/****************************************************************************/
4453static int
4454ips_isinit_copperhead(ips_ha_t * ha)
4455{
4456 uint8_t scpr;
4457 uint8_t isr;
4458
4459 METHOD_TRACE("ips_isinit_copperhead", 1);
4460
4461 isr = inb(ha->io_addr + IPS_REG_HISR);
4462 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4463
4464 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4465 return (0);
4466 else
4467 return (1);
4468}
4469
4470/****************************************************************************/
4471/* */
4472/* Routine Name: ips_isinit_copperhead_memio */
4473/* */
4474/* Routine Description: */
4475/* */
4476/* Is controller initialized ? */
4477/* */
4478/****************************************************************************/
4479static int
4480ips_isinit_copperhead_memio(ips_ha_t * ha)
4481{
4482 uint8_t isr = 0;
4483 uint8_t scpr;
4484
4485 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4486
4487 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4488 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4489
4490 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4491 return (0);
4492 else
4493 return (1);
4494}
4495
4496/****************************************************************************/
4497/* */
4498/* Routine Name: ips_isinit_morpheus */
4499/* */
4500/* Routine Description: */
4501/* */
4502/* Is controller initialized ? */
4503/* */
4504/****************************************************************************/
4505static int
4506ips_isinit_morpheus(ips_ha_t * ha)
4507{
4508 uint32_t post;
4509 uint32_t bits;
4510
4511 METHOD_TRACE("ips_is_init_morpheus", 1);
4512
4513 if (ips_isintr_morpheus(ha))
4514 ips_flush_and_reset(ha);
4515
4516 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4517 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4518
4519 if (post == 0)
4520 return (0);
4521 else if (bits & 0x3)
4522 return (0);
4523 else
4524 return (1);
4525}
4526
4527/****************************************************************************/
4528/* */
4529/* Routine Name: ips_flush_and_reset */
4530/* */
4531/* Routine Description: */
4532/* */
4533/* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */
4534/* state ( was trying to INIT and an interrupt was already pending ) ... */
4535/* */
4536/****************************************************************************/
4537static void
4538ips_flush_and_reset(ips_ha_t *ha)
4539{
4540 ips_scb_t *scb;
4541 int ret;
4542 int time;
4543 int done;
4544 dma_addr_t command_dma;
4545
4546 /* Create a usuable SCB */
4547 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t),
4548 &command_dma, GFP_KERNEL);
4549 if (scb) {
4550 memset(scb, 0, sizeof(ips_scb_t));
4551 ips_init_scb(ha, scb);
4552 scb->scb_busaddr = command_dma;
4553
4554 scb->timeout = ips_cmd_timeout;
4555 scb->cdb[0] = IPS_CMD_FLUSH;
4556
4557 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4558 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */
4559 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4560 scb->cmd.flush_cache.reserved = 0;
4561 scb->cmd.flush_cache.reserved2 = 0;
4562 scb->cmd.flush_cache.reserved3 = 0;
4563 scb->cmd.flush_cache.reserved4 = 0;
4564
4565 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */
4566
4567 if (ret == IPS_SUCCESS) {
4568 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */
4569 done = 0;
4570
4571 while ((time > 0) && (!done)) {
4572 done = ips_poll_for_flush_complete(ha);
4573 /* This may look evil, but it's only done during extremely rare start-up conditions ! */
4574 udelay(1000);
4575 time--;
4576 }
4577 }
4578 }
4579
4580 /* Now RESET and INIT the adapter */
4581 (*ha->func.reset) (ha);
4582
4583 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma);
4584 return;
4585}
4586
4587/****************************************************************************/
4588/* */
4589/* Routine Name: ips_poll_for_flush_complete */
4590/* */
4591/* Routine Description: */
4592/* */
4593/* Poll for the Flush Command issued by ips_flush_and_reset() to complete */
4594/* All other responses are just taken off the queue and ignored */
4595/* */
4596/****************************************************************************/
4597static int
4598ips_poll_for_flush_complete(ips_ha_t * ha)
4599{
4600 IPS_STATUS cstatus;
4601
4602 while (true) {
4603 cstatus.value = (*ha->func.statupd) (ha);
4604
4605 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */
4606 break;
4607
4608 /* Success is when we see the Flush Command ID */
4609 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4610 return 1;
4611 }
4612
4613 return 0;
4614}
4615
4616/****************************************************************************/
4617/* */
4618/* Routine Name: ips_enable_int_copperhead */
4619/* */
4620/* Routine Description: */
4621/* Turn on interrupts */
4622/* */
4623/****************************************************************************/
4624static void
4625ips_enable_int_copperhead(ips_ha_t * ha)
4626{
4627 METHOD_TRACE("ips_enable_int_copperhead", 1);
4628
4629 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4630 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4631}
4632
4633/****************************************************************************/
4634/* */
4635/* Routine Name: ips_enable_int_copperhead_memio */
4636/* */
4637/* Routine Description: */
4638/* Turn on interrupts */
4639/* */
4640/****************************************************************************/
4641static void
4642ips_enable_int_copperhead_memio(ips_ha_t * ha)
4643{
4644 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4645
4646 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4647 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4648}
4649
4650/****************************************************************************/
4651/* */
4652/* Routine Name: ips_enable_int_morpheus */
4653/* */
4654/* Routine Description: */
4655/* Turn on interrupts */
4656/* */
4657/****************************************************************************/
4658static void
4659ips_enable_int_morpheus(ips_ha_t * ha)
4660{
4661 uint32_t Oimr;
4662
4663 METHOD_TRACE("ips_enable_int_morpheus", 1);
4664
4665 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4666 Oimr &= ~0x08;
4667 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4668 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4669}
4670
4671/****************************************************************************/
4672/* */
4673/* Routine Name: ips_init_copperhead */
4674/* */
4675/* Routine Description: */
4676/* */
4677/* Initialize a copperhead controller */
4678/* */
4679/****************************************************************************/
4680static int
4681ips_init_copperhead(ips_ha_t * ha)
4682{
4683 uint8_t Isr;
4684 uint8_t Cbsp;
4685 uint8_t PostByte[IPS_MAX_POST_BYTES];
4686 int i, j;
4687
4688 METHOD_TRACE("ips_init_copperhead", 1);
4689
4690 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4691 for (j = 0; j < 45; j++) {
4692 Isr = inb(ha->io_addr + IPS_REG_HISR);
4693 if (Isr & IPS_BIT_GHI)
4694 break;
4695
4696 /* Delay for 1 Second */
4697 MDELAY(IPS_ONE_SEC);
4698 }
4699
4700 if (j >= 45)
4701 /* error occurred */
4702 return (0);
4703
4704 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4705 outb(Isr, ha->io_addr + IPS_REG_HISR);
4706 }
4707
4708 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4709 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4710 "reset controller fails (post status %x %x).\n",
4711 PostByte[0], PostByte[1]);
4712
4713 return (0);
4714 }
4715
4716 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4717 for (j = 0; j < 240; j++) {
4718 Isr = inb(ha->io_addr + IPS_REG_HISR);
4719 if (Isr & IPS_BIT_GHI)
4720 break;
4721
4722 /* Delay for 1 Second */
4723 MDELAY(IPS_ONE_SEC);
4724 }
4725
4726 if (j >= 240)
4727 /* error occurred */
4728 return (0);
4729
4730 inb(ha->io_addr + IPS_REG_ISPR);
4731 outb(Isr, ha->io_addr + IPS_REG_HISR);
4732 }
4733
4734 for (i = 0; i < 240; i++) {
4735 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4736
4737 if ((Cbsp & IPS_BIT_OP) == 0)
4738 break;
4739
4740 /* Delay for 1 Second */
4741 MDELAY(IPS_ONE_SEC);
4742 }
4743
4744 if (i >= 240)
4745 /* reset failed */
4746 return (0);
4747
4748 /* setup CCCR */
4749 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4750
4751 /* Enable busmastering */
4752 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4753
4754 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4755 /* fix for anaconda64 */
4756 outl(0, ha->io_addr + IPS_REG_NDAE);
4757
4758 /* Enable interrupts */
4759 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4760
4761 return (1);
4762}
4763
4764/****************************************************************************/
4765/* */
4766/* Routine Name: ips_init_copperhead_memio */
4767/* */
4768/* Routine Description: */
4769/* */
4770/* Initialize a copperhead controller with memory mapped I/O */
4771/* */
4772/****************************************************************************/
4773static int
4774ips_init_copperhead_memio(ips_ha_t * ha)
4775{
4776 uint8_t Isr = 0;
4777 uint8_t Cbsp;
4778 uint8_t PostByte[IPS_MAX_POST_BYTES];
4779 int i, j;
4780
4781 METHOD_TRACE("ips_init_copperhead_memio", 1);
4782
4783 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4784 for (j = 0; j < 45; j++) {
4785 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4786 if (Isr & IPS_BIT_GHI)
4787 break;
4788
4789 /* Delay for 1 Second */
4790 MDELAY(IPS_ONE_SEC);
4791 }
4792
4793 if (j >= 45)
4794 /* error occurred */
4795 return (0);
4796
4797 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4798 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4799 }
4800
4801 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4802 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4803 "reset controller fails (post status %x %x).\n",
4804 PostByte[0], PostByte[1]);
4805
4806 return (0);
4807 }
4808
4809 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4810 for (j = 0; j < 240; j++) {
4811 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4812 if (Isr & IPS_BIT_GHI)
4813 break;
4814
4815 /* Delay for 1 Second */
4816 MDELAY(IPS_ONE_SEC);
4817 }
4818
4819 if (j >= 240)
4820 /* error occurred */
4821 return (0);
4822
4823 readb(ha->mem_ptr + IPS_REG_ISPR);
4824 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4825 }
4826
4827 for (i = 0; i < 240; i++) {
4828 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4829
4830 if ((Cbsp & IPS_BIT_OP) == 0)
4831 break;
4832
4833 /* Delay for 1 Second */
4834 MDELAY(IPS_ONE_SEC);
4835 }
4836
4837 if (i >= 240)
4838 /* error occurred */
4839 return (0);
4840
4841 /* setup CCCR */
4842 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4843
4844 /* Enable busmastering */
4845 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4846
4847 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4848 /* fix for anaconda64 */
4849 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4850
4851 /* Enable interrupts */
4852 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4853
4854 /* if we get here then everything went OK */
4855 return (1);
4856}
4857
4858/****************************************************************************/
4859/* */
4860/* Routine Name: ips_init_morpheus */
4861/* */
4862/* Routine Description: */
4863/* */
4864/* Initialize a morpheus controller */
4865/* */
4866/****************************************************************************/
4867static int
4868ips_init_morpheus(ips_ha_t * ha)
4869{
4870 uint32_t Post;
4871 uint32_t Config;
4872 uint32_t Isr;
4873 uint32_t Oimr;
4874 int i;
4875
4876 METHOD_TRACE("ips_init_morpheus", 1);
4877
4878 /* Wait up to 45 secs for Post */
4879 for (i = 0; i < 45; i++) {
4880 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4881
4882 if (Isr & IPS_BIT_I960_MSG0I)
4883 break;
4884
4885 /* Delay for 1 Second */
4886 MDELAY(IPS_ONE_SEC);
4887 }
4888
4889 if (i >= 45) {
4890 /* error occurred */
4891 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4892 "timeout waiting for post.\n");
4893
4894 return (0);
4895 }
4896
4897 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4898
4899 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
4900 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4901 "Flashing Battery PIC, Please wait ...\n");
4902
4903 /* Clear the interrupt bit */
4904 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4905 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4906
4907 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
4908 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4909 if (Post != 0x4F00)
4910 break;
4911 /* Delay for 1 Second */
4912 MDELAY(IPS_ONE_SEC);
4913 }
4914
4915 if (i >= 120) {
4916 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4917 "timeout waiting for Battery PIC Flash\n");
4918 return (0);
4919 }
4920
4921 }
4922
4923 /* Clear the interrupt bit */
4924 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4925 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4926
4927 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4928 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4929 "reset controller fails (post status %x).\n", Post);
4930
4931 return (0);
4932 }
4933
4934 /* Wait up to 240 secs for config bytes */
4935 for (i = 0; i < 240; i++) {
4936 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4937
4938 if (Isr & IPS_BIT_I960_MSG1I)
4939 break;
4940
4941 /* Delay for 1 Second */
4942 MDELAY(IPS_ONE_SEC);
4943 }
4944
4945 if (i >= 240) {
4946 /* error occurred */
4947 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4948 "timeout waiting for config.\n");
4949
4950 return (0);
4951 }
4952
4953 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4954
4955 /* Clear interrupt bit */
4956 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4957 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4958
4959 /* Turn on the interrupts */
4960 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4961 Oimr &= ~0x8;
4962 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4963
4964 /* if we get here then everything went OK */
4965
4966 /* Since we did a RESET, an EraseStripeLock may be needed */
4967 if (Post == 0xEF10) {
4968 if ((Config == 0x000F) || (Config == 0x0009))
4969 ha->requires_esl = 1;
4970 }
4971
4972 return (1);
4973}
4974
4975/****************************************************************************/
4976/* */
4977/* Routine Name: ips_reset_copperhead */
4978/* */
4979/* Routine Description: */
4980/* */
4981/* Reset the controller */
4982/* */
4983/****************************************************************************/
4984static int
4985ips_reset_copperhead(ips_ha_t * ha)
4986{
4987 int reset_counter;
4988
4989 METHOD_TRACE("ips_reset_copperhead", 1);
4990
4991 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
4992 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
4993
4994 reset_counter = 0;
4995
4996 while (reset_counter < 2) {
4997 reset_counter++;
4998
4999 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5000
5001 /* Delay for 1 Second */
5002 MDELAY(IPS_ONE_SEC);
5003
5004 outb(0, ha->io_addr + IPS_REG_SCPR);
5005
5006 /* Delay for 1 Second */
5007 MDELAY(IPS_ONE_SEC);
5008
5009 if ((*ha->func.init) (ha))
5010 break;
5011 else if (reset_counter >= 2) {
5012
5013 return (0);
5014 }
5015 }
5016
5017 return (1);
5018}
5019
5020/****************************************************************************/
5021/* */
5022/* Routine Name: ips_reset_copperhead_memio */
5023/* */
5024/* Routine Description: */
5025/* */
5026/* Reset the controller */
5027/* */
5028/****************************************************************************/
5029static int
5030ips_reset_copperhead_memio(ips_ha_t * ha)
5031{
5032 int reset_counter;
5033
5034 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5035
5036 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5037 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5038
5039 reset_counter = 0;
5040
5041 while (reset_counter < 2) {
5042 reset_counter++;
5043
5044 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5045
5046 /* Delay for 1 Second */
5047 MDELAY(IPS_ONE_SEC);
5048
5049 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5050
5051 /* Delay for 1 Second */
5052 MDELAY(IPS_ONE_SEC);
5053
5054 if ((*ha->func.init) (ha))
5055 break;
5056 else if (reset_counter >= 2) {
5057
5058 return (0);
5059 }
5060 }
5061
5062 return (1);
5063}
5064
5065/****************************************************************************/
5066/* */
5067/* Routine Name: ips_reset_morpheus */
5068/* */
5069/* Routine Description: */
5070/* */
5071/* Reset the controller */
5072/* */
5073/****************************************************************************/
5074static int
5075ips_reset_morpheus(ips_ha_t * ha)
5076{
5077 int reset_counter;
5078 uint8_t junk;
5079
5080 METHOD_TRACE("ips_reset_morpheus", 1);
5081
5082 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5083 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5084
5085 reset_counter = 0;
5086
5087 while (reset_counter < 2) {
5088 reset_counter++;
5089
5090 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5091
5092 /* Delay for 5 Seconds */
5093 MDELAY(5 * IPS_ONE_SEC);
5094
5095 /* Do a PCI config read to wait for adapter */
5096 pci_read_config_byte(ha->pcidev, 4, &junk);
5097
5098 if ((*ha->func.init) (ha))
5099 break;
5100 else if (reset_counter >= 2) {
5101
5102 return (0);
5103 }
5104 }
5105
5106 return (1);
5107}
5108
5109/****************************************************************************/
5110/* */
5111/* Routine Name: ips_statinit */
5112/* */
5113/* Routine Description: */
5114/* */
5115/* Initialize the status queues on the controller */
5116/* */
5117/****************************************************************************/
5118static void
5119ips_statinit(ips_ha_t * ha)
5120{
5121 uint32_t phys_status_start;
5122
5123 METHOD_TRACE("ips_statinit", 1);
5124
5125 ha->adapt->p_status_start = ha->adapt->status;
5126 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5127 ha->adapt->p_status_tail = ha->adapt->status;
5128
5129 phys_status_start = ha->adapt->hw_status_start;
5130 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5131 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5132 ha->io_addr + IPS_REG_SQER);
5133 outl(phys_status_start + IPS_STATUS_SIZE,
5134 ha->io_addr + IPS_REG_SQHR);
5135 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5136
5137 ha->adapt->hw_status_tail = phys_status_start;
5138}
5139
5140/****************************************************************************/
5141/* */
5142/* Routine Name: ips_statinit_memio */
5143/* */
5144/* Routine Description: */
5145/* */
5146/* Initialize the status queues on the controller */
5147/* */
5148/****************************************************************************/
5149static void
5150ips_statinit_memio(ips_ha_t * ha)
5151{
5152 uint32_t phys_status_start;
5153
5154 METHOD_TRACE("ips_statinit_memio", 1);
5155
5156 ha->adapt->p_status_start = ha->adapt->status;
5157 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5158 ha->adapt->p_status_tail = ha->adapt->status;
5159
5160 phys_status_start = ha->adapt->hw_status_start;
5161 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5162 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5163 ha->mem_ptr + IPS_REG_SQER);
5164 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5165 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5166
5167 ha->adapt->hw_status_tail = phys_status_start;
5168}
5169
5170/****************************************************************************/
5171/* */
5172/* Routine Name: ips_statupd_copperhead */
5173/* */
5174/* Routine Description: */
5175/* */
5176/* Remove an element from the status queue */
5177/* */
5178/****************************************************************************/
5179static uint32_t
5180ips_statupd_copperhead(ips_ha_t * ha)
5181{
5182 METHOD_TRACE("ips_statupd_copperhead", 1);
5183
5184 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5185 ha->adapt->p_status_tail++;
5186 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5187 } else {
5188 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5189 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5190 }
5191
5192 outl(ha->adapt->hw_status_tail,
5193 ha->io_addr + IPS_REG_SQTR);
5194
5195 return (ha->adapt->p_status_tail->value);
5196}
5197
5198/****************************************************************************/
5199/* */
5200/* Routine Name: ips_statupd_copperhead_memio */
5201/* */
5202/* Routine Description: */
5203/* */
5204/* Remove an element from the status queue */
5205/* */
5206/****************************************************************************/
5207static uint32_t
5208ips_statupd_copperhead_memio(ips_ha_t * ha)
5209{
5210 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5211
5212 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5213 ha->adapt->p_status_tail++;
5214 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5215 } else {
5216 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5217 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5218 }
5219
5220 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5221
5222 return (ha->adapt->p_status_tail->value);
5223}
5224
5225/****************************************************************************/
5226/* */
5227/* Routine Name: ips_statupd_morpheus */
5228/* */
5229/* Routine Description: */
5230/* */
5231/* Remove an element from the status queue */
5232/* */
5233/****************************************************************************/
5234static uint32_t
5235ips_statupd_morpheus(ips_ha_t * ha)
5236{
5237 uint32_t val;
5238
5239 METHOD_TRACE("ips_statupd_morpheus", 1);
5240
5241 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5242
5243 return (val);
5244}
5245
5246/****************************************************************************/
5247/* */
5248/* Routine Name: ips_issue_copperhead */
5249/* */
5250/* Routine Description: */
5251/* */
5252/* Send a command down to the controller */
5253/* */
5254/****************************************************************************/
5255static int
5256ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5257{
5258 uint32_t TimeOut;
5259 uint32_t val;
5260
5261 METHOD_TRACE("ips_issue_copperhead", 1);
5262
5263 if (scb->scsi_cmd) {
5264 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5265 ips_name,
5266 ha->host_num,
5267 scb->cdb[0],
5268 scb->cmd.basic_io.command_id,
5269 scb->bus, scb->target_id, scb->lun);
5270 } else {
5271 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5272 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5273 }
5274
5275 TimeOut = 0;
5276
5277 while ((val =
5278 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5279 udelay(1000);
5280
5281 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5282 if (!(val & IPS_BIT_START_STOP))
5283 break;
5284
5285 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5286 "ips_issue val [0x%x].\n", val);
5287 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5288 "ips_issue semaphore chk timeout.\n");
5289
5290 return (IPS_FAILURE);
5291 } /* end if */
5292 } /* end while */
5293
5294 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5295 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5296
5297 return (IPS_SUCCESS);
5298}
5299
5300/****************************************************************************/
5301/* */
5302/* Routine Name: ips_issue_copperhead_memio */
5303/* */
5304/* Routine Description: */
5305/* */
5306/* Send a command down to the controller */
5307/* */
5308/****************************************************************************/
5309static int
5310ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5311{
5312 uint32_t TimeOut;
5313 uint32_t val;
5314
5315 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5316
5317 if (scb->scsi_cmd) {
5318 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5319 ips_name,
5320 ha->host_num,
5321 scb->cdb[0],
5322 scb->cmd.basic_io.command_id,
5323 scb->bus, scb->target_id, scb->lun);
5324 } else {
5325 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5326 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5327 }
5328
5329 TimeOut = 0;
5330
5331 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5332 udelay(1000);
5333
5334 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5335 if (!(val & IPS_BIT_START_STOP))
5336 break;
5337
5338 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5339 "ips_issue val [0x%x].\n", val);
5340 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5341 "ips_issue semaphore chk timeout.\n");
5342
5343 return (IPS_FAILURE);
5344 } /* end if */
5345 } /* end while */
5346
5347 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5348 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5349
5350 return (IPS_SUCCESS);
5351}
5352
5353/****************************************************************************/
5354/* */
5355/* Routine Name: ips_issue_i2o */
5356/* */
5357/* Routine Description: */
5358/* */
5359/* Send a command down to the controller */
5360/* */
5361/****************************************************************************/
5362static int
5363ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5364{
5365
5366 METHOD_TRACE("ips_issue_i2o", 1);
5367
5368 if (scb->scsi_cmd) {
5369 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5370 ips_name,
5371 ha->host_num,
5372 scb->cdb[0],
5373 scb->cmd.basic_io.command_id,
5374 scb->bus, scb->target_id, scb->lun);
5375 } else {
5376 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5377 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5378 }
5379
5380 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5381
5382 return (IPS_SUCCESS);
5383}
5384
5385/****************************************************************************/
5386/* */
5387/* Routine Name: ips_issue_i2o_memio */
5388/* */
5389/* Routine Description: */
5390/* */
5391/* Send a command down to the controller */
5392/* */
5393/****************************************************************************/
5394static int
5395ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5396{
5397
5398 METHOD_TRACE("ips_issue_i2o_memio", 1);
5399
5400 if (scb->scsi_cmd) {
5401 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5402 ips_name,
5403 ha->host_num,
5404 scb->cdb[0],
5405 scb->cmd.basic_io.command_id,
5406 scb->bus, scb->target_id, scb->lun);
5407 } else {
5408 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5409 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5410 }
5411
5412 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5413
5414 return (IPS_SUCCESS);
5415}
5416
5417/****************************************************************************/
5418/* */
5419/* Routine Name: ips_isintr_copperhead */
5420/* */
5421/* Routine Description: */
5422/* */
5423/* Test to see if an interrupt is for us */
5424/* */
5425/****************************************************************************/
5426static int
5427ips_isintr_copperhead(ips_ha_t * ha)
5428{
5429 uint8_t Isr;
5430
5431 METHOD_TRACE("ips_isintr_copperhead", 2);
5432
5433 Isr = inb(ha->io_addr + IPS_REG_HISR);
5434
5435 if (Isr == 0xFF)
5436 /* ?!?! Nothing really there */
5437 return (0);
5438
5439 if (Isr & IPS_BIT_SCE)
5440 return (1);
5441 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5442 /* status queue overflow or GHI */
5443 /* just clear the interrupt */
5444 outb(Isr, ha->io_addr + IPS_REG_HISR);
5445 }
5446
5447 return (0);
5448}
5449
5450/****************************************************************************/
5451/* */
5452/* Routine Name: ips_isintr_copperhead_memio */
5453/* */
5454/* Routine Description: */
5455/* */
5456/* Test to see if an interrupt is for us */
5457/* */
5458/****************************************************************************/
5459static int
5460ips_isintr_copperhead_memio(ips_ha_t * ha)
5461{
5462 uint8_t Isr;
5463
5464 METHOD_TRACE("ips_isintr_memio", 2);
5465
5466 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5467
5468 if (Isr == 0xFF)
5469 /* ?!?! Nothing really there */
5470 return (0);
5471
5472 if (Isr & IPS_BIT_SCE)
5473 return (1);
5474 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5475 /* status queue overflow or GHI */
5476 /* just clear the interrupt */
5477 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5478 }
5479
5480 return (0);
5481}
5482
5483/****************************************************************************/
5484/* */
5485/* Routine Name: ips_isintr_morpheus */
5486/* */
5487/* Routine Description: */
5488/* */
5489/* Test to see if an interrupt is for us */
5490/* */
5491/****************************************************************************/
5492static int
5493ips_isintr_morpheus(ips_ha_t * ha)
5494{
5495 uint32_t Isr;
5496
5497 METHOD_TRACE("ips_isintr_morpheus", 2);
5498
5499 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5500
5501 if (Isr & IPS_BIT_I2O_OPQI)
5502 return (1);
5503 else
5504 return (0);
5505}
5506
5507/****************************************************************************/
5508/* */
5509/* Routine Name: ips_wait */
5510/* */
5511/* Routine Description: */
5512/* */
5513/* Wait for a command to complete */
5514/* */
5515/****************************************************************************/
5516static int
5517ips_wait(ips_ha_t * ha, int time, int intr)
5518{
5519 int ret;
5520 int done;
5521
5522 METHOD_TRACE("ips_wait", 1);
5523
5524 ret = IPS_FAILURE;
5525 done = false;
5526
5527 time *= IPS_ONE_SEC; /* convert seconds */
5528
5529 while ((time > 0) && (!done)) {
5530 if (intr == IPS_INTR_ON) {
5531 if (!ha->waitflag) {
5532 ret = IPS_SUCCESS;
5533 done = true;
5534 break;
5535 }
5536 } else if (intr == IPS_INTR_IORL) {
5537 if (!ha->waitflag) {
5538 /*
5539 * controller generated an interrupt to
5540 * acknowledge completion of the command
5541 * and ips_intr() has serviced the interrupt.
5542 */
5543 ret = IPS_SUCCESS;
5544 done = true;
5545 break;
5546 }
5547
5548 /*
5549 * NOTE: we already have the io_request_lock so
5550 * even if we get an interrupt it won't get serviced
5551 * until after we finish.
5552 */
5553
5554 (*ha->func.intr) (ha);
5555 }
5556
5557 /* This looks like a very evil loop, but it only does this during start-up */
5558 udelay(1000);
5559 time--;
5560 }
5561
5562 return (ret);
5563}
5564
5565/****************************************************************************/
5566/* */
5567/* Routine Name: ips_write_driver_status */
5568/* */
5569/* Routine Description: */
5570/* */
5571/* Write OS/Driver version to Page 5 of the nvram on the controller */
5572/* */
5573/****************************************************************************/
5574static int
5575ips_write_driver_status(ips_ha_t * ha, int intr)
5576{
5577 METHOD_TRACE("ips_write_driver_status", 1);
5578
5579 if (!ips_readwrite_page5(ha, false, intr)) {
5580 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5581 "unable to read NVRAM page 5.\n");
5582
5583 return (0);
5584 }
5585
5586 /* check to make sure the page has a valid */
5587 /* signature */
5588 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5589 DEBUG_VAR(1,
5590 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5591 ips_name, ha->host_num, ha->nvram->signature);
5592 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5593 }
5594
5595 DEBUG_VAR(2,
5596 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5597 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5598 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5599 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5600 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5601 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5602 ha->nvram->bios_low[3]);
5603
5604 ips_get_bios_version(ha, intr);
5605
5606 /* change values (as needed) */
5607 ha->nvram->operating_system = IPS_OS_LINUX;
5608 ha->nvram->adapter_type = ha->ad_type;
5609 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5610 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5611 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5612 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5613
5614 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */
5615
5616 /* now update the page */
5617 if (!ips_readwrite_page5(ha, true, intr)) {
5618 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5619 "unable to write NVRAM page 5.\n");
5620
5621 return (0);
5622 }
5623
5624 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5625 ha->slot_num = ha->nvram->adapter_slot;
5626
5627 return (1);
5628}
5629
5630/****************************************************************************/
5631/* */
5632/* Routine Name: ips_read_adapter_status */
5633/* */
5634/* Routine Description: */
5635/* */
5636/* Do an Inquiry command to the adapter */
5637/* */
5638/****************************************************************************/
5639static int
5640ips_read_adapter_status(ips_ha_t * ha, int intr)
5641{
5642 ips_scb_t *scb;
5643 int ret;
5644
5645 METHOD_TRACE("ips_read_adapter_status", 1);
5646
5647 scb = &ha->scbs[ha->max_cmds - 1];
5648
5649 ips_init_scb(ha, scb);
5650
5651 scb->timeout = ips_cmd_timeout;
5652 scb->cdb[0] = IPS_CMD_ENQUIRY;
5653
5654 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5655 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5656 scb->cmd.basic_io.sg_count = 0;
5657 scb->cmd.basic_io.lba = 0;
5658 scb->cmd.basic_io.sector_count = 0;
5659 scb->cmd.basic_io.log_drv = 0;
5660 scb->data_len = sizeof (*ha->enq);
5661 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5662
5663 /* send command */
5664 if (((ret =
5665 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5666 || (ret == IPS_SUCCESS_IMM)
5667 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5668 return (0);
5669
5670 return (1);
5671}
5672
5673/****************************************************************************/
5674/* */
5675/* Routine Name: ips_read_subsystem_parameters */
5676/* */
5677/* Routine Description: */
5678/* */
5679/* Read subsystem parameters from the adapter */
5680/* */
5681/****************************************************************************/
5682static int
5683ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5684{
5685 ips_scb_t *scb;
5686 int ret;
5687
5688 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5689
5690 scb = &ha->scbs[ha->max_cmds - 1];
5691
5692 ips_init_scb(ha, scb);
5693
5694 scb->timeout = ips_cmd_timeout;
5695 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5696
5697 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5698 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5699 scb->cmd.basic_io.sg_count = 0;
5700 scb->cmd.basic_io.lba = 0;
5701 scb->cmd.basic_io.sector_count = 0;
5702 scb->cmd.basic_io.log_drv = 0;
5703 scb->data_len = sizeof (*ha->subsys);
5704 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5705
5706 /* send command */
5707 if (((ret =
5708 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5709 || (ret == IPS_SUCCESS_IMM)
5710 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5711 return (0);
5712
5713 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5714 return (1);
5715}
5716
5717/****************************************************************************/
5718/* */
5719/* Routine Name: ips_read_config */
5720/* */
5721/* Routine Description: */
5722/* */
5723/* Read the configuration on the adapter */
5724/* */
5725/****************************************************************************/
5726static int
5727ips_read_config(ips_ha_t * ha, int intr)
5728{
5729 ips_scb_t *scb;
5730 int i;
5731 int ret;
5732
5733 METHOD_TRACE("ips_read_config", 1);
5734
5735 /* set defaults for initiator IDs */
5736 for (i = 0; i < 4; i++)
5737 ha->conf->init_id[i] = 7;
5738
5739 scb = &ha->scbs[ha->max_cmds - 1];
5740
5741 ips_init_scb(ha, scb);
5742
5743 scb->timeout = ips_cmd_timeout;
5744 scb->cdb[0] = IPS_CMD_READ_CONF;
5745
5746 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5747 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5748 scb->data_len = sizeof (*ha->conf);
5749 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5750
5751 /* send command */
5752 if (((ret =
5753 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5754 || (ret == IPS_SUCCESS_IMM)
5755 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5756
5757 memset(ha->conf, 0, sizeof (IPS_CONF));
5758
5759 /* reset initiator IDs */
5760 for (i = 0; i < 4; i++)
5761 ha->conf->init_id[i] = 7;
5762
5763 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5764 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5765 IPS_CMD_CMPLT_WERROR)
5766 return (1);
5767
5768 return (0);
5769 }
5770
5771 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5772 return (1);
5773}
5774
5775/****************************************************************************/
5776/* */
5777/* Routine Name: ips_readwrite_page5 */
5778/* */
5779/* Routine Description: */
5780/* */
5781/* Read nvram page 5 from the adapter */
5782/* */
5783/****************************************************************************/
5784static int
5785ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5786{
5787 ips_scb_t *scb;
5788 int ret;
5789
5790 METHOD_TRACE("ips_readwrite_page5", 1);
5791
5792 scb = &ha->scbs[ha->max_cmds - 1];
5793
5794 ips_init_scb(ha, scb);
5795
5796 scb->timeout = ips_cmd_timeout;
5797 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5798
5799 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5800 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5801 scb->cmd.nvram.page = 5;
5802 scb->cmd.nvram.write = write;
5803 scb->cmd.nvram.reserved = 0;
5804 scb->cmd.nvram.reserved2 = 0;
5805 scb->data_len = sizeof (*ha->nvram);
5806 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5807 if (write)
5808 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5809
5810 /* issue the command */
5811 if (((ret =
5812 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5813 || (ret == IPS_SUCCESS_IMM)
5814 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5815
5816 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5817
5818 return (0);
5819 }
5820 if (!write)
5821 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5822 return (1);
5823}
5824
5825/****************************************************************************/
5826/* */
5827/* Routine Name: ips_clear_adapter */
5828/* */
5829/* Routine Description: */
5830/* */
5831/* Clear the stripe lock tables */
5832/* */
5833/****************************************************************************/
5834static int
5835ips_clear_adapter(ips_ha_t * ha, int intr)
5836{
5837 ips_scb_t *scb;
5838 int ret;
5839
5840 METHOD_TRACE("ips_clear_adapter", 1);
5841
5842 scb = &ha->scbs[ha->max_cmds - 1];
5843
5844 ips_init_scb(ha, scb);
5845
5846 scb->timeout = ips_reset_timeout;
5847 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5848
5849 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5850 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5851 scb->cmd.config_sync.channel = 0;
5852 scb->cmd.config_sync.source_target = IPS_POCL;
5853 scb->cmd.config_sync.reserved = 0;
5854 scb->cmd.config_sync.reserved2 = 0;
5855 scb->cmd.config_sync.reserved3 = 0;
5856
5857 /* issue command */
5858 if (((ret =
5859 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5860 || (ret == IPS_SUCCESS_IMM)
5861 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5862 return (0);
5863
5864 /* send unlock stripe command */
5865 ips_init_scb(ha, scb);
5866
5867 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5868 scb->timeout = ips_reset_timeout;
5869
5870 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5871 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5872 scb->cmd.unlock_stripe.log_drv = 0;
5873 scb->cmd.unlock_stripe.control = IPS_CSL;
5874 scb->cmd.unlock_stripe.reserved = 0;
5875 scb->cmd.unlock_stripe.reserved2 = 0;
5876 scb->cmd.unlock_stripe.reserved3 = 0;
5877
5878 /* issue command */
5879 if (((ret =
5880 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5881 || (ret == IPS_SUCCESS_IMM)
5882 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5883 return (0);
5884
5885 return (1);
5886}
5887
5888/****************************************************************************/
5889/* */
5890/* Routine Name: ips_ffdc_reset */
5891/* */
5892/* Routine Description: */
5893/* */
5894/* FFDC: write reset info */
5895/* */
5896/****************************************************************************/
5897static void
5898ips_ffdc_reset(ips_ha_t * ha, int intr)
5899{
5900 ips_scb_t *scb;
5901
5902 METHOD_TRACE("ips_ffdc_reset", 1);
5903
5904 scb = &ha->scbs[ha->max_cmds - 1];
5905
5906 ips_init_scb(ha, scb);
5907
5908 scb->timeout = ips_cmd_timeout;
5909 scb->cdb[0] = IPS_CMD_FFDC;
5910 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5911 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5912 scb->cmd.ffdc.reset_count = ha->reset_count;
5913 scb->cmd.ffdc.reset_type = 0x80;
5914
5915 /* convert time to what the card wants */
5916 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5917
5918 /* issue command */
5919 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5920}
5921
5922/****************************************************************************/
5923/* */
5924/* Routine Name: ips_ffdc_time */
5925/* */
5926/* Routine Description: */
5927/* */
5928/* FFDC: write time info */
5929/* */
5930/****************************************************************************/
5931static void
5932ips_ffdc_time(ips_ha_t * ha)
5933{
5934 ips_scb_t *scb;
5935
5936 METHOD_TRACE("ips_ffdc_time", 1);
5937
5938 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5939
5940 scb = &ha->scbs[ha->max_cmds - 1];
5941
5942 ips_init_scb(ha, scb);
5943
5944 scb->timeout = ips_cmd_timeout;
5945 scb->cdb[0] = IPS_CMD_FFDC;
5946 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5947 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5948 scb->cmd.ffdc.reset_count = 0;
5949 scb->cmd.ffdc.reset_type = 0;
5950
5951 /* convert time to what the card wants */
5952 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5953
5954 /* issue command */
5955 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5956}
5957
5958/****************************************************************************/
5959/* */
5960/* Routine Name: ips_fix_ffdc_time */
5961/* */
5962/* Routine Description: */
5963/* Adjust time_t to what the card wants */
5964/* */
5965/****************************************************************************/
5966static void
5967ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time)
5968{
5969 struct tm tm;
5970
5971 METHOD_TRACE("ips_fix_ffdc_time", 1);
5972
5973 time64_to_tm(current_time, 0, &tm);
5974
5975 scb->cmd.ffdc.hour = tm.tm_hour;
5976 scb->cmd.ffdc.minute = tm.tm_min;
5977 scb->cmd.ffdc.second = tm.tm_sec;
5978 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100;
5979 scb->cmd.ffdc.yearL = tm.tm_year % 100;
5980 scb->cmd.ffdc.month = tm.tm_mon + 1;
5981 scb->cmd.ffdc.day = tm.tm_mday;
5982}
5983
5984/****************************************************************************
5985 * BIOS Flash Routines *
5986 ****************************************************************************/
5987
5988/****************************************************************************/
5989/* */
5990/* Routine Name: ips_erase_bios */
5991/* */
5992/* Routine Description: */
5993/* Erase the BIOS on the adapter */
5994/* */
5995/****************************************************************************/
5996static int
5997ips_erase_bios(ips_ha_t * ha)
5998{
5999 int timeout;
6000 uint8_t status = 0;
6001
6002 METHOD_TRACE("ips_erase_bios", 1);
6003
6004 status = 0;
6005
6006 /* Clear the status register */
6007 outl(0, ha->io_addr + IPS_REG_FLAP);
6008 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6009 udelay(25); /* 25 us */
6010
6011 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6012 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6013 udelay(25); /* 25 us */
6014
6015 /* Erase Setup */
6016 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6017 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6018 udelay(25); /* 25 us */
6019
6020 /* Erase Confirm */
6021 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6022 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6023 udelay(25); /* 25 us */
6024
6025 /* Erase Status */
6026 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6027 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6028 udelay(25); /* 25 us */
6029
6030 timeout = 80000; /* 80 seconds */
6031
6032 while (timeout > 0) {
6033 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6034 outl(0, ha->io_addr + IPS_REG_FLAP);
6035 udelay(25); /* 25 us */
6036 }
6037
6038 status = inb(ha->io_addr + IPS_REG_FLDP);
6039
6040 if (status & 0x80)
6041 break;
6042
6043 MDELAY(1);
6044 timeout--;
6045 }
6046
6047 /* check for timeout */
6048 if (timeout <= 0) {
6049 /* timeout */
6050
6051 /* try to suspend the erase */
6052 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6053 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6054 udelay(25); /* 25 us */
6055
6056 /* wait for 10 seconds */
6057 timeout = 10000;
6058 while (timeout > 0) {
6059 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6060 outl(0, ha->io_addr + IPS_REG_FLAP);
6061 udelay(25); /* 25 us */
6062 }
6063
6064 status = inb(ha->io_addr + IPS_REG_FLDP);
6065
6066 if (status & 0xC0)
6067 break;
6068
6069 MDELAY(1);
6070 timeout--;
6071 }
6072
6073 return (1);
6074 }
6075
6076 /* check for valid VPP */
6077 if (status & 0x08)
6078 /* VPP failure */
6079 return (1);
6080
6081 /* check for successful flash */
6082 if (status & 0x30)
6083 /* sequence error */
6084 return (1);
6085
6086 /* Otherwise, we were successful */
6087 /* clear status */
6088 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6089 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6090 udelay(25); /* 25 us */
6091
6092 /* enable reads */
6093 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6094 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6095 udelay(25); /* 25 us */
6096
6097 return (0);
6098}
6099
6100/****************************************************************************/
6101/* */
6102/* Routine Name: ips_erase_bios_memio */
6103/* */
6104/* Routine Description: */
6105/* Erase the BIOS on the adapter */
6106/* */
6107/****************************************************************************/
6108static int
6109ips_erase_bios_memio(ips_ha_t * ha)
6110{
6111 int timeout;
6112 uint8_t status;
6113
6114 METHOD_TRACE("ips_erase_bios_memio", 1);
6115
6116 status = 0;
6117
6118 /* Clear the status register */
6119 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6120 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6121 udelay(25); /* 25 us */
6122
6123 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6124 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6125 udelay(25); /* 25 us */
6126
6127 /* Erase Setup */
6128 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6129 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6130 udelay(25); /* 25 us */
6131
6132 /* Erase Confirm */
6133 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6134 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6135 udelay(25); /* 25 us */
6136
6137 /* Erase Status */
6138 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6139 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6140 udelay(25); /* 25 us */
6141
6142 timeout = 80000; /* 80 seconds */
6143
6144 while (timeout > 0) {
6145 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6146 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6147 udelay(25); /* 25 us */
6148 }
6149
6150 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6151
6152 if (status & 0x80)
6153 break;
6154
6155 MDELAY(1);
6156 timeout--;
6157 }
6158
6159 /* check for timeout */
6160 if (timeout <= 0) {
6161 /* timeout */
6162
6163 /* try to suspend the erase */
6164 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6165 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6166 udelay(25); /* 25 us */
6167
6168 /* wait for 10 seconds */
6169 timeout = 10000;
6170 while (timeout > 0) {
6171 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6172 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6173 udelay(25); /* 25 us */
6174 }
6175
6176 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6177
6178 if (status & 0xC0)
6179 break;
6180
6181 MDELAY(1);
6182 timeout--;
6183 }
6184
6185 return (1);
6186 }
6187
6188 /* check for valid VPP */
6189 if (status & 0x08)
6190 /* VPP failure */
6191 return (1);
6192
6193 /* check for successful flash */
6194 if (status & 0x30)
6195 /* sequence error */
6196 return (1);
6197
6198 /* Otherwise, we were successful */
6199 /* clear status */
6200 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6201 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6202 udelay(25); /* 25 us */
6203
6204 /* enable reads */
6205 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6206 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6207 udelay(25); /* 25 us */
6208
6209 return (0);
6210}
6211
6212/****************************************************************************/
6213/* */
6214/* Routine Name: ips_program_bios */
6215/* */
6216/* Routine Description: */
6217/* Program the BIOS on the adapter */
6218/* */
6219/****************************************************************************/
6220static int
6221ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6222 uint32_t offset)
6223{
6224 int i;
6225 int timeout;
6226 uint8_t status = 0;
6227
6228 METHOD_TRACE("ips_program_bios", 1);
6229
6230 status = 0;
6231
6232 for (i = 0; i < buffersize; i++) {
6233 /* write a byte */
6234 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6235 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6236 udelay(25); /* 25 us */
6237
6238 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6239 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6240 udelay(25); /* 25 us */
6241
6242 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6243 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6244 udelay(25); /* 25 us */
6245
6246 /* wait up to one second */
6247 timeout = 1000;
6248 while (timeout > 0) {
6249 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6250 outl(0, ha->io_addr + IPS_REG_FLAP);
6251 udelay(25); /* 25 us */
6252 }
6253
6254 status = inb(ha->io_addr + IPS_REG_FLDP);
6255
6256 if (status & 0x80)
6257 break;
6258
6259 MDELAY(1);
6260 timeout--;
6261 }
6262
6263 if (timeout == 0) {
6264 /* timeout error */
6265 outl(0, ha->io_addr + IPS_REG_FLAP);
6266 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6267 udelay(25); /* 25 us */
6268
6269 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6270 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6271 udelay(25); /* 25 us */
6272
6273 return (1);
6274 }
6275
6276 /* check the status */
6277 if (status & 0x18) {
6278 /* programming error */
6279 outl(0, ha->io_addr + IPS_REG_FLAP);
6280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6281 udelay(25); /* 25 us */
6282
6283 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6284 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6285 udelay(25); /* 25 us */
6286
6287 return (1);
6288 }
6289 } /* end for */
6290
6291 /* Enable reading */
6292 outl(0, ha->io_addr + IPS_REG_FLAP);
6293 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6294 udelay(25); /* 25 us */
6295
6296 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6297 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6298 udelay(25); /* 25 us */
6299
6300 return (0);
6301}
6302
6303/****************************************************************************/
6304/* */
6305/* Routine Name: ips_program_bios_memio */
6306/* */
6307/* Routine Description: */
6308/* Program the BIOS on the adapter */
6309/* */
6310/****************************************************************************/
6311static int
6312ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6313 uint32_t offset)
6314{
6315 int i;
6316 int timeout;
6317 uint8_t status = 0;
6318
6319 METHOD_TRACE("ips_program_bios_memio", 1);
6320
6321 status = 0;
6322
6323 for (i = 0; i < buffersize; i++) {
6324 /* write a byte */
6325 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6326 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6327 udelay(25); /* 25 us */
6328
6329 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6330 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6331 udelay(25); /* 25 us */
6332
6333 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6334 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6335 udelay(25); /* 25 us */
6336
6337 /* wait up to one second */
6338 timeout = 1000;
6339 while (timeout > 0) {
6340 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6341 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6342 udelay(25); /* 25 us */
6343 }
6344
6345 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6346
6347 if (status & 0x80)
6348 break;
6349
6350 MDELAY(1);
6351 timeout--;
6352 }
6353
6354 if (timeout == 0) {
6355 /* timeout error */
6356 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6357 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6358 udelay(25); /* 25 us */
6359
6360 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6361 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6362 udelay(25); /* 25 us */
6363
6364 return (1);
6365 }
6366
6367 /* check the status */
6368 if (status & 0x18) {
6369 /* programming error */
6370 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6371 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6372 udelay(25); /* 25 us */
6373
6374 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6375 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6376 udelay(25); /* 25 us */
6377
6378 return (1);
6379 }
6380 } /* end for */
6381
6382 /* Enable reading */
6383 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6384 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6385 udelay(25); /* 25 us */
6386
6387 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6389 udelay(25); /* 25 us */
6390
6391 return (0);
6392}
6393
6394/****************************************************************************/
6395/* */
6396/* Routine Name: ips_verify_bios */
6397/* */
6398/* Routine Description: */
6399/* Verify the BIOS on the adapter */
6400/* */
6401/****************************************************************************/
6402static int
6403ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6404 uint32_t offset)
6405{
6406 uint8_t checksum;
6407 int i;
6408
6409 METHOD_TRACE("ips_verify_bios", 1);
6410
6411 /* test 1st byte */
6412 outl(0, ha->io_addr + IPS_REG_FLAP);
6413 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6414 udelay(25); /* 25 us */
6415
6416 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6417 return (1);
6418
6419 outl(1, ha->io_addr + IPS_REG_FLAP);
6420 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6421 udelay(25); /* 25 us */
6422 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6423 return (1);
6424
6425 checksum = 0xff;
6426 for (i = 2; i < buffersize; i++) {
6427
6428 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6429 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6430 udelay(25); /* 25 us */
6431
6432 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6433 }
6434
6435 if (checksum != 0)
6436 /* failure */
6437 return (1);
6438 else
6439 /* success */
6440 return (0);
6441}
6442
6443/****************************************************************************/
6444/* */
6445/* Routine Name: ips_verify_bios_memio */
6446/* */
6447/* Routine Description: */
6448/* Verify the BIOS on the adapter */
6449/* */
6450/****************************************************************************/
6451static int
6452ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6453 uint32_t offset)
6454{
6455 uint8_t checksum;
6456 int i;
6457
6458 METHOD_TRACE("ips_verify_bios_memio", 1);
6459
6460 /* test 1st byte */
6461 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6462 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6463 udelay(25); /* 25 us */
6464
6465 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6466 return (1);
6467
6468 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6469 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6470 udelay(25); /* 25 us */
6471 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6472 return (1);
6473
6474 checksum = 0xff;
6475 for (i = 2; i < buffersize; i++) {
6476
6477 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6478 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6479 udelay(25); /* 25 us */
6480
6481 checksum =
6482 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6483 }
6484
6485 if (checksum != 0)
6486 /* failure */
6487 return (1);
6488 else
6489 /* success */
6490 return (0);
6491}
6492
6493/****************************************************************************/
6494/* */
6495/* Routine Name: ips_abort_init */
6496/* */
6497/* Routine Description: */
6498/* cleanup routine for a failed adapter initialization */
6499/****************************************************************************/
6500static int
6501ips_abort_init(ips_ha_t * ha, int index)
6502{
6503 ha->active = 0;
6504 ips_free(ha);
6505 ips_ha[index] = NULL;
6506 ips_sh[index] = NULL;
6507 return -1;
6508}
6509
6510/****************************************************************************/
6511/* */
6512/* Routine Name: ips_shift_controllers */
6513/* */
6514/* Routine Description: */
6515/* helper function for ordering adapters */
6516/****************************************************************************/
6517static void
6518ips_shift_controllers(int lowindex, int highindex)
6519{
6520 ips_ha_t *ha_sav = ips_ha[highindex];
6521 struct Scsi_Host *sh_sav = ips_sh[highindex];
6522 int i;
6523
6524 for (i = highindex; i > lowindex; i--) {
6525 ips_ha[i] = ips_ha[i - 1];
6526 ips_sh[i] = ips_sh[i - 1];
6527 ips_ha[i]->host_num = i;
6528 }
6529 ha_sav->host_num = lowindex;
6530 ips_ha[lowindex] = ha_sav;
6531 ips_sh[lowindex] = sh_sav;
6532}
6533
6534/****************************************************************************/
6535/* */
6536/* Routine Name: ips_order_controllers */
6537/* */
6538/* Routine Description: */
6539/* place controllers is the "proper" boot order */
6540/****************************************************************************/
6541static void
6542ips_order_controllers(void)
6543{
6544 int i, j, tmp, position = 0;
6545 IPS_NVRAM_P5 *nvram;
6546 if (!ips_ha[0])
6547 return;
6548 nvram = ips_ha[0]->nvram;
6549
6550 if (nvram->adapter_order[0]) {
6551 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6552 for (j = position; j < ips_num_controllers; j++) {
6553 switch (ips_ha[j]->ad_type) {
6554 case IPS_ADTYPE_SERVERAID6M:
6555 case IPS_ADTYPE_SERVERAID7M:
6556 if (nvram->adapter_order[i] == 'M') {
6557 ips_shift_controllers(position,
6558 j);
6559 position++;
6560 }
6561 break;
6562 case IPS_ADTYPE_SERVERAID4L:
6563 case IPS_ADTYPE_SERVERAID4M:
6564 case IPS_ADTYPE_SERVERAID4MX:
6565 case IPS_ADTYPE_SERVERAID4LX:
6566 if (nvram->adapter_order[i] == 'N') {
6567 ips_shift_controllers(position,
6568 j);
6569 position++;
6570 }
6571 break;
6572 case IPS_ADTYPE_SERVERAID6I:
6573 case IPS_ADTYPE_SERVERAID5I2:
6574 case IPS_ADTYPE_SERVERAID5I1:
6575 case IPS_ADTYPE_SERVERAID7k:
6576 if (nvram->adapter_order[i] == 'S') {
6577 ips_shift_controllers(position,
6578 j);
6579 position++;
6580 }
6581 break;
6582 case IPS_ADTYPE_SERVERAID:
6583 case IPS_ADTYPE_SERVERAID2:
6584 case IPS_ADTYPE_NAVAJO:
6585 case IPS_ADTYPE_KIOWA:
6586 case IPS_ADTYPE_SERVERAID3L:
6587 case IPS_ADTYPE_SERVERAID3:
6588 case IPS_ADTYPE_SERVERAID4H:
6589 if (nvram->adapter_order[i] == 'A') {
6590 ips_shift_controllers(position,
6591 j);
6592 position++;
6593 }
6594 break;
6595 default:
6596 break;
6597 }
6598 }
6599 }
6600 /* if adapter_order[0], then ordering is complete */
6601 return;
6602 }
6603 /* old bios, use older ordering */
6604 tmp = 0;
6605 for (i = position; i < ips_num_controllers; i++) {
6606 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6607 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6608 ips_shift_controllers(position, i);
6609 position++;
6610 tmp = 1;
6611 }
6612 }
6613 /* if there were no 5I cards, then don't do any extra ordering */
6614 if (!tmp)
6615 return;
6616 for (i = position; i < ips_num_controllers; i++) {
6617 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6618 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6619 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6620 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6621 ips_shift_controllers(position, i);
6622 position++;
6623 }
6624 }
6625
6626 return;
6627}
6628
6629/****************************************************************************/
6630/* */
6631/* Routine Name: ips_register_scsi */
6632/* */
6633/* Routine Description: */
6634/* perform any registration and setup with the scsi layer */
6635/****************************************************************************/
6636static int
6637ips_register_scsi(int index)
6638{
6639 struct Scsi_Host *sh;
6640 ips_ha_t *ha, *oldha = ips_ha[index];
6641 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6642 if (!sh) {
6643 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6644 "Unable to register controller with SCSI subsystem\n");
6645 return -1;
6646 }
6647 ha = IPS_HA(sh);
6648 memcpy(ha, oldha, sizeof (ips_ha_t));
6649 free_irq(oldha->pcidev->irq, oldha);
6650 /* Install the interrupt handler with the new ha */
6651 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6652 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6653 "Unable to install interrupt handler\n");
6654 goto err_out_sh;
6655 }
6656
6657 kfree(oldha);
6658
6659 /* Store away needed values for later use */
6660 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6661 sh->sg_tablesize = sh->hostt->sg_tablesize;
6662 sh->can_queue = sh->hostt->can_queue;
6663 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6664 sh->max_sectors = 128;
6665
6666 sh->max_id = ha->ntargets;
6667 sh->max_lun = ha->nlun;
6668 sh->max_channel = ha->nbus - 1;
6669 sh->can_queue = ha->max_cmds - 1;
6670
6671 if (scsi_add_host(sh, &ha->pcidev->dev))
6672 goto err_out;
6673
6674 ips_sh[index] = sh;
6675 ips_ha[index] = ha;
6676
6677 scsi_scan_host(sh);
6678
6679 return 0;
6680
6681err_out:
6682 free_irq(ha->pcidev->irq, ha);
6683err_out_sh:
6684 scsi_host_put(sh);
6685 return -1;
6686}
6687
6688/*---------------------------------------------------------------------------*/
6689/* Routine Name: ips_remove_device */
6690/* */
6691/* Routine Description: */
6692/* Remove one Adapter ( Hot Plugging ) */
6693/*---------------------------------------------------------------------------*/
6694static void
6695ips_remove_device(struct pci_dev *pci_dev)
6696{
6697 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6698
6699 pci_set_drvdata(pci_dev, NULL);
6700
6701 ips_release(sh);
6702
6703 pci_release_regions(pci_dev);
6704 pci_disable_device(pci_dev);
6705}
6706
6707/****************************************************************************/
6708/* */
6709/* Routine Name: ips_module_init */
6710/* */
6711/* Routine Description: */
6712/* function called on module load */
6713/****************************************************************************/
6714static int __init
6715ips_module_init(void)
6716{
6717#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6718 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6719 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6720#endif
6721
6722 if (pci_register_driver(&ips_pci_driver) < 0)
6723 return -ENODEV;
6724 ips_driver_template.module = THIS_MODULE;
6725 ips_order_controllers();
6726 if (!ips_detect(&ips_driver_template)) {
6727 pci_unregister_driver(&ips_pci_driver);
6728 return -ENODEV;
6729 }
6730 register_reboot_notifier(&ips_notifier);
6731 return 0;
6732}
6733
6734/****************************************************************************/
6735/* */
6736/* Routine Name: ips_module_exit */
6737/* */
6738/* Routine Description: */
6739/* function called on module unload */
6740/****************************************************************************/
6741static void __exit
6742ips_module_exit(void)
6743{
6744 pci_unregister_driver(&ips_pci_driver);
6745 unregister_reboot_notifier(&ips_notifier);
6746}
6747
6748module_init(ips_module_init);
6749module_exit(ips_module_exit);
6750
6751/*---------------------------------------------------------------------------*/
6752/* Routine Name: ips_insert_device */
6753/* */
6754/* Routine Description: */
6755/* Add One Adapter ( Hot Plug ) */
6756/* */
6757/* Return Value: */
6758/* 0 if Successful, else non-zero */
6759/*---------------------------------------------------------------------------*/
6760static int
6761ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6762{
6763 int index = -1;
6764 int rc;
6765
6766 METHOD_TRACE("ips_insert_device", 1);
6767 rc = pci_enable_device(pci_dev);
6768 if (rc)
6769 return rc;
6770
6771 rc = pci_request_regions(pci_dev, "ips");
6772 if (rc)
6773 goto err_out;
6774
6775 rc = ips_init_phase1(pci_dev, &index);
6776 if (rc == SUCCESS)
6777 rc = ips_init_phase2(index);
6778
6779 if (ips_hotplug)
6780 if (ips_register_scsi(index)) {
6781 ips_free(ips_ha[index]);
6782 rc = -1;
6783 }
6784
6785 if (rc == SUCCESS)
6786 ips_num_controllers++;
6787
6788 ips_next_controller = ips_num_controllers;
6789
6790 if (rc < 0) {
6791 rc = -ENODEV;
6792 goto err_out_regions;
6793 }
6794
6795 pci_set_drvdata(pci_dev, ips_sh[index]);
6796 return 0;
6797
6798err_out_regions:
6799 pci_release_regions(pci_dev);
6800err_out:
6801 pci_disable_device(pci_dev);
6802 return rc;
6803}
6804
6805/*---------------------------------------------------------------------------*/
6806/* Routine Name: ips_init_phase1 */
6807/* */
6808/* Routine Description: */
6809/* Adapter Initialization */
6810/* */
6811/* Return Value: */
6812/* 0 if Successful, else non-zero */
6813/*---------------------------------------------------------------------------*/
6814static int
6815ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6816{
6817 ips_ha_t *ha;
6818 uint32_t io_addr;
6819 uint32_t mem_addr;
6820 uint32_t io_len;
6821 uint32_t mem_len;
6822 int j;
6823 int index;
6824 dma_addr_t dma_address;
6825 char __iomem *ioremap_ptr;
6826 char __iomem *mem_ptr;
6827 uint32_t IsDead;
6828
6829 METHOD_TRACE("ips_init_phase1", 1);
6830 index = IPS_MAX_ADAPTERS;
6831 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6832 if (ips_ha[j] == NULL) {
6833 index = j;
6834 break;
6835 }
6836 }
6837
6838 if (index >= IPS_MAX_ADAPTERS)
6839 return -1;
6840
6841 /* Init MEM/IO addresses to 0 */
6842 mem_addr = 0;
6843 io_addr = 0;
6844 mem_len = 0;
6845 io_len = 0;
6846
6847 for (j = 0; j < 2; j++) {
6848 if (!pci_resource_start(pci_dev, j))
6849 break;
6850
6851 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6852 io_addr = pci_resource_start(pci_dev, j);
6853 io_len = pci_resource_len(pci_dev, j);
6854 } else {
6855 mem_addr = pci_resource_start(pci_dev, j);
6856 mem_len = pci_resource_len(pci_dev, j);
6857 }
6858 }
6859
6860 /* setup memory mapped area (if applicable) */
6861 if (mem_addr) {
6862 uint32_t base;
6863 uint32_t offs;
6864
6865 base = mem_addr & PAGE_MASK;
6866 offs = mem_addr - base;
6867 ioremap_ptr = ioremap(base, PAGE_SIZE);
6868 if (!ioremap_ptr)
6869 return -1;
6870 mem_ptr = ioremap_ptr + offs;
6871 } else {
6872 ioremap_ptr = NULL;
6873 mem_ptr = NULL;
6874 }
6875
6876 /* found a controller */
6877 ha = kzalloc_obj(ips_ha_t);
6878 if (ha == NULL) {
6879 IPS_PRINTK(KERN_WARNING, pci_dev,
6880 "Unable to allocate temporary ha struct\n");
6881 return -1;
6882 }
6883
6884 ips_sh[index] = NULL;
6885 ips_ha[index] = ha;
6886 ha->active = 1;
6887
6888 /* Store info in HA structure */
6889 ha->io_addr = io_addr;
6890 ha->io_len = io_len;
6891 ha->mem_addr = mem_addr;
6892 ha->mem_len = mem_len;
6893 ha->mem_ptr = mem_ptr;
6894 ha->ioremap_ptr = ioremap_ptr;
6895 ha->host_num = (uint32_t) index;
6896 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6897 ha->pcidev = pci_dev;
6898
6899 /*
6900 * Set the pci_dev's dma_mask. Not all adapters support 64bit
6901 * addressing so don't enable it if the adapter can't support
6902 * it! Also, don't use 64bit addressing if dma addresses
6903 * are guaranteed to be < 4G.
6904 */
6905 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) &&
6906 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) {
6907 (ha)->flags |= IPS_HA_ENH_SG;
6908 } else {
6909 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) {
6910 printk(KERN_WARNING "Unable to set DMA Mask\n");
6911 return ips_abort_init(ha, index);
6912 }
6913 }
6914 if(ips_cd_boot && !ips_FlashData){
6915 ips_FlashData = dma_alloc_coherent(&pci_dev->dev,
6916 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL);
6917 }
6918
6919 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ),
6920 &ha->enq_busaddr, GFP_KERNEL);
6921 if (!ha->enq) {
6922 IPS_PRINTK(KERN_WARNING, pci_dev,
6923 "Unable to allocate host inquiry structure\n");
6924 return ips_abort_init(ha, index);
6925 }
6926
6927 ha->adapt = dma_alloc_coherent(&pci_dev->dev,
6928 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD),
6929 &dma_address, GFP_KERNEL);
6930 if (!ha->adapt) {
6931 IPS_PRINTK(KERN_WARNING, pci_dev,
6932 "Unable to allocate host adapt & dummy structures\n");
6933 return ips_abort_init(ha, index);
6934 }
6935 ha->adapt->hw_status_start = dma_address;
6936 ha->dummy = (void *) (ha->adapt + 1);
6937
6938
6939
6940 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev,
6941 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL);
6942 if (!ha->logical_drive_info) {
6943 IPS_PRINTK(KERN_WARNING, pci_dev,
6944 "Unable to allocate logical drive info structure\n");
6945 return ips_abort_init(ha, index);
6946 }
6947 ha->logical_drive_info_dma_addr = dma_address;
6948
6949
6950 ha->conf = kmalloc_obj(IPS_CONF);
6951
6952 if (!ha->conf) {
6953 IPS_PRINTK(KERN_WARNING, pci_dev,
6954 "Unable to allocate host conf structure\n");
6955 return ips_abort_init(ha, index);
6956 }
6957
6958 ha->nvram = kmalloc_obj(IPS_NVRAM_P5);
6959
6960 if (!ha->nvram) {
6961 IPS_PRINTK(KERN_WARNING, pci_dev,
6962 "Unable to allocate host NVRAM structure\n");
6963 return ips_abort_init(ha, index);
6964 }
6965
6966 ha->subsys = kmalloc_obj(IPS_SUBSYS);
6967
6968 if (!ha->subsys) {
6969 IPS_PRINTK(KERN_WARNING, pci_dev,
6970 "Unable to allocate host subsystem structure\n");
6971 return ips_abort_init(ha, index);
6972 }
6973
6974 /* the ioctl buffer is now used during adapter initialization, so its
6975 * successful allocation is now required */
6976 if (ips_ioctlsize < PAGE_SIZE)
6977 ips_ioctlsize = PAGE_SIZE;
6978
6979 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize,
6980 &ha->ioctl_busaddr, GFP_KERNEL);
6981 ha->ioctl_len = ips_ioctlsize;
6982 if (!ha->ioctl_data) {
6983 IPS_PRINTK(KERN_WARNING, pci_dev,
6984 "Unable to allocate IOCTL data\n");
6985 return ips_abort_init(ha, index);
6986 }
6987
6988 /*
6989 * Setup Functions
6990 */
6991 ips_setup_funclist(ha);
6992
6993 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
6994 /* If Morpheus appears dead, reset it */
6995 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
6996 if (IsDead == 0xDEADBEEF) {
6997 ips_reset_morpheus(ha);
6998 }
6999 }
7000
7001 /*
7002 * Initialize the card if it isn't already
7003 */
7004
7005 if (!(*ha->func.isinit) (ha)) {
7006 if (!(*ha->func.init) (ha)) {
7007 /*
7008 * Initialization failed
7009 */
7010 IPS_PRINTK(KERN_WARNING, pci_dev,
7011 "Unable to initialize controller\n");
7012 return ips_abort_init(ha, index);
7013 }
7014 }
7015
7016 *indexPtr = index;
7017 return SUCCESS;
7018}
7019
7020/*---------------------------------------------------------------------------*/
7021/* Routine Name: ips_init_phase2 */
7022/* */
7023/* Routine Description: */
7024/* Adapter Initialization Phase 2 */
7025/* */
7026/* Return Value: */
7027/* 0 if Successful, else non-zero */
7028/*---------------------------------------------------------------------------*/
7029static int
7030ips_init_phase2(int index)
7031{
7032 ips_ha_t *ha;
7033
7034 ha = ips_ha[index];
7035
7036 METHOD_TRACE("ips_init_phase2", 1);
7037 if (!ha->active) {
7038 ips_ha[index] = NULL;
7039 return -1;
7040 }
7041
7042 /* Install the interrupt handler */
7043 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7044 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7045 "Unable to install interrupt handler\n");
7046 return ips_abort_init(ha, index);
7047 }
7048
7049 /*
7050 * Allocate a temporary SCB for initialization
7051 */
7052 ha->max_cmds = 1;
7053 if (!ips_allocatescbs(ha)) {
7054 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7055 "Unable to allocate a CCB\n");
7056 free_irq(ha->pcidev->irq, ha);
7057 return ips_abort_init(ha, index);
7058 }
7059
7060 if (!ips_hainit(ha)) {
7061 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7062 "Unable to initialize controller\n");
7063 free_irq(ha->pcidev->irq, ha);
7064 return ips_abort_init(ha, index);
7065 }
7066 /* Free the temporary SCB */
7067 ips_deallocatescbs(ha, 1);
7068
7069 /* allocate CCBs */
7070 if (!ips_allocatescbs(ha)) {
7071 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7072 "Unable to allocate CCBs\n");
7073 free_irq(ha->pcidev->irq, ha);
7074 return ips_abort_init(ha, index);
7075 }
7076
7077 return SUCCESS;
7078}
7079
7080MODULE_LICENSE("GPL");
7081MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7082MODULE_VERSION(IPS_VER_STRING);