projects/linux·blob master · refs

502 lines · 11.7 KiB

1/*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay ([email protected])
12 * Copyright (C) 2003 Takashi Kusuda <[email protected]>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19#define pr_fmt(fmt) "intc: " fmt
20
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/slab.h>
25#include <linux/stat.h>
26#include <linux/interrupt.h>
27#include <linux/sh_intc.h>
28#include <linux/irqdomain.h>
29#include <linux/device.h>
30#include <linux/syscore_ops.h>
31#include <linux/list.h>
32#include <linux/spinlock.h>
33#include <linux/radix-tree.h>
34#include <linux/export.h>
35#include <linux/sort.h>
36#include "internals.h"
37
38LIST_HEAD(intc_list);
39DEFINE_RAW_SPINLOCK(intc_big_lock);
40static unsigned int nr_intc_controllers;
41
42/*
43 * Default priority level
44 * - this needs to be at least 2 for 5-bit priorities on 7780
45 */
46static unsigned int default_prio_level = 2; /* 2 - 16 */
47static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */
48
49unsigned int intc_get_dfl_prio_level(void)
50{
51 return default_prio_level;
52}
53
54unsigned int intc_get_prio_level(unsigned int irq)
55{
56 return intc_prio_level[irq];
57}
58
59void intc_set_prio_level(unsigned int irq, unsigned int level)
60{
61 unsigned long flags;
62
63 raw_spin_lock_irqsave(&intc_big_lock, flags);
64 intc_prio_level[irq] = level;
65 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
66}
67
68static void intc_redirect_irq(struct irq_desc *desc)
69{
70 generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc));
71}
72
73static void __init intc_register_irq(struct intc_desc *desc,
74 struct intc_desc_int *d,
75 intc_enum enum_id,
76 unsigned int irq)
77{
78 struct intc_handle_int *hp;
79 struct irq_data *irq_data;
80 unsigned int data[2], primary;
81 unsigned long flags;
82
83 raw_spin_lock_irqsave(&intc_big_lock, flags);
84 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
85 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
86
87 /*
88 * Prefer single interrupt source bitmap over other combinations:
89 *
90 * 1. bitmap, single interrupt source
91 * 2. priority, single interrupt source
92 * 3. bitmap, multiple interrupt sources (groups)
93 * 4. priority, multiple interrupt sources (groups)
94 */
95 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
96 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
97
98 primary = 0;
99 if (!data[0] && data[1])
100 primary = 1;
101
102 if (!data[0] && !data[1])
103 pr_warn("missing unique irq mask for irq %d (vect 0x%04x)\n",
104 irq, irq2evt(irq));
105
106 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
107 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
108
109 if (!data[primary])
110 primary ^= 1;
111
112 BUG_ON(!data[primary]); /* must have primary masking method */
113
114 irq_data = irq_get_irq_data(irq);
115
116 disable_irq_nosync(irq);
117 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
118 "level");
119 irq_set_chip_data(irq, (void *)data[primary]);
120
121 /*
122 * set priority level
123 */
124 intc_set_prio_level(irq, intc_get_dfl_prio_level());
125
126 /* enable secondary masking method if present */
127 if (data[!primary])
128 _intc_enable(irq_data, data[!primary]);
129
130 /* add irq to d->prio list if priority is available */
131 if (data[1]) {
132 hp = d->prio + d->nr_prio;
133 hp->irq = irq;
134 hp->handle = data[1];
135
136 if (primary) {
137 /*
138 * only secondary priority should access registers, so
139 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
140 */
141 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
142 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
143 }
144 d->nr_prio++;
145 }
146
147 /* add irq to d->sense list if sense is available */
148 data[0] = intc_get_sense_handle(desc, d, enum_id);
149 if (data[0]) {
150 (d->sense + d->nr_sense)->irq = irq;
151 (d->sense + d->nr_sense)->handle = data[0];
152 d->nr_sense++;
153 }
154
155 /* irq should be disabled by default */
156 d->chip.irq_mask(irq_data);
157
158 intc_set_ack_handle(irq, desc, d, enum_id);
159 intc_set_dist_handle(irq, desc, d, enum_id);
160
161 activate_irq(irq);
162}
163
164static unsigned int __init save_reg(struct intc_desc_int *d,
165 unsigned int cnt,
166 unsigned long value,
167 unsigned int smp)
168{
169 if (value) {
170 value = intc_phys_to_virt(d, value);
171
172 d->reg[cnt] = value;
173#ifdef CONFIG_SMP
174 d->smp[cnt] = smp;
175#endif
176 return 1;
177 }
178
179 return 0;
180}
181
182static bool __init intc_map(struct irq_domain *domain, int irq)
183{
184 if (!irq_to_desc(irq) && irq_alloc_desc_at(irq, NUMA_NO_NODE) != irq) {
185 pr_err("uname to allocate IRQ %d\n", irq);
186 return false;
187 }
188
189 if (irq_domain_associate(domain, irq, irq)) {
190 pr_err("domain association failure\n");
191 return false;
192 }
193
194 return true;
195}
196
197int __init register_intc_controller(struct intc_desc *desc)
198{
199 unsigned int i, k, smp;
200 struct intc_hw_desc *hw = &desc->hw;
201 struct intc_desc_int *d;
202 struct resource *res;
203
204 pr_info("Registered controller '%s' with %u IRQs\n",
205 desc->name, hw->nr_vectors);
206
207 d = kzalloc_obj(*d, GFP_NOWAIT);
208 if (!d)
209 goto err0;
210
211 INIT_LIST_HEAD(&d->list);
212
213 raw_spin_lock_init(&d->lock);
214 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
215
216 d->index = nr_intc_controllers;
217
218 if (desc->num_resources) {
219 d->nr_windows = desc->num_resources;
220 d->window = kzalloc_objs(*d->window, d->nr_windows, GFP_NOWAIT);
221 if (!d->window)
222 goto err1;
223
224 for (k = 0; k < d->nr_windows; k++) {
225 res = desc->resource + k;
226 WARN_ON(resource_type(res) != IORESOURCE_MEM);
227 d->window[k].phys = res->start;
228 d->window[k].size = resource_size(res);
229 d->window[k].virt = ioremap(res->start,
230 resource_size(res));
231 if (!d->window[k].virt)
232 goto err2;
233 }
234 }
235
236 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
237#ifdef CONFIG_INTC_BALANCING
238 if (d->nr_reg)
239 d->nr_reg += hw->nr_mask_regs;
240#endif
241 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
242 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
243 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
244 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
245
246 d->reg = kcalloc(d->nr_reg, sizeof(*d->reg), GFP_NOWAIT);
247 if (!d->reg)
248 goto err2;
249
250#ifdef CONFIG_SMP
251 d->smp = kcalloc(d->nr_reg, sizeof(*d->smp), GFP_NOWAIT);
252 if (!d->smp)
253 goto err3;
254#endif
255 k = 0;
256
257 if (hw->mask_regs) {
258 for (i = 0; i < hw->nr_mask_regs; i++) {
259 smp = IS_SMP(hw->mask_regs[i]);
260 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
261 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
262#ifdef CONFIG_INTC_BALANCING
263 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
264#endif
265 }
266 }
267
268 if (hw->prio_regs) {
269 d->prio = kzalloc_objs(*d->prio, hw->nr_vectors, GFP_NOWAIT);
270 if (!d->prio)
271 goto err4;
272
273 for (i = 0; i < hw->nr_prio_regs; i++) {
274 smp = IS_SMP(hw->prio_regs[i]);
275 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
276 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
277 }
278
279 sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
280 intc_handle_int_cmp, NULL);
281 }
282
283 if (hw->sense_regs) {
284 d->sense = kzalloc_objs(*d->sense, hw->nr_vectors, GFP_NOWAIT);
285 if (!d->sense)
286 goto err5;
287
288 for (i = 0; i < hw->nr_sense_regs; i++)
289 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
290
291 sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
292 intc_handle_int_cmp, NULL);
293 }
294
295 if (hw->subgroups)
296 for (i = 0; i < hw->nr_subgroups; i++)
297 if (hw->subgroups[i].reg)
298 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
299
300 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
301 d->chip.name = desc->name;
302
303 if (hw->ack_regs)
304 for (i = 0; i < hw->nr_ack_regs; i++)
305 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
306 else
307 d->chip.irq_mask_ack = d->chip.irq_disable;
308
309 /* disable bits matching force_disable before registering irqs */
310 if (desc->force_disable)
311 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
312
313 /* disable bits matching force_enable before registering irqs */
314 if (desc->force_enable)
315 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
316
317 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
318
319 intc_irq_domain_init(d, hw);
320
321 /* register the vectors one by one */
322 for (i = 0; i < hw->nr_vectors; i++) {
323 struct intc_vect *vect = hw->vectors + i;
324 unsigned int irq = evt2irq(vect->vect);
325
326 if (!vect->enum_id)
327 continue;
328
329 if (!intc_map(d->domain, irq))
330 continue;
331
332 intc_irq_xlate_set(irq, vect->enum_id, d);
333 intc_register_irq(desc, d, vect->enum_id, irq);
334
335 for (k = i + 1; k < hw->nr_vectors; k++) {
336 struct intc_vect *vect2 = hw->vectors + k;
337 unsigned int irq2 = evt2irq(vect2->vect);
338
339 if (vect->enum_id != vect2->enum_id)
340 continue;
341
342 /*
343 * In the case of multi-evt handling and sparse
344 * IRQ support, each vector still needs to have
345 * its own backing irq_desc.
346 */
347 if (!intc_map(d->domain, irq2))
348 continue;
349
350 vect2->enum_id = 0;
351
352 /* redirect this interrupts to the first one */
353 irq_set_chip(irq2, &dummy_irq_chip);
354 irq_set_chained_handler_and_data(irq2,
355 intc_redirect_irq,
356 (void *)irq);
357 }
358 }
359
360 intc_subgroup_init(desc, d);
361
362 /* enable bits matching force_enable after registering irqs */
363 if (desc->force_enable)
364 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
365
366 d->skip_suspend = desc->skip_syscore_suspend;
367
368 list_add_tail(&d->list, &intc_list);
369 nr_intc_controllers++;
370
371 return 0;
372err5:
373 kfree(d->prio);
374err4:
375#ifdef CONFIG_SMP
376 kfree(d->smp);
377err3:
378#endif
379 kfree(d->reg);
380err2:
381 for (k = 0; k < d->nr_windows; k++)
382 if (d->window[k].virt)
383 iounmap(d->window[k].virt);
384
385 kfree(d->window);
386err1:
387 kfree(d);
388err0:
389 pr_err("unable to allocate INTC memory\n");
390
391 return -ENOMEM;
392}
393
394static int intc_suspend(void *data)
395{
396 struct intc_desc_int *d;
397
398 list_for_each_entry(d, &intc_list, list) {
399 int irq;
400
401 if (d->skip_suspend)
402 continue;
403
404 /* enable wakeup irqs belonging to this intc controller */
405 for_each_active_irq(irq) {
406 struct irq_data *data;
407 struct irq_chip *chip;
408
409 data = irq_get_irq_data(irq);
410 chip = irq_data_get_irq_chip(data);
411 if (chip != &d->chip)
412 continue;
413 if (irqd_is_wakeup_set(data))
414 chip->irq_enable(data);
415 }
416 }
417 return 0;
418}
419
420static void intc_resume(void *data)
421{
422 struct intc_desc_int *d;
423
424 list_for_each_entry(d, &intc_list, list) {
425 int irq;
426
427 if (d->skip_suspend)
428 continue;
429
430 for_each_active_irq(irq) {
431 struct irq_data *data;
432 struct irq_chip *chip;
433
434 data = irq_get_irq_data(irq);
435 chip = irq_data_get_irq_chip(data);
436 /*
437 * This will catch the redirect and VIRQ cases
438 * due to the dummy_irq_chip being inserted.
439 */
440 if (chip != &d->chip)
441 continue;
442 if (irqd_irq_disabled(data))
443 chip->irq_disable(data);
444 else
445 chip->irq_enable(data);
446 }
447 }
448}
449
450static const struct syscore_ops intc_syscore_ops = {
451 .suspend = intc_suspend,
452 .resume = intc_resume,
453};
454
455static struct syscore intc_syscore = {
456 .ops = &intc_syscore_ops,
457};
458
459const struct bus_type intc_subsys = {
460 .name = "intc",
461 .dev_name = "intc",
462};
463
464static ssize_t
465show_intc_name(struct device *dev, struct device_attribute *attr, char *buf)
466{
467 struct intc_desc_int *d;
468
469 d = container_of(dev, struct intc_desc_int, dev);
470
471 return sprintf(buf, "%s\n", d->chip.name);
472}
473
474static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);
475
476static int __init register_intc_devs(void)
477{
478 struct intc_desc_int *d;
479 int error;
480
481 register_syscore(&intc_syscore);
482
483 error = subsys_system_register(&intc_subsys, NULL);
484 if (!error) {
485 list_for_each_entry(d, &intc_list, list) {
486 d->dev.id = d->index;
487 d->dev.bus = &intc_subsys;
488 error = device_register(&d->dev);
489 if (error == 0)
490 error = device_create_file(&d->dev,
491 &dev_attr_name);
492 if (error)
493 break;
494 }
495 }
496
497 if (error)
498 pr_err("device registration error\n");
499
500 return error;
501}
502device_initcall(register_intc_devs);