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1856 lines · 52.4 KiB

1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2019, Linaro Limited
3
4#include <linux/clk.h>
5#include <linux/completion.h>
6#include <linux/interrupt.h>
7#include <linux/io.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/debugfs.h>
11#include <linux/of.h>
12#include <linux/of_irq.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
16#include <linux/slab.h>
17#include <linux/pm_wakeirq.h>
18#include <linux/slimbus.h>
19#include <linux/soundwire/sdw.h>
20#include <linux/soundwire/sdw_registers.h>
21#include <sound/pcm_params.h>
22#include <sound/soc.h>
23#include "bus.h"
24
25#define SWRM_COMP_SW_RESET 0x008
26#define SWRM_COMP_STATUS 0x014
27#define SWRM_LINK_MANAGER_EE 0x018
28#define SWRM_EE_CPU 1
29#define SWRM_FRM_GEN_ENABLED BIT(0)
30#define SWRM_VERSION_1_3_0 0x01030000
31#define SWRM_VERSION_1_5_1 0x01050001
32#define SWRM_VERSION_1_7_0 0x01070000
33#define SWRM_VERSION_2_0_0 0x02000000
34#define SWRM_VERSION_3_1_0 0x03010000
35#define SWRM_COMP_HW_VERSION 0x00
36#define SWRM_COMP_CFG_ADDR 0x04
37#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
38#define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
39#define SWRM_COMP_PARAMS 0x100
40#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(14, 10)
41#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(19, 15)
42#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
43#define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
44#define SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH GENMASK(17, 10)
45#define SWRM_V3_COMP_PARAMS_RD_FIFO_DEPTH GENMASK(23, 18)
46
47#define SWRM_COMP_MASTER_ID 0x104
48#define SWRM_V1_3_INTERRUPT_STATUS 0x200
49#define SWRM_V2_0_INTERRUPT_STATUS 0x5000
50#define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
51#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ BIT(0)
52#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
53#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
54#define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET BIT(3)
55#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW BIT(4)
56#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW BIT(5)
57#define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW BIT(6)
58#define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
59#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION BIT(8)
60#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH BIT(9)
61#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
62#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED BIT(11)
63#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL BIT(12)
64#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2 BIT(13)
65#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2 BIT(14)
66#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP BIT(16)
67#define SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED BIT(19)
68#define SWRM_INTERRUPT_MAX 17
69#define SWRM_V1_3_INTERRUPT_MASK_ADDR 0x204
70#define SWRM_V1_3_INTERRUPT_CLEAR 0x208
71#define SWRM_V2_0_INTERRUPT_CLEAR 0x5008
72#define SWRM_V1_3_INTERRUPT_CPU_EN 0x210
73#define SWRM_V2_0_INTERRUPT_CPU_EN 0x5004
74#define SWRM_V1_3_CMD_FIFO_WR_CMD 0x300
75#define SWRM_V2_0_CMD_FIFO_WR_CMD 0x5020
76#define SWRM_V1_3_CMD_FIFO_RD_CMD 0x304
77#define SWRM_V2_0_CMD_FIFO_RD_CMD 0x5024
78#define SWRM_CMD_FIFO_CMD 0x308
79#define SWRM_CMD_FIFO_FLUSH 0x1
80#define SWRM_V1_3_CMD_FIFO_STATUS 0x30C
81#define SWRM_V2_0_CMD_FIFO_STATUS 0x5050
82#define SWRM_RD_CMD_FIFO_CNT_MASK GENMASK(20, 16)
83#define SWRM_WR_CMD_FIFO_CNT_MASK GENMASK(12, 8)
84#define SWRM_CMD_FIFO_CFG_ADDR 0x314
85#define SWRM_CONTINUE_EXEC_ON_CMD_IGNORE BIT(31)
86#define SWRM_RD_WR_CMD_RETRIES 0x7
87#define SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR 0x318
88#define SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR 0x5040
89#define SWRM_RD_FIFO_CMD_ID_MASK GENMASK(11, 8)
90#define SWRM_ENUMERATOR_CFG_ADDR 0x500
91#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (0x530 + 0x8 * (m))
92#define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (0x534 + 0x8 * (m))
93#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
94#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
95#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
96#define SWRM_MCP_BUS_CTRL 0x1044
97#define SWRM_MCP_BUS_CLK_START BIT(1)
98#define SWRM_MCP_CFG_ADDR 0x1048
99#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
100#define SWRM_DEF_CMD_NO_PINGS 0x1f
101#define SWRM_MCP_STATUS 0x104C
102#define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
103#define SWRM_MCP_SLV_STATUS 0x1090
104#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
105#define SWRM_MCP_SLV_STATUS_SZ 2
106
107#define SWRM_DPn_PORT_CTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
108#define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
109#define SWRM_DPn_BLOCK_CTRL_1(offset, n) (offset + 0x100 * (n - 1))
110#define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
111#define SWRM_DPn_PORT_HCTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
112#define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
113#define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
114
115#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
116#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
117
118#define SWRM_V2_0_CLK_CTRL 0x5060
119#define SWRM_V2_0_CLK_CTRL_CLK_START BIT(0)
120#define SWRM_V2_0_LINK_STATUS 0x5064
121
122#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
123#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
124#define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
125#define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
126#define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
127#define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
128#define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
129
130#define SWRM_REG_VAL_PACK(data, dev, id, reg) \
131 ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
132
133#define MAX_FREQ_NUM 1
134#define TIMEOUT_MS 100
135#define QCOM_SWRM_MAX_RD_LEN 0x1
136#define DEFAULT_CLK_FREQ 9600000
137#define SWR_INVALID_PARAM 0xFF
138#define SWR_HSTOP_MAX_VAL 0xF
139#define SWR_HSTART_MIN_VAL 0x0
140#define SWR_BROADCAST_CMD_ID 0x0F
141#define SWR_MAX_CMD_ID 14
142#define MAX_FIFO_RD_RETRY 3
143#define SWR_OVERFLOW_RETRY_COUNT 30
144#define SWRM_LINK_STATUS_RETRY_CNT 100
145
146enum {
147 MASTER_ID_WSA = 1,
148 MASTER_ID_RX,
149 MASTER_ID_TX
150};
151
152struct qcom_swrm_port_config {
153 u16 si;
154 u8 off1;
155 u8 off2;
156 u8 bp_mode;
157 u8 hstart;
158 u8 hstop;
159 u8 word_length;
160 u8 blk_group_count;
161 u8 lane_control;
162};
163
164/*
165 * Internal IDs for different register layouts. Only few registers differ per
166 * each variant, so the list of IDs below does not include all of registers.
167 */
168enum {
169 SWRM_REG_FRAME_GEN_ENABLED,
170 SWRM_REG_INTERRUPT_STATUS,
171 SWRM_REG_INTERRUPT_MASK_ADDR,
172 SWRM_REG_INTERRUPT_CLEAR,
173 SWRM_REG_INTERRUPT_CPU_EN,
174 SWRM_REG_CMD_FIFO_WR_CMD,
175 SWRM_REG_CMD_FIFO_RD_CMD,
176 SWRM_REG_CMD_FIFO_STATUS,
177 SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
178 SWRM_OFFSET_DP_PORT_CTRL_BANK,
179 SWRM_OFFSET_DP_PORT_CTRL_2_BANK,
180 SWRM_OFFSET_DP_BLOCK_CTRL_1,
181 SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,
182 SWRM_OFFSET_DP_PORT_HCTRL_BANK,
183 SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,
184 SWRM_OFFSET_DP_SAMPLECTRL2_BANK,
185};
186
187struct qcom_swrm_ctrl {
188 struct sdw_bus bus;
189 struct device *dev;
190 struct regmap *regmap;
191 u32 max_reg;
192 const unsigned int *reg_layout;
193 void __iomem *mmio;
194 struct reset_control *audio_cgcr;
195#ifdef CONFIG_DEBUG_FS
196 struct dentry *debugfs;
197#endif
198 struct completion broadcast;
199 struct completion enumeration;
200 /* Port alloc/free lock */
201 struct mutex port_lock;
202 struct clk *hclk;
203 int irq;
204 unsigned int version;
205 int wake_irq;
206 int num_din_ports;
207 int num_dout_ports;
208 int nports;
209 int cols_index;
210 int rows_index;
211 unsigned long port_mask;
212 u32 intr_mask;
213 u8 rcmd_id;
214 u8 wcmd_id;
215 /* Port numbers are 1 - 14 */
216 struct qcom_swrm_port_config *pconfig;
217 struct sdw_stream_runtime **sruntime;
218 enum sdw_slave_status status[SDW_MAX_DEVICES + 1];
219 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
220 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
221 u32 slave_status;
222 u32 wr_fifo_depth;
223 bool clock_stop_not_supported;
224};
225
226struct qcom_swrm_data {
227 u32 default_cols;
228 u32 default_rows;
229 bool sw_clk_gate_required;
230 u32 max_reg;
231 const unsigned int *reg_layout;
232};
233
234static const unsigned int swrm_v1_3_reg_layout[] = {
235 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_COMP_STATUS,
236 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V1_3_INTERRUPT_STATUS,
237 [SWRM_REG_INTERRUPT_MASK_ADDR] = SWRM_V1_3_INTERRUPT_MASK_ADDR,
238 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V1_3_INTERRUPT_CLEAR,
239 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V1_3_INTERRUPT_CPU_EN,
240 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V1_3_CMD_FIFO_WR_CMD,
241 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
242 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
243 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
244 [SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
245 [SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
246 [SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
247 [SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
248 [SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
249 [SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
250 [SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
251};
252
253static const struct qcom_swrm_data swrm_v1_3_data = {
254 .default_rows = 48,
255 .default_cols = 16,
256 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
257 .reg_layout = swrm_v1_3_reg_layout,
258};
259
260static const struct qcom_swrm_data swrm_v1_5_data = {
261 .default_rows = 50,
262 .default_cols = 16,
263 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
264 .reg_layout = swrm_v1_3_reg_layout,
265};
266
267static const struct qcom_swrm_data swrm_v1_6_data = {
268 .default_rows = 50,
269 .default_cols = 16,
270 .sw_clk_gate_required = true,
271 .max_reg = SWR_V1_3_MSTR_MAX_REG_ADDR,
272 .reg_layout = swrm_v1_3_reg_layout,
273};
274
275static const unsigned int swrm_v2_0_reg_layout[] = {
276 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
277 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
278 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
279 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
280 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
281 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
282 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
283 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
284 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
285 [SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
286 [SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
287 [SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
288 [SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
289 [SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
290 [SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
291 [SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
292};
293
294static const struct qcom_swrm_data swrm_v2_0_data = {
295 .default_rows = 50,
296 .default_cols = 16,
297 .sw_clk_gate_required = true,
298 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
299 .reg_layout = swrm_v2_0_reg_layout,
300};
301
302static const unsigned int swrm_v3_0_reg_layout[] = {
303 [SWRM_REG_FRAME_GEN_ENABLED] = SWRM_V2_0_LINK_STATUS,
304 [SWRM_REG_INTERRUPT_STATUS] = SWRM_V2_0_INTERRUPT_STATUS,
305 [SWRM_REG_INTERRUPT_MASK_ADDR] = 0, /* Not present */
306 [SWRM_REG_INTERRUPT_CLEAR] = SWRM_V2_0_INTERRUPT_CLEAR,
307 [SWRM_REG_INTERRUPT_CPU_EN] = SWRM_V2_0_INTERRUPT_CPU_EN,
308 [SWRM_REG_CMD_FIFO_WR_CMD] = SWRM_V2_0_CMD_FIFO_WR_CMD,
309 [SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
310 [SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
311 [SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
312 [SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1224,
313 [SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1228,
314 [SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x122c,
315 [SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1230,
316 [SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1234,
317 [SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1238,
318 [SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x123c,
319};
320
321static const struct qcom_swrm_data swrm_v3_0_data = {
322 .default_rows = 50,
323 .default_cols = 16,
324 .sw_clk_gate_required = true,
325 .max_reg = SWR_V2_0_MSTR_MAX_REG_ADDR,
326 .reg_layout = swrm_v3_0_reg_layout,
327};
328#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
329
330static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
331 u32 *val)
332{
333 struct regmap *wcd_regmap = ctrl->regmap;
334 int ret;
335
336 /* pg register + offset */
337 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
338 (u8 *)&reg, 4);
339 if (ret < 0)
340 return SDW_CMD_FAIL;
341
342 ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
343 val, 4);
344 if (ret < 0)
345 return SDW_CMD_FAIL;
346
347 return SDW_CMD_OK;
348}
349
350static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
351 int reg, int val)
352{
353 struct regmap *wcd_regmap = ctrl->regmap;
354 int ret;
355 /* pg register + offset */
356 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
357 (u8 *)&val, 4);
358 if (ret)
359 return SDW_CMD_FAIL;
360
361 /* write address register */
362 ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
363 (u8 *)&reg, 4);
364 if (ret)
365 return SDW_CMD_FAIL;
366
367 return SDW_CMD_OK;
368}
369
370static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
371 u32 *val)
372{
373 *val = readl(ctrl->mmio + reg);
374 return SDW_CMD_OK;
375}
376
377static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
378 int val)
379{
380 writel(val, ctrl->mmio + reg);
381 return SDW_CMD_OK;
382}
383
384static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
385 u8 dev_addr, u16 reg_addr)
386{
387 u32 val;
388 u8 id = *cmd_id;
389
390 if (id != SWR_BROADCAST_CMD_ID) {
391 if (id < SWR_MAX_CMD_ID)
392 id += 1;
393 else
394 id = 0;
395 *cmd_id = id;
396 }
397 val = SWRM_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
398
399 return val;
400}
401
402static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
403{
404 u32 fifo_outstanding_data, value;
405 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
406
407 do {
408 /* Check for fifo underflow during read */
409 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
410 &value);
411 fifo_outstanding_data = FIELD_GET(SWRM_RD_CMD_FIFO_CNT_MASK, value);
412
413 /* Check if read data is available in read fifo */
414 if (fifo_outstanding_data > 0)
415 return 0;
416
417 usleep_range(500, 510);
418 } while (fifo_retry_count--);
419
420 if (fifo_outstanding_data == 0) {
421 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
422 return -EIO;
423 }
424
425 return 0;
426}
427
428static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
429{
430 u32 fifo_outstanding_cmds, value;
431 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
432
433 do {
434 /* Check for fifo overflow during write */
435 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
436 &value);
437 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
438
439 /* Check for space in write fifo before writing */
440 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
441 return 0;
442
443 usleep_range(500, 510);
444 } while (fifo_retry_count--);
445
446 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
447 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
448 return -EIO;
449 }
450
451 return 0;
452}
453
454static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
455{
456 u32 fifo_outstanding_cmds, value;
457 int fifo_retry_count = SWR_OVERFLOW_RETRY_COUNT;
458
459 /* Check for fifo overflow during write */
460 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
461 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
462
463 if (fifo_outstanding_cmds) {
464 while (fifo_retry_count) {
465 usleep_range(500, 510);
466 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
467 fifo_outstanding_cmds = FIELD_GET(SWRM_WR_CMD_FIFO_CNT_MASK, value);
468 fifo_retry_count--;
469 if (fifo_outstanding_cmds == 0)
470 return true;
471 }
472 } else {
473 return true;
474 }
475
476
477 return false;
478}
479
480static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
481 u8 dev_addr, u16 reg_addr)
482{
483
484 u32 val;
485 int ret = 0;
486 u8 cmd_id = 0x0;
487
488 if (dev_addr == SDW_BROADCAST_DEV_NUM) {
489 cmd_id = SWR_BROADCAST_CMD_ID;
490 val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
491 dev_addr, reg_addr);
492 } else {
493 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
494 dev_addr, reg_addr);
495 }
496
497 if (swrm_wait_for_wr_fifo_avail(ctrl))
498 return SDW_CMD_FAIL_OTHER;
499
500 if (cmd_id == SWR_BROADCAST_CMD_ID)
501 reinit_completion(&ctrl->broadcast);
502
503 /* Its assumed that write is okay as we do not get any status back */
504 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
505
506 if (ctrl->version <= SWRM_VERSION_1_3_0)
507 usleep_range(150, 155);
508
509 if (cmd_id == SWR_BROADCAST_CMD_ID) {
510 swrm_wait_for_wr_fifo_done(ctrl);
511 /*
512 * sleep for 10ms for MSM soundwire variant to allow broadcast
513 * command to complete.
514 */
515 ret = wait_for_completion_timeout(&ctrl->broadcast,
516 msecs_to_jiffies(TIMEOUT_MS));
517 if (!ret)
518 ret = SDW_CMD_IGNORED;
519 else
520 ret = SDW_CMD_OK;
521
522 } else {
523 ret = SDW_CMD_OK;
524 }
525 return ret;
526}
527
528static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
529 u8 dev_addr, u16 reg_addr,
530 u32 len, u8 *rval)
531{
532 u32 cmd_data, cmd_id, val, retry_attempt = 0;
533
534 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
535
536 /*
537 * Check for outstanding cmd wrt. write fifo depth to avoid
538 * overflow as read will also increase write fifo cnt.
539 */
540 swrm_wait_for_wr_fifo_avail(ctrl);
541
542 /* wait for FIFO RD to complete to avoid overflow */
543 usleep_range(100, 105);
544 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
545 /* wait for FIFO RD CMD complete to avoid overflow */
546 usleep_range(250, 255);
547
548 if (swrm_wait_for_rd_fifo_avail(ctrl))
549 return SDW_CMD_FAIL_OTHER;
550
551 do {
552 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
553 &cmd_data);
554 rval[0] = cmd_data & 0xFF;
555 cmd_id = FIELD_GET(SWRM_RD_FIFO_CMD_ID_MASK, cmd_data);
556
557 if (cmd_id != ctrl->rcmd_id) {
558 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) {
559 /* wait 500 us before retry on fifo read failure */
560 usleep_range(500, 505);
561 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
562 SWRM_CMD_FIFO_FLUSH);
563 ctrl->reg_write(ctrl,
564 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
565 val);
566 }
567 retry_attempt++;
568 } else {
569 return SDW_CMD_OK;
570 }
571
572 } while (retry_attempt < MAX_FIFO_RD_RETRY);
573
574 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
575 dev_num: 0x%x, cmd_data: 0x%x\n",
576 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
577
578 return SDW_CMD_IGNORED;
579}
580
581static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
582{
583 u32 val, status;
584 int dev_num;
585
586 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
587
588 for (dev_num = 1; dev_num <= SDW_MAX_DEVICES; dev_num++) {
589 status = (val >> (dev_num * SWRM_MCP_SLV_STATUS_SZ));
590
591 if ((status & SWRM_MCP_SLV_STATUS_MASK) == SDW_SLAVE_ALERT) {
592 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
593 return dev_num;
594 }
595 }
596
597 return -EINVAL;
598}
599
600static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
601{
602 u32 val;
603 int i;
604
605 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
606 ctrl->slave_status = val;
607
608 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
609 u32 s;
610
611 s = (val >> (i * 2));
612 s &= SWRM_MCP_SLV_STATUS_MASK;
613 ctrl->status[i] = s;
614 }
615}
616
617static void qcom_swrm_set_slave_dev_num(struct sdw_bus *bus,
618 struct sdw_slave *slave, int devnum)
619{
620 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
621 u32 status;
622
623 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
624 status = (status >> (devnum * SWRM_MCP_SLV_STATUS_SZ));
625 status &= SWRM_MCP_SLV_STATUS_MASK;
626
627 if (status == SDW_SLAVE_ATTACHED) {
628 if (slave)
629 slave->dev_num = devnum;
630 mutex_lock(&bus->bus_lock);
631 set_bit(devnum, bus->assigned);
632 mutex_unlock(&bus->bus_lock);
633 }
634}
635
636static int qcom_swrm_enumerate(struct sdw_bus *bus)
637{
638 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
639 struct sdw_slave *slave, *_s;
640 struct sdw_slave_id id;
641 u32 val1, val2;
642 bool found;
643 u64 addr;
644 int i;
645 char *buf1 = (char *)&val1, *buf2 = (char *)&val2;
646
647 for (i = 1; i <= SDW_MAX_DEVICES; i++) {
648 /* do not continue if the status is Not Present */
649 if (!ctrl->status[i])
650 continue;
651
652 /*SCP_Devid5 - Devid 4*/
653 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
654
655 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/
656 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
657
658 if (!val1 && !val2)
659 break;
660
661 addr = buf2[1] | (buf2[0] << 8) | (buf1[3] << 16) |
662 ((u64)buf1[2] << 24) | ((u64)buf1[1] << 32) |
663 ((u64)buf1[0] << 40);
664
665 sdw_extract_slave_id(bus, addr, &id);
666 found = false;
667 ctrl->clock_stop_not_supported = false;
668 /* Now compare with entries */
669 list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
670 if (sdw_compare_devid(slave, id) == 0) {
671 qcom_swrm_set_slave_dev_num(bus, slave, i);
672 if (slave->prop.clk_stop_mode1)
673 ctrl->clock_stop_not_supported = true;
674
675 found = true;
676 break;
677 }
678 }
679
680 if (!found) {
681 qcom_swrm_set_slave_dev_num(bus, NULL, i);
682 sdw_slave_add(bus, &id, NULL);
683 }
684 }
685
686 complete(&ctrl->enumeration);
687 return 0;
688}
689
690static irqreturn_t qcom_swrm_wake_irq_handler(int irq, void *dev_id)
691{
692 struct qcom_swrm_ctrl *ctrl = dev_id;
693 int ret;
694
695 ret = pm_runtime_get_sync(ctrl->dev);
696 if (ret < 0 && ret != -EACCES) {
697 dev_err_ratelimited(ctrl->dev,
698 "pm_runtime_get_sync failed in %s, ret %d\n",
699 __func__, ret);
700 pm_runtime_put_noidle(ctrl->dev);
701 return ret;
702 }
703
704 if (ctrl->wake_irq > 0) {
705 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
706 disable_irq_nosync(ctrl->wake_irq);
707 }
708
709 pm_runtime_mark_last_busy(ctrl->dev);
710 pm_runtime_put_autosuspend(ctrl->dev);
711
712 return IRQ_HANDLED;
713}
714
715static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
716{
717 struct qcom_swrm_ctrl *ctrl = dev_id;
718 u32 value, intr_sts, intr_sts_masked, slave_status;
719 u32 i;
720 int devnum;
721 int ret = IRQ_HANDLED;
722 clk_prepare_enable(ctrl->hclk);
723
724 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
725 &intr_sts);
726 intr_sts_masked = intr_sts & ctrl->intr_mask;
727
728 do {
729 for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
730 value = intr_sts_masked & BIT(i);
731 if (!value)
732 continue;
733
734 switch (value) {
735 case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
736 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
737 if (devnum < 0) {
738 dev_err_ratelimited(ctrl->dev,
739 "no slave alert found.spurious interrupt\n");
740 } else {
741 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
742 }
743
744 break;
745 case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
746 case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
747 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
748 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
749 if (ctrl->slave_status == slave_status) {
750 dev_dbg(ctrl->dev, "Slave status not changed %x\n",
751 slave_status);
752 } else {
753 qcom_swrm_get_device_status(ctrl);
754 qcom_swrm_enumerate(&ctrl->bus);
755 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
756 }
757 break;
758 case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
759 dev_err_ratelimited(ctrl->dev,
760 "%s: SWR bus clsh detected\n",
761 __func__);
762 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
763 ctrl->reg_write(ctrl,
764 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
765 ctrl->intr_mask);
766 break;
767 case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
768 ctrl->reg_read(ctrl,
769 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
770 &value);
771 dev_err_ratelimited(ctrl->dev,
772 "%s: SWR read FIFO overflow fifo status 0x%x\n",
773 __func__, value);
774 break;
775 case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
776 ctrl->reg_read(ctrl,
777 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
778 &value);
779 dev_err_ratelimited(ctrl->dev,
780 "%s: SWR read FIFO underflow fifo status 0x%x\n",
781 __func__, value);
782 break;
783 case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
784 ctrl->reg_read(ctrl,
785 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
786 &value);
787 dev_err(ctrl->dev,
788 "%s: SWR write FIFO overflow fifo status %x\n",
789 __func__, value);
790 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
791 break;
792 case SWRM_INTERRUPT_STATUS_CMD_ERROR:
793 ctrl->reg_read(ctrl,
794 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
795 &value);
796 dev_err_ratelimited(ctrl->dev,
797 "%s: SWR CMD error, fifo status 0x%x, flushing fifo\n",
798 __func__, value);
799 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
800 break;
801 case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
802 dev_err_ratelimited(ctrl->dev,
803 "%s: SWR Port collision detected\n",
804 __func__);
805 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
806 ctrl->reg_write(ctrl,
807 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
808 ctrl->intr_mask);
809 break;
810 case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
811 dev_err_ratelimited(ctrl->dev,
812 "%s: SWR read enable valid mismatch\n",
813 __func__);
814 ctrl->intr_mask &=
815 ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
816 ctrl->reg_write(ctrl,
817 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
818 ctrl->intr_mask);
819 break;
820 case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
821 complete(&ctrl->broadcast);
822 break;
823 case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED_V2:
824 break;
825 case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2:
826 break;
827 case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP:
828 break;
829 case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
830 ctrl->reg_read(ctrl,
831 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
832 &value);
833 dev_err(ctrl->dev,
834 "%s: SWR CMD ignored, fifo status %x\n",
835 __func__, value);
836
837 /* Wait 3.5ms to clear */
838 usleep_range(3500, 3505);
839 break;
840 default:
841 dev_err_ratelimited(ctrl->dev,
842 "%s: SWR unknown interrupt value: %d\n",
843 __func__, value);
844 ret = IRQ_NONE;
845 break;
846 }
847 }
848 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
849 intr_sts);
850 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
851 &intr_sts);
852 intr_sts_masked = intr_sts & ctrl->intr_mask;
853 } while (intr_sts_masked);
854
855 clk_disable_unprepare(ctrl->hclk);
856 return ret;
857}
858
859static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
860{
861 int retry = SWRM_LINK_STATUS_RETRY_CNT;
862 int comp_sts;
863
864 do {
865 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED],
866 &comp_sts);
867 if (comp_sts & SWRM_FRM_GEN_ENABLED)
868 return true;
869
870 usleep_range(500, 510);
871 } while (retry--);
872
873 dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
874 comp_sts & SWRM_FRM_GEN_ENABLED ? "connected" : "disconnected");
875
876 return false;
877}
878
879static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
880{
881 u32 val;
882
883 /* Clear Rows and Cols */
884 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
885 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
886
887 reset_control_reset(ctrl->audio_cgcr);
888
889 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
890
891 /* Enable Auto enumeration */
892 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
893
894 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
895 /* Mask soundwire interrupts */
896 if (ctrl->version < SWRM_VERSION_2_0_0)
897 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
898 SWRM_INTERRUPT_STATUS_RMSK);
899
900 /* Configure No pings */
901 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
902 u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
903 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
904
905 if (ctrl->version == SWRM_VERSION_1_7_0) {
906 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
907 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
908 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
909 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
910 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
911 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
912 SWRM_V2_0_CLK_CTRL_CLK_START);
913 } else {
914 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
915 }
916
917 /* Configure number of retries of a read/write cmd */
918 if (ctrl->version >= SWRM_VERSION_1_5_1) {
919 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
920 SWRM_RD_WR_CMD_RETRIES |
921 SWRM_CONTINUE_EXEC_ON_CMD_IGNORE);
922 } else {
923 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
924 SWRM_RD_WR_CMD_RETRIES);
925 }
926
927 /* COMP Enable */
928 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
929
930 /* Set IRQ to PULSE */
931 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
932 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK);
933
934 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
935 0xFFFFFFFF);
936
937 /* enable CPU IRQs */
938 if (ctrl->mmio) {
939 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
940 SWRM_INTERRUPT_STATUS_RMSK);
941 }
942
943 /* Set IRQ to PULSE */
944 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
945 SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
946 SWRM_COMP_CFG_ENABLE_MSK);
947
948 swrm_wait_for_frame_gen_enabled(ctrl);
949 ctrl->slave_status = 0;
950 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
951
952 if (ctrl->version >= SWRM_VERSION_3_1_0)
953 ctrl->wr_fifo_depth = FIELD_GET(SWRM_V3_COMP_PARAMS_WR_FIFO_DEPTH, val);
954 else
955 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
956
957 return 0;
958}
959
960static int qcom_swrm_read_prop(struct sdw_bus *bus)
961{
962 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
963
964 if (ctrl->version >= SWRM_VERSION_2_0_0) {
965 bus->multi_link = true;
966 bus->hw_sync_min_links = 3;
967 }
968
969 return 0;
970}
971
972static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
973 struct sdw_msg *msg)
974{
975 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
976 int ret, i, len;
977
978 if (msg->page) {
979 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->addr_page1,
980 msg->dev_num,
981 SDW_SCP_ADDRPAGE1);
982 if (ret)
983 return ret;
984
985 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->addr_page2,
986 msg->dev_num,
987 SDW_SCP_ADDRPAGE2);
988 if (ret)
989 return ret;
990 }
991
992 if (msg->flags == SDW_MSG_FLAG_READ) {
993 for (i = 0; i < msg->len;) {
994 len = min(msg->len - i, QCOM_SWRM_MAX_RD_LEN);
995
996 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
997 msg->addr + i, len,
998 &msg->buf[i]);
999 if (ret)
1000 return ret;
1001
1002 i = i + len;
1003 }
1004 } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
1005 for (i = 0; i < msg->len; i++) {
1006 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
1007 msg->dev_num,
1008 msg->addr + i);
1009 if (ret)
1010 return SDW_CMD_IGNORED;
1011 }
1012 }
1013
1014 return SDW_CMD_OK;
1015}
1016
1017static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
1018{
1019 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
1020 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1021 u32 val;
1022
1023 ctrl->reg_read(ctrl, reg, &val);
1024
1025 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
1026 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
1027
1028 return ctrl->reg_write(ctrl, reg, val);
1029}
1030
1031static int qcom_swrm_port_params(struct sdw_bus *bus,
1032 struct sdw_port_params *p_params,
1033 unsigned int bank)
1034{
1035 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1036 u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];
1037
1038 return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num),
1039 p_params->bps - 1);
1040}
1041
1042static int qcom_swrm_transport_params(struct sdw_bus *bus,
1043 struct sdw_transport_params *params,
1044 enum sdw_reg_bank bank)
1045{
1046 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1047 struct qcom_swrm_port_config *pcfg;
1048 u32 value;
1049 int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1050 int ret;
1051
1052 reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);
1053
1054 pcfg = &ctrl->pconfig[params->port_num];
1055
1056 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
1057 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
1058 value |= pcfg->si & 0xff;
1059
1060 ret = ctrl->reg_write(ctrl, reg, value);
1061 if (ret)
1062 goto err;
1063
1064 if (pcfg->si > 0xff) {
1065 offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];
1066 value = (pcfg->si >> 8) & 0xff;
1067 reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);
1068
1069 ret = ctrl->reg_write(ctrl, reg, value);
1070 if (ret)
1071 goto err;
1072 }
1073
1074 if (pcfg->lane_control != SWR_INVALID_PARAM) {
1075 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];
1076 reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);
1077
1078 value = pcfg->lane_control;
1079 ret = ctrl->reg_write(ctrl, reg, value);
1080 if (ret)
1081 goto err;
1082 }
1083
1084 if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1085 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];
1086
1087 reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);
1088
1089 value = pcfg->blk_group_count;
1090 ret = ctrl->reg_write(ctrl, reg, value);
1091 if (ret)
1092 goto err;
1093 }
1094
1095 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];
1096 reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);
1097
1098 if (pcfg->hstart != SWR_INVALID_PARAM && pcfg->hstop != SWR_INVALID_PARAM) {
1099 value = (pcfg->hstop << 4) | pcfg->hstart;
1100 ret = ctrl->reg_write(ctrl, reg, value);
1101 } else {
1102 value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1103 ret = ctrl->reg_write(ctrl, reg, value);
1104 }
1105
1106 if (ret)
1107 goto err;
1108
1109 if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1110 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];
1111 reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);
1112 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1113 }
1114
1115err:
1116 return ret;
1117}
1118
1119static int qcom_swrm_port_enable(struct sdw_bus *bus,
1120 struct sdw_enable_ch *enable_ch,
1121 unsigned int bank)
1122{
1123 u32 reg;
1124 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1125 u32 val;
1126 u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1127
1128 reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);
1129
1130 ctrl->reg_read(ctrl, reg, &val);
1131
1132 if (enable_ch->enable)
1133 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1134 else
1135 val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
1136
1137 return ctrl->reg_write(ctrl, reg, val);
1138}
1139
1140static const struct sdw_master_port_ops qcom_swrm_port_ops = {
1141 .dpn_set_port_params = qcom_swrm_port_params,
1142 .dpn_set_port_transport_params = qcom_swrm_transport_params,
1143 .dpn_port_enable_ch = qcom_swrm_port_enable,
1144};
1145
1146static const struct sdw_master_ops qcom_swrm_ops = {
1147 .read_prop = qcom_swrm_read_prop,
1148 .xfer_msg = qcom_swrm_xfer_msg,
1149 .pre_bank_switch = qcom_swrm_pre_bank_switch,
1150};
1151
1152static int qcom_swrm_compute_params(struct sdw_bus *bus, struct sdw_stream_runtime *stream)
1153{
1154 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1155 struct sdw_master_runtime *m_rt;
1156 struct sdw_slave_runtime *s_rt;
1157 struct sdw_port_runtime *p_rt;
1158 struct qcom_swrm_port_config *pcfg;
1159 struct sdw_slave *slave;
1160 unsigned int m_port;
1161 int i = 1;
1162
1163 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
1164 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
1165 pcfg = &ctrl->pconfig[p_rt->num];
1166 p_rt->transport_params.port_num = p_rt->num;
1167 if (pcfg->word_length != SWR_INVALID_PARAM) {
1168 sdw_fill_port_params(&p_rt->port_params,
1169 p_rt->num, pcfg->word_length + 1,
1170 SDW_PORT_FLOW_MODE_ISOCH,
1171 SDW_PORT_DATA_MODE_NORMAL);
1172 }
1173
1174 }
1175
1176 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1177 slave = s_rt->slave;
1178 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1179 m_port = slave->m_port_map[p_rt->num];
1180 /* port config starts at offset 0 so -1 from actual port number */
1181 if (m_port)
1182 pcfg = &ctrl->pconfig[m_port];
1183 else
1184 pcfg = &ctrl->pconfig[i];
1185 p_rt->transport_params.port_num = p_rt->num;
1186 p_rt->transport_params.sample_interval =
1187 pcfg->si + 1;
1188 p_rt->transport_params.offset1 = pcfg->off1;
1189 p_rt->transport_params.offset2 = pcfg->off2;
1190 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
1191 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count;
1192
1193 p_rt->transport_params.hstart = pcfg->hstart;
1194 p_rt->transport_params.hstop = pcfg->hstop;
1195 p_rt->transport_params.lane_ctrl = pcfg->lane_control;
1196 if (pcfg->word_length != SWR_INVALID_PARAM) {
1197 sdw_fill_port_params(&p_rt->port_params,
1198 p_rt->num,
1199 pcfg->word_length + 1,
1200 SDW_PORT_FLOW_MODE_ISOCH,
1201 SDW_PORT_DATA_MODE_NORMAL);
1202 }
1203 i++;
1204 }
1205 }
1206 }
1207
1208 return 0;
1209}
1210
1211static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
1212 DEFAULT_CLK_FREQ,
1213};
1214
1215static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1216 struct sdw_stream_runtime *stream)
1217{
1218 struct sdw_master_runtime *m_rt;
1219 struct sdw_port_runtime *p_rt;
1220 unsigned long *port_mask;
1221
1222 mutex_lock(&ctrl->port_lock);
1223
1224 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1225 port_mask = &ctrl->port_mask;
1226 list_for_each_entry(p_rt, &m_rt->port_list, port_node)
1227 clear_bit(p_rt->num, port_mask);
1228 }
1229
1230 mutex_unlock(&ctrl->port_lock);
1231}
1232
1233static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1234 struct sdw_stream_runtime *stream,
1235 struct snd_pcm_hw_params *params,
1236 int direction)
1237{
1238 struct sdw_stream_config sconfig;
1239 struct sdw_master_runtime *m_rt;
1240 struct sdw_slave_runtime *s_rt;
1241 struct sdw_port_runtime *p_rt;
1242 struct sdw_slave *slave;
1243 unsigned long *port_mask;
1244 int maxport, pn, nports = 0;
1245 unsigned int m_port;
1246 struct sdw_port_config *pconfig __free(kfree) = kzalloc_objs(*pconfig,
1247 ctrl->nports);
1248 if (!pconfig)
1249 return -ENOMEM;
1250
1251 if (direction == SNDRV_PCM_STREAM_CAPTURE)
1252 sconfig.direction = SDW_DATA_DIR_TX;
1253 else
1254 sconfig.direction = SDW_DATA_DIR_RX;
1255
1256 /* hw parameters will be ignored as we only support PDM */
1257 sconfig.ch_count = 1;
1258 sconfig.frame_rate = params_rate(params);
1259 sconfig.type = stream->type;
1260 sconfig.bps = 1;
1261
1262 guard(mutex)(&ctrl->port_lock);
1263
1264 list_for_each_entry(m_rt, &stream->master_list, stream_node) {
1265 /*
1266 * For streams with multiple masters:
1267 * Allocate ports only for devices connected to this master.
1268 * Such devices will have ports allocated by their own master
1269 * and its qcom_swrm_stream_alloc_ports() call.
1270 */
1271 if (ctrl->bus.id != m_rt->bus->id)
1272 continue;
1273
1274 port_mask = &ctrl->port_mask;
1275 maxport = ctrl->nports;
1276
1277 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
1278 slave = s_rt->slave;
1279 list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
1280 m_port = slave->m_port_map[p_rt->num];
1281 /* Port numbers start from 1 - 14*/
1282 if (m_port)
1283 pn = m_port;
1284 else
1285 pn = find_first_zero_bit(port_mask, maxport);
1286
1287 if (pn >= maxport) {
1288 dev_err(ctrl->dev, "All ports busy\n");
1289 return -EBUSY;
1290 }
1291 set_bit(pn, port_mask);
1292 pconfig[nports].num = pn;
1293 pconfig[nports].ch_mask = p_rt->ch_mask;
1294 nports++;
1295 }
1296 }
1297 }
1298
1299 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1300 nports, stream);
1301
1302 return 0;
1303}
1304
1305static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
1306 struct snd_pcm_hw_params *params,
1307 struct snd_soc_dai *dai)
1308{
1309 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1310 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1311 int ret;
1312
1313 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1314 substream->stream);
1315 if (ret)
1316 qcom_swrm_stream_free_ports(ctrl, sruntime);
1317
1318 return ret;
1319}
1320
1321static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
1322 struct snd_soc_dai *dai)
1323{
1324 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1325 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1326
1327 qcom_swrm_stream_free_ports(ctrl, sruntime);
1328 sdw_stream_remove_master(&ctrl->bus, sruntime);
1329
1330 return 0;
1331}
1332
1333static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
1334 void *stream, int direction)
1335{
1336 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1337
1338 ctrl->sruntime[dai->id] = stream;
1339
1340 return 0;
1341}
1342
1343static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
1344{
1345 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1346
1347 return ctrl->sruntime[dai->id];
1348}
1349
1350static int qcom_swrm_startup(struct snd_pcm_substream *substream,
1351 struct snd_soc_dai *dai)
1352{
1353 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1354 int ret;
1355
1356 ret = pm_runtime_get_sync(ctrl->dev);
1357 if (ret < 0 && ret != -EACCES) {
1358 dev_err_ratelimited(ctrl->dev,
1359 "pm_runtime_get_sync failed in %s, ret %d\n",
1360 __func__, ret);
1361 pm_runtime_put_noidle(ctrl->dev);
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
1369 struct snd_soc_dai *dai)
1370{
1371 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1372
1373 swrm_wait_for_wr_fifo_done(ctrl);
1374 pm_runtime_mark_last_busy(ctrl->dev);
1375 pm_runtime_put_autosuspend(ctrl->dev);
1376
1377}
1378
1379static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
1380 .hw_params = qcom_swrm_hw_params,
1381 .hw_free = qcom_swrm_hw_free,
1382 .startup = qcom_swrm_startup,
1383 .shutdown = qcom_swrm_shutdown,
1384 .set_stream = qcom_swrm_set_sdw_stream,
1385 .get_stream = qcom_swrm_get_sdw_stream,
1386};
1387
1388static const struct snd_soc_component_driver qcom_swrm_dai_component = {
1389 .name = "soundwire",
1390};
1391
1392static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1393{
1394 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1395 struct snd_soc_dai_driver *dais;
1396 struct snd_soc_pcm_stream *stream;
1397 struct device *dev = ctrl->dev;
1398 int i;
1399
1400 ctrl->sruntime = devm_kcalloc(dev, num_dais, sizeof(*ctrl->sruntime), GFP_KERNEL);
1401 if (!ctrl->sruntime)
1402 return -ENOMEM;
1403
1404 /* PDM dais are only tested for now */
1405 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
1406 if (!dais)
1407 return -ENOMEM;
1408
1409 for (i = 0; i < num_dais; i++) {
1410 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
1411 if (!dais[i].name)
1412 return -ENOMEM;
1413
1414 if (i < ctrl->num_dout_ports)
1415 stream = &dais[i].playback;
1416 else
1417 stream = &dais[i].capture;
1418
1419 stream->channels_min = 1;
1420 stream->channels_max = 1;
1421 stream->rates = SNDRV_PCM_RATE_48000;
1422 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
1423
1424 dais[i].ops = &qcom_swrm_pdm_dai_ops;
1425 dais[i].id = i;
1426 }
1427
1428 return devm_snd_soc_register_component(ctrl->dev,
1429 &qcom_swrm_dai_component,
1430 dais, num_dais);
1431}
1432
1433static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1434{
1435 struct device_node *np = ctrl->dev->of_node;
1436 struct qcom_swrm_port_config *pcfg;
1437 int i, ret, val;
1438
1439 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1440
1441 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1442 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1443
1444 ret = of_property_read_u32(np, "qcom,din-ports", &val);
1445 if (!ret) { /* only if present */
1446 if (val != ctrl->num_din_ports) {
1447 dev_err(ctrl->dev, "din-ports (%d) mismatch with controller (%d)",
1448 val, ctrl->num_din_ports);
1449 }
1450
1451 ctrl->num_din_ports = val;
1452 }
1453
1454 ret = of_property_read_u32(np, "qcom,dout-ports", &val);
1455 if (!ret) { /* only if present */
1456 if (val != ctrl->num_dout_ports) {
1457 dev_err(ctrl->dev, "dout-ports (%d) mismatch with controller (%d)",
1458 val, ctrl->num_dout_ports);
1459 }
1460
1461 ctrl->num_dout_ports = val;
1462 }
1463
1464 ctrl->nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1465
1466 ctrl->pconfig = devm_kcalloc(ctrl->dev, ctrl->nports + 1,
1467 sizeof(*ctrl->pconfig), GFP_KERNEL);
1468 if (!ctrl->pconfig)
1469 return -ENOMEM;
1470
1471 set_bit(0, &ctrl->port_mask);
1472 /* Valid port numbers are from 1, so mask out port 0 explicitly */
1473 for (i = 0; i < ctrl->nports; i++) {
1474 pcfg = &ctrl->pconfig[i + 1];
1475
1476 ret = of_property_read_u8_index(np, "qcom,ports-offset1", i, &pcfg->off1);
1477 if (ret)
1478 return ret;
1479
1480 ret = of_property_read_u8_index(np, "qcom,ports-offset2", i, &pcfg->off2);
1481 if (ret)
1482 return ret;
1483
1484 ret = of_property_read_u8_index(np, "qcom,ports-sinterval-low", i, (u8 *)&pcfg->si);
1485 if (ret) {
1486 ret = of_property_read_u16_index(np, "qcom,ports-sinterval", i, &pcfg->si);
1487 if (ret)
1488 return ret;
1489 }
1490
1491 ret = of_property_read_u8_index(np, "qcom,ports-block-pack-mode",
1492 i, &pcfg->bp_mode);
1493 if (ret) {
1494 if (ctrl->version <= SWRM_VERSION_1_3_0)
1495 pcfg->bp_mode = SWR_INVALID_PARAM;
1496 else
1497 return ret;
1498 }
1499
1500 /* Optional properties */
1501 pcfg->hstart = SWR_INVALID_PARAM;
1502 pcfg->hstop = SWR_INVALID_PARAM;
1503 pcfg->word_length = SWR_INVALID_PARAM;
1504 pcfg->blk_group_count = SWR_INVALID_PARAM;
1505 pcfg->lane_control = SWR_INVALID_PARAM;
1506
1507 of_property_read_u8_index(np, "qcom,ports-hstart", i, &pcfg->hstart);
1508
1509 of_property_read_u8_index(np, "qcom,ports-hstop", i, &pcfg->hstop);
1510
1511 of_property_read_u8_index(np, "qcom,ports-word-length", i, &pcfg->word_length);
1512
1513 of_property_read_u8_index(np, "qcom,ports-block-group-count",
1514 i, &pcfg->blk_group_count);
1515
1516 of_property_read_u8_index(np, "qcom,ports-lane-control", i, &pcfg->lane_control);
1517 }
1518
1519 return 0;
1520}
1521
1522#ifdef CONFIG_DEBUG_FS
1523static int swrm_reg_show(struct seq_file *s_file, void *data)
1524{
1525 struct qcom_swrm_ctrl *ctrl = s_file->private;
1526 int reg, reg_val, ret;
1527
1528 ret = pm_runtime_get_sync(ctrl->dev);
1529 if (ret < 0 && ret != -EACCES) {
1530 dev_err_ratelimited(ctrl->dev,
1531 "pm_runtime_get_sync failed in %s, ret %d\n",
1532 __func__, ret);
1533 pm_runtime_put_noidle(ctrl->dev);
1534 return ret;
1535 }
1536
1537 for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1538 ctrl->reg_read(ctrl, reg, &reg_val);
1539 seq_printf(s_file, "0x%.3x: 0x%.2x\n", reg, reg_val);
1540 }
1541 pm_runtime_mark_last_busy(ctrl->dev);
1542 pm_runtime_put_autosuspend(ctrl->dev);
1543
1544
1545 return 0;
1546}
1547DEFINE_SHOW_ATTRIBUTE(swrm_reg);
1548#endif
1549
1550static int qcom_swrm_probe(struct platform_device *pdev)
1551{
1552 struct device *dev = &pdev->dev;
1553 struct sdw_master_prop *prop;
1554 struct sdw_bus_params *params;
1555 struct qcom_swrm_ctrl *ctrl;
1556 const struct qcom_swrm_data *data;
1557 int ret;
1558 u32 val;
1559
1560 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1561 if (!ctrl)
1562 return -ENOMEM;
1563
1564 data = of_device_get_match_data(dev);
1565 ctrl->max_reg = data->max_reg;
1566 ctrl->reg_layout = data->reg_layout;
1567 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1568 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1569#if IS_REACHABLE(CONFIG_SLIMBUS)
1570 if (dev->parent->bus == &slimbus_bus) {
1571#else
1572 if (false) {
1573#endif
1574 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1575 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1576 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1577 if (!ctrl->regmap)
1578 return -EINVAL;
1579 } else {
1580 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1581 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1582 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1583 if (IS_ERR(ctrl->mmio))
1584 return PTR_ERR(ctrl->mmio);
1585 }
1586
1587 if (data->sw_clk_gate_required) {
1588 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1589 if (IS_ERR(ctrl->audio_cgcr)) {
1590 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1591 ret = PTR_ERR(ctrl->audio_cgcr);
1592 goto err_init;
1593 }
1594 }
1595
1596 ctrl->irq = of_irq_get(dev->of_node, 0);
1597 if (ctrl->irq < 0) {
1598 ret = ctrl->irq;
1599 goto err_init;
1600 }
1601
1602 ctrl->hclk = devm_clk_get(dev, "iface");
1603 if (IS_ERR(ctrl->hclk)) {
1604 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1605 goto err_init;
1606 }
1607
1608 clk_prepare_enable(ctrl->hclk);
1609
1610 ctrl->dev = dev;
1611 dev_set_drvdata(&pdev->dev, ctrl);
1612 mutex_init(&ctrl->port_lock);
1613 init_completion(&ctrl->broadcast);
1614 init_completion(&ctrl->enumeration);
1615
1616 ctrl->bus.ops = &qcom_swrm_ops;
1617 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1618 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1619 ctrl->bus.clk_stop_timeout = 300;
1620
1621 ret = qcom_swrm_get_port_config(ctrl);
1622 if (ret)
1623 goto err_clk;
1624
1625 params = &ctrl->bus.params;
1626 params->max_dr_freq = DEFAULT_CLK_FREQ;
1627 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1628 params->col = data->default_cols;
1629 params->row = data->default_rows;
1630 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1631 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1632 params->next_bank = !params->curr_bank;
1633
1634 prop = &ctrl->bus.prop;
1635 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1636 prop->mclk_freq = DEFAULT_CLK_FREQ;
1637 prop->num_clk_gears = 0;
1638 prop->num_clk_freq = MAX_FREQ_NUM;
1639 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1640 prop->default_col = data->default_cols;
1641 prop->default_row = data->default_rows;
1642
1643 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1644
1645 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1646 qcom_swrm_irq_handler,
1647 IRQF_TRIGGER_RISING |
1648 IRQF_ONESHOT,
1649 "soundwire", ctrl);
1650 if (ret) {
1651 dev_err(dev, "Failed to request soundwire irq\n");
1652 goto err_clk;
1653 }
1654
1655 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1656 if (ctrl->wake_irq > 0) {
1657 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1658 qcom_swrm_wake_irq_handler,
1659 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1660 "swr_wake_irq", ctrl);
1661 if (ret) {
1662 dev_err(dev, "Failed to request soundwire wake irq\n");
1663 goto err_init;
1664 }
1665 }
1666
1667 ctrl->bus.controller_id = -1;
1668
1669 if (ctrl->version > SWRM_VERSION_1_3_0) {
1670 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1671 ctrl->bus.controller_id = val;
1672 }
1673
1674 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1675 if (ret) {
1676 dev_err(dev, "Failed to register Soundwire controller (%d)\n",
1677 ret);
1678 goto err_clk;
1679 }
1680
1681 qcom_swrm_init(ctrl);
1682 wait_for_completion_timeout(&ctrl->enumeration,
1683 msecs_to_jiffies(TIMEOUT_MS));
1684 ret = qcom_swrm_register_dais(ctrl);
1685 if (ret)
1686 goto err_master_add;
1687
1688 dev_dbg(dev, "Qualcomm Soundwire controller v%x.%x.%x registered\n",
1689 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1690 ctrl->version & 0xffff);
1691
1692 pm_runtime_set_autosuspend_delay(dev, 3000);
1693 pm_runtime_use_autosuspend(dev);
1694 pm_runtime_mark_last_busy(dev);
1695 pm_runtime_set_active(dev);
1696 pm_runtime_enable(dev);
1697
1698#ifdef CONFIG_DEBUG_FS
1699 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1700 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1701 &swrm_reg_fops);
1702#endif
1703
1704 return 0;
1705
1706err_master_add:
1707 sdw_bus_master_delete(&ctrl->bus);
1708err_clk:
1709 clk_disable_unprepare(ctrl->hclk);
1710err_init:
1711 return ret;
1712}
1713
1714static void qcom_swrm_remove(struct platform_device *pdev)
1715{
1716 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1717
1718 sdw_bus_master_delete(&ctrl->bus);
1719 clk_disable_unprepare(ctrl->hclk);
1720}
1721
1722static int __maybe_unused swrm_runtime_resume(struct device *dev)
1723{
1724 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1725 int ret;
1726
1727 if (ctrl->wake_irq > 0) {
1728 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1729 disable_irq_nosync(ctrl->wake_irq);
1730 }
1731
1732 clk_prepare_enable(ctrl->hclk);
1733
1734 if (ctrl->clock_stop_not_supported) {
1735 reinit_completion(&ctrl->enumeration);
1736 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1737 usleep_range(100, 105);
1738
1739 qcom_swrm_init(ctrl);
1740
1741 usleep_range(100, 105);
1742 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1743 dev_err(ctrl->dev, "link failed to connect\n");
1744
1745 /* wait for hw enumeration to complete */
1746 wait_for_completion_timeout(&ctrl->enumeration,
1747 msecs_to_jiffies(TIMEOUT_MS));
1748 qcom_swrm_get_device_status(ctrl);
1749 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1750 } else {
1751 reset_control_reset(ctrl->audio_cgcr);
1752
1753 if (ctrl->version == SWRM_VERSION_1_7_0) {
1754 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1755 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1756 SWRM_MCP_BUS_CLK_START << SWRM_EE_CPU);
1757 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1758 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1759 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1760 SWRM_V2_0_CLK_CTRL_CLK_START);
1761 } else {
1762 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1763 }
1764 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1765 SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET);
1766
1767 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1768 if (ctrl->version < SWRM_VERSION_2_0_0)
1769 ctrl->reg_write(ctrl,
1770 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1771 ctrl->intr_mask);
1772 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1773 ctrl->intr_mask);
1774
1775 usleep_range(100, 105);
1776 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1777 dev_err(ctrl->dev, "link failed to connect\n");
1778
1779 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1780 if (ret < 0)
1781 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1782 }
1783
1784 return 0;
1785}
1786
1787static int __maybe_unused swrm_runtime_suspend(struct device *dev)
1788{
1789 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1790 int ret;
1791
1792 swrm_wait_for_wr_fifo_done(ctrl);
1793 if (!ctrl->clock_stop_not_supported) {
1794 /* Mask bus clash interrupt */
1795 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1796 if (ctrl->version < SWRM_VERSION_2_0_0)
1797 ctrl->reg_write(ctrl,
1798 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1799 ctrl->intr_mask);
1800 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1801 ctrl->intr_mask);
1802 /* Prepare slaves for clock stop */
1803 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1804 if (ret < 0 && ret != -ENODATA) {
1805 dev_err(dev, "prepare clock stop failed %d", ret);
1806 return ret;
1807 }
1808
1809 ret = sdw_bus_clk_stop(&ctrl->bus);
1810 if (ret < 0 && ret != -ENODATA) {
1811 dev_err(dev, "bus clock stop failed %d", ret);
1812 return ret;
1813 }
1814 }
1815
1816 clk_disable_unprepare(ctrl->hclk);
1817
1818 usleep_range(300, 305);
1819
1820 if (ctrl->wake_irq > 0) {
1821 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1822 enable_irq(ctrl->wake_irq);
1823 }
1824
1825 return 0;
1826}
1827
1828static const struct dev_pm_ops swrm_dev_pm_ops = {
1829 SET_RUNTIME_PM_OPS(swrm_runtime_suspend, swrm_runtime_resume, NULL)
1830};
1831
1832static const struct of_device_id qcom_swrm_of_match[] = {
1833 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1834 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1835 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1836 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1837 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1838 { .compatible = "qcom,soundwire-v3.1.0", .data = &swrm_v3_0_data },
1839 {/* sentinel */},
1840};
1841
1842MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
1843
1844static struct platform_driver qcom_swrm_driver = {
1845 .probe = &qcom_swrm_probe,
1846 .remove = qcom_swrm_remove,
1847 .driver = {
1848 .name = "qcom-soundwire",
1849 .of_match_table = qcom_swrm_of_match,
1850 .pm = &swrm_dev_pm_ops,
1851 }
1852};
1853module_platform_driver(qcom_swrm_driver);
1854
1855MODULE_DESCRIPTION("Qualcomm soundwire driver");
1856MODULE_LICENSE("GPL v2");