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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * USB4 specific functionality
4 *
5 * Copyright (C) 2019, Intel Corporation
6 * Authors: Mika Westerberg <[email protected]>
7 * Rajmohan Mani <[email protected]>
8 */
9
10#include <linux/delay.h>
11#include <linux/ktime.h>
12#include <linux/string_choices.h>
13#include <linux/units.h>
14
15#include "sb_regs.h"
16#include "tb.h"
17
18#define USB4_DATA_RETRIES 3
19#define USB4_DATA_DWORDS 16
20
21#define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2)
22#define USB4_NVM_READ_OFFSET_SHIFT 2
23#define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24)
24#define USB4_NVM_READ_LENGTH_SHIFT 24
25
26#define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK
27#define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT
28
29#define USB4_DROM_ADDRESS_MASK GENMASK(14, 2)
30#define USB4_DROM_ADDRESS_SHIFT 2
31#define USB4_DROM_SIZE_MASK GENMASK(19, 15)
32#define USB4_DROM_SIZE_SHIFT 15
33
34#define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0)
35
36#define USB4_BA_LENGTH_MASK GENMASK(7, 0)
37#define USB4_BA_INDEX_MASK GENMASK(15, 0)
38
39enum usb4_ba_index {
40 USB4_BA_MAX_USB3 = 0x1,
41 USB4_BA_MIN_DP_AUX = 0x2,
42 USB4_BA_MIN_DP_MAIN = 0x3,
43 USB4_BA_MAX_PCIE = 0x4,
44 USB4_BA_MAX_HI = 0x5,
45};
46
47#define USB4_BA_VALUE_MASK GENMASK(31, 16)
48#define USB4_BA_VALUE_SHIFT 16
49
50/* Delays in us used with usb4_port_wait_for_bit() */
51#define USB4_PORT_DELAY 50
52#define USB4_PORT_SB_DELAY 1000
53
54static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
55 u32 *metadata, u8 *status,
56 const void *tx_data, size_t tx_dwords,
57 void *rx_data, size_t rx_dwords)
58{
59 u32 val;
60 int ret;
61
62 if (metadata) {
63 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
64 if (ret)
65 return ret;
66 }
67 if (tx_dwords) {
68 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
69 tx_dwords);
70 if (ret)
71 return ret;
72 }
73
74 val = opcode | ROUTER_CS_26_OV;
75 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
76 if (ret)
77 return ret;
78
79 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
80 if (ret)
81 return ret;
82
83 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
84 if (ret)
85 return ret;
86
87 if (val & ROUTER_CS_26_ONS)
88 return -EOPNOTSUPP;
89
90 if (status)
91 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
92 ROUTER_CS_26_STATUS_SHIFT;
93
94 if (metadata) {
95 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
96 if (ret)
97 return ret;
98 }
99 if (rx_dwords) {
100 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
101 rx_dwords);
102 if (ret)
103 return ret;
104 }
105
106 return 0;
107}
108
109static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
110 u8 *status, const void *tx_data, size_t tx_dwords,
111 void *rx_data, size_t rx_dwords)
112{
113 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
114
115 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
116 return -EINVAL;
117
118 /*
119 * If the connection manager implementation provides USB4 router
120 * operation proxy callback, call it here instead of running the
121 * operation natively.
122 */
123 if (cm_ops->usb4_switch_op) {
124 int ret;
125
126 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
127 tx_data, tx_dwords, rx_data,
128 rx_dwords);
129 if (ret != -EOPNOTSUPP)
130 return ret;
131
132 /*
133 * If the proxy was not supported then run the native
134 * router operation instead.
135 */
136 }
137
138 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
139 tx_dwords, rx_data, rx_dwords);
140}
141
142static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
143 u32 *metadata, u8 *status)
144{
145 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
146}
147
148static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
149 u32 *metadata, u8 *status,
150 const void *tx_data, size_t tx_dwords,
151 void *rx_data, size_t rx_dwords)
152{
153 return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
154 tx_dwords, rx_data, rx_dwords);
155}
156
157/**
158 * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
159 * @sw: Router whose wakes to check
160 *
161 * Checks wakes occurred during suspend and notify the PM core about them.
162 */
163void usb4_switch_check_wakes(struct tb_switch *sw)
164{
165 bool wakeup_usb4 = false;
166 struct usb4_port *usb4;
167 struct tb_port *port;
168 bool wakeup = false;
169 u32 val;
170
171 if (tb_route(sw)) {
172 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
173 return;
174
175 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
176 str_yes_no(val & ROUTER_CS_6_WOPS),
177 str_yes_no(val & ROUTER_CS_6_WOUS));
178
179 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
180 }
181
182 /*
183 * Check for any downstream ports for USB4 wake,
184 * connection wake and disconnection wake.
185 */
186 tb_switch_for_each_port(sw, port) {
187 if (!port->cap_usb4)
188 continue;
189
190 if (tb_port_read(port, &val, TB_CFG_PORT,
191 port->cap_usb4 + PORT_CS_18, 1))
192 break;
193
194 tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
195 str_yes_no(val & PORT_CS_18_WOU4S),
196 str_yes_no(val & PORT_CS_18_WOCS),
197 str_yes_no(val & PORT_CS_18_WODS));
198
199 wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
200 PORT_CS_18_WODS);
201
202 usb4 = port->usb4;
203 if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
204 pm_wakeup_event(&usb4->dev, 0);
205
206 wakeup |= wakeup_usb4;
207 }
208
209 if (wakeup)
210 pm_wakeup_event(&sw->dev, 0);
211}
212
213static bool link_is_usb4(struct tb_port *port)
214{
215 u32 val;
216
217 if (!port->cap_usb4)
218 return false;
219
220 if (tb_port_read(port, &val, TB_CFG_PORT,
221 port->cap_usb4 + PORT_CS_18, 1))
222 return false;
223
224 return !(val & PORT_CS_18_TCM);
225}
226
227/**
228 * usb4_switch_setup() - Additional setup for USB4 device
229 * @sw: USB4 router to setup
230 *
231 * USB4 routers need additional settings in order to enable all the
232 * tunneling. This function enables USB and PCIe tunneling if it can be
233 * enabled (e.g the parent switch also supports them). If USB tunneling
234 * is not available for some reason (like that there is Thunderbolt 3
235 * switch upstream) then the internal xHCI controller is enabled
236 * instead.
237 *
238 * This does not set the configuration valid bit of the router. To do
239 * that call usb4_switch_configuration_valid().
240 *
241 * Return: %0 on success, negative errno otherwise.
242 */
243int usb4_switch_setup(struct tb_switch *sw)
244{
245 struct tb_switch *parent = tb_switch_parent(sw);
246 struct tb_port *down;
247 bool tbt3, xhci;
248 u32 val = 0;
249 int ret;
250
251 if (!tb_route(sw))
252 return 0;
253
254 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
255 if (ret)
256 return ret;
257
258 down = tb_switch_downstream_port(sw);
259 sw->link_usb4 = link_is_usb4(down);
260 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
261
262 xhci = val & ROUTER_CS_6_HCI;
263 tbt3 = !(val & ROUTER_CS_6_TNS);
264
265 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
266 str_yes_no(tbt3), str_yes_no(xhci));
267
268 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
269 if (ret)
270 return ret;
271
272 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
273 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
274 val |= ROUTER_CS_5_UTO;
275 xhci = false;
276 }
277
278 /*
279 * Only enable PCIe tunneling if the parent router supports it
280 * and it is not disabled.
281 */
282 if (tb_acpi_may_tunnel_pcie() &&
283 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
284 val |= ROUTER_CS_5_PTO;
285 /*
286 * xHCI can be enabled if PCIe tunneling is supported
287 * and the parent does not have any USB3 downstream
288 * adapters (so we cannot do USB 3.x tunneling).
289 */
290 if (xhci)
291 val |= ROUTER_CS_5_HCO;
292 }
293
294 /* TBT3 supported by the CM */
295 val &= ~ROUTER_CS_5_CNS;
296
297 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
298 if (ret)
299 return ret;
300
301 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_RR,
302 ROUTER_CS_6_RR, 500);
303}
304
305/**
306 * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
307 * @sw: USB4 router
308 *
309 * Sets configuration valid bit for the router. Must be called before
310 * any tunnels can be set through the router and after
311 * usb4_switch_setup() has been called. Can be called to host and device
312 * routers (does nothing for the former).
313 *
314 * Return: %0 on success, negative errno otherwise.
315 */
316int usb4_switch_configuration_valid(struct tb_switch *sw)
317{
318 u32 val;
319 int ret;
320
321 if (!tb_route(sw))
322 return 0;
323
324 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
325 if (ret)
326 return ret;
327
328 val |= ROUTER_CS_5_CV;
329
330 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
331 if (ret)
332 return ret;
333
334 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
335 ROUTER_CS_6_CR, 500);
336}
337
338/**
339 * usb4_switch_read_uid() - Read UID from USB4 router
340 * @sw: USB4 router
341 * @uid: UID is stored here
342 *
343 * Reads 64-bit UID from USB4 router config space.
344 *
345 * Return: %0 on success, negative errno otherwise.
346 */
347int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
348{
349 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
350}
351
352static int usb4_switch_drom_read_block(void *data,
353 unsigned int dwaddress, void *buf,
354 size_t dwords)
355{
356 struct tb_switch *sw = data;
357 u8 status = 0;
358 u32 metadata;
359 int ret;
360
361 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
362 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
363 USB4_DROM_ADDRESS_MASK;
364
365 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
366 &status, NULL, 0, buf, dwords);
367 if (ret)
368 return ret;
369
370 return status ? -EIO : 0;
371}
372
373/**
374 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
375 * @sw: USB4 router
376 * @address: Byte address inside DROM to start reading
377 * @buf: Buffer where the DROM content is stored
378 * @size: Number of bytes to read from DROM
379 *
380 * Uses USB4 router operations to read router DROM. For devices this
381 * should always work but for hosts it may return %-EOPNOTSUPP in which
382 * case the host router does not have DROM.
383 *
384 * Return: %0 on success, negative errno otherwise.
385 */
386int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
387 size_t size)
388{
389 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
390 usb4_switch_drom_read_block, sw);
391}
392
393/**
394 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
395 * @sw: USB4 router
396 *
397 * Checks whether conditions are met so that lane bonding can be
398 * established with the upstream router. Call only for device routers.
399 *
400 * Return: %true if lane bonding is possible, %false otherwise.
401 */
402bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
403{
404 struct tb_port *up;
405 int ret;
406 u32 val;
407
408 up = tb_upstream_port(sw);
409 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
410 if (ret)
411 return false;
412
413 return !!(val & PORT_CS_18_BE);
414}
415
416/**
417 * usb4_switch_set_wake() - Enabled/disable wake
418 * @sw: USB4 router
419 * @flags: Wakeup flags (%0 to disable)
420 * @runtime: Wake is being programmed during system runtime
421 *
422 * Enables/disables router to wake up from sleep.
423 *
424 * Return: %0 on success, negative errno otherwise.
425 */
426int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags, bool runtime)
427{
428 struct tb_port *port;
429 u64 route = tb_route(sw);
430 u32 val;
431 int ret;
432
433 /*
434 * Enable wakes coming from all USB4 downstream ports (from
435 * child routers). For device routers do this also for the
436 * upstream USB4 port.
437 */
438 tb_switch_for_each_port(sw, port) {
439 if (!tb_port_is_null(port))
440 continue;
441 if (!route && tb_is_upstream_port(port))
442 continue;
443 if (!port->cap_usb4)
444 continue;
445
446 ret = tb_port_read(port, &val, TB_CFG_PORT,
447 port->cap_usb4 + PORT_CS_19, 1);
448 if (ret)
449 return ret;
450
451 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
452
453 if (tb_is_upstream_port(port)) {
454 val |= PORT_CS_19_WOU4;
455 } else {
456 bool configured = val & PORT_CS_19_PC;
457 bool wakeup = runtime || device_may_wakeup(&port->usb4->dev);
458
459 if ((flags & TB_WAKE_ON_CONNECT) && wakeup && !configured)
460 val |= PORT_CS_19_WOC;
461 if ((flags & TB_WAKE_ON_DISCONNECT) && wakeup && configured)
462 val |= PORT_CS_19_WOD;
463 if ((flags & TB_WAKE_ON_USB4) && configured)
464 val |= PORT_CS_19_WOU4;
465 }
466
467 ret = tb_port_write(port, &val, TB_CFG_PORT,
468 port->cap_usb4 + PORT_CS_19, 1);
469 if (ret)
470 return ret;
471 }
472
473 /*
474 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
475 * needed for device routers.
476 */
477 if (route) {
478 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
479 if (ret)
480 return ret;
481
482 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
483 if (flags & TB_WAKE_ON_USB3)
484 val |= ROUTER_CS_5_WOU;
485 if (flags & TB_WAKE_ON_PCIE)
486 val |= ROUTER_CS_5_WOP;
487 if (flags & TB_WAKE_ON_DP)
488 val |= ROUTER_CS_5_WOD;
489
490 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
491 if (ret)
492 return ret;
493 }
494
495 return 0;
496}
497
498/**
499 * usb4_switch_set_sleep() - Prepare the router to enter sleep
500 * @sw: USB4 router
501 *
502 * Sets sleep bit for the router and waits until router sleep ready
503 * bit has been asserted.
504 *
505 * Return: %0 on success, negative errno otherwise.
506 */
507int usb4_switch_set_sleep(struct tb_switch *sw)
508{
509 int ret;
510 u32 val;
511
512 /* Set sleep bit and wait for sleep ready to be asserted */
513 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
514 if (ret)
515 return ret;
516
517 val |= ROUTER_CS_5_SLP;
518
519 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
520 if (ret)
521 return ret;
522
523 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
524 ROUTER_CS_6_SLPR, 500);
525}
526
527/**
528 * usb4_switch_nvm_sector_size() - Return router NVM sector size
529 * @sw: USB4 router
530 *
531 * Return:
532 * * NVM sector size in bytes if router supports NVM operations.
533 * * %-EOPNOTSUPP - If router does not support NVM operations.
534 * * Negative errno - Another error occurred.
535 */
536int usb4_switch_nvm_sector_size(struct tb_switch *sw)
537{
538 u32 metadata;
539 u8 status;
540 int ret;
541
542 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
543 &status);
544 if (ret)
545 return ret;
546
547 if (status)
548 return status == 0x2 ? -EOPNOTSUPP : -EIO;
549
550 return metadata & USB4_NVM_SECTOR_SIZE_MASK;
551}
552
553static int usb4_switch_nvm_read_block(void *data,
554 unsigned int dwaddress, void *buf, size_t dwords)
555{
556 struct tb_switch *sw = data;
557 u8 status = 0;
558 u32 metadata;
559 int ret;
560
561 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
562 USB4_NVM_READ_LENGTH_MASK;
563 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
564 USB4_NVM_READ_OFFSET_MASK;
565
566 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
567 &status, NULL, 0, buf, dwords);
568 if (ret)
569 return ret;
570
571 return status ? -EIO : 0;
572}
573
574/**
575 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
576 * @sw: USB4 router
577 * @address: Starting address in bytes
578 * @buf: Read data is placed here
579 * @size: How many bytes to read
580 *
581 * Reads NVM contents of the router.
582 *
583 * Return:
584 * * %0 - Read completed successfully.
585 * * %-EOPNOTSUPP - NVM not supported.
586 * * Negative errno - Another error occurred.
587 */
588int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
589 size_t size)
590{
591 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
592 usb4_switch_nvm_read_block, sw);
593}
594
595/**
596 * usb4_switch_nvm_set_offset() - Set NVM write offset
597 * @sw: USB4 router
598 * @address: Start offset
599 *
600 * Explicitly sets NVM write offset. Normally when writing to NVM this
601 * is done automatically by usb4_switch_nvm_write().
602 *
603 * Return: %0 on success, negative errno otherwise.
604 */
605int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
606{
607 u32 metadata, dwaddress;
608 u8 status = 0;
609 int ret;
610
611 dwaddress = address / 4;
612 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
613 USB4_NVM_SET_OFFSET_MASK;
614
615 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
616 &status);
617 if (ret)
618 return ret;
619
620 return status ? -EIO : 0;
621}
622
623static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
624 const void *buf, size_t dwords)
625{
626 struct tb_switch *sw = data;
627 u8 status;
628 int ret;
629
630 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
631 buf, dwords, NULL, 0);
632 if (ret)
633 return ret;
634
635 return status ? -EIO : 0;
636}
637
638/**
639 * usb4_switch_nvm_write() - Write to the router NVM
640 * @sw: USB4 router
641 * @address: Start address where to write in bytes
642 * @buf: Pointer to the data to write
643 * @size: Size of @buf in bytes
644 *
645 * Writes @buf to the router NVM using USB4 router operations.
646 *
647 * Return:
648 * * %0 - Write completed successfully.
649 * * %-EOPNOTSUPP - NVM write not supported.
650 * * Negative errno - Another error occurred.
651 */
652int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
653 const void *buf, size_t size)
654{
655 int ret;
656
657 ret = usb4_switch_nvm_set_offset(sw, address);
658 if (ret)
659 return ret;
660
661 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
662 usb4_switch_nvm_write_next_block, sw);
663}
664
665/**
666 * usb4_switch_nvm_authenticate() - Authenticate new NVM
667 * @sw: USB4 router
668 *
669 * After the new NVM has been written via usb4_switch_nvm_write(), this
670 * function triggers NVM authentication process. The router gets power
671 * cycled and if the authentication is successful the new NVM starts
672 * running.
673 *
674 * The caller should call usb4_switch_nvm_authenticate_status() to read
675 * the status of the authentication after power cycle. It should be the
676 * first router operation to avoid the status being lost.
677 *
678 * Return: %0 on success, negative errno otherwise.
679 */
680int usb4_switch_nvm_authenticate(struct tb_switch *sw)
681{
682 int ret;
683
684 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
685 switch (ret) {
686 /*
687 * The router is power cycled once NVM_AUTH is started so it is
688 * expected to get any of the following errors back.
689 */
690 case -EACCES:
691 case -ENOTCONN:
692 case -ETIMEDOUT:
693 return 0;
694
695 default:
696 return ret;
697 }
698}
699
700/**
701 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
702 * @sw: USB4 router
703 * @status: Status code of the operation
704 *
705 * The function checks if there is status available from the last NVM
706 * authenticate router operation.
707 *
708 * Must be called before any other router operation.
709 *
710 * Return:
711 * * %0 - If there is status. Status code is placed in @status.
712 * * Negative errno - Failure occurred.
713 */
714int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
715{
716 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
717 u16 opcode;
718 u32 val;
719 int ret;
720
721 if (cm_ops->usb4_switch_nvm_authenticate_status) {
722 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
723 if (ret != -EOPNOTSUPP)
724 return ret;
725 }
726
727 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
728 if (ret)
729 return ret;
730
731 /* Check that the opcode is correct */
732 opcode = val & ROUTER_CS_26_OPCODE_MASK;
733 if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
734 if (val & ROUTER_CS_26_OV)
735 return -EBUSY;
736 if (val & ROUTER_CS_26_ONS)
737 return -EOPNOTSUPP;
738
739 *status = (val & ROUTER_CS_26_STATUS_MASK) >>
740 ROUTER_CS_26_STATUS_SHIFT;
741 } else {
742 *status = 0;
743 }
744
745 return 0;
746}
747
748/**
749 * usb4_switch_credits_init() - Read buffer allocation parameters
750 * @sw: USB4 router
751 *
752 * Reads @sw buffer allocation parameters and initializes @sw buffer
753 * allocation fields accordingly. Specifically @sw->credits_allocation
754 * is set to %true if these parameters can be used in tunneling.
755 *
756 * Return: %0 on success, negative errno otherwise.
757 */
758int usb4_switch_credits_init(struct tb_switch *sw)
759{
760 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
761 int ret, length, i, nports;
762 const struct tb_port *port;
763 u32 data[USB4_DATA_DWORDS];
764 u32 metadata = 0;
765 u8 status = 0;
766
767 memset(data, 0, sizeof(data));
768 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
769 &status, NULL, 0, data, ARRAY_SIZE(data));
770 if (ret)
771 return ret;
772 if (status)
773 return -EIO;
774
775 length = metadata & USB4_BA_LENGTH_MASK;
776 if (WARN_ON(length > ARRAY_SIZE(data)))
777 return -EMSGSIZE;
778
779 max_usb3 = -1;
780 min_dp_aux = -1;
781 min_dp_main = -1;
782 max_pcie = -1;
783 max_dma = -1;
784
785 tb_sw_dbg(sw, "credit allocation parameters:\n");
786
787 for (i = 0; i < length; i++) {
788 u16 index, value;
789
790 index = data[i] & USB4_BA_INDEX_MASK;
791 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
792
793 switch (index) {
794 case USB4_BA_MAX_USB3:
795 tb_sw_dbg(sw, " USB3: %u\n", value);
796 max_usb3 = value;
797 break;
798 case USB4_BA_MIN_DP_AUX:
799 tb_sw_dbg(sw, " DP AUX: %u\n", value);
800 min_dp_aux = value;
801 break;
802 case USB4_BA_MIN_DP_MAIN:
803 tb_sw_dbg(sw, " DP main: %u\n", value);
804 min_dp_main = value;
805 break;
806 case USB4_BA_MAX_PCIE:
807 tb_sw_dbg(sw, " PCIe: %u\n", value);
808 max_pcie = value;
809 break;
810 case USB4_BA_MAX_HI:
811 tb_sw_dbg(sw, " DMA: %u\n", value);
812 max_dma = value;
813 break;
814 default:
815 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
816 index);
817 break;
818 }
819 }
820
821 /*
822 * Validate the buffer allocation preferences. If we find
823 * issues, log a warning and fall back using the hard-coded
824 * values.
825 */
826
827 /* Host router must report baMaxHI */
828 if (!tb_route(sw) && max_dma < 0) {
829 tb_sw_warn(sw, "host router is missing baMaxHI\n");
830 goto err_invalid;
831 }
832
833 nports = 0;
834 tb_switch_for_each_port(sw, port) {
835 if (tb_port_is_null(port))
836 nports++;
837 }
838
839 /* Must have DP buffer allocation (multiple USB4 ports) */
840 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
841 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
842 goto err_invalid;
843 }
844
845 tb_switch_for_each_port(sw, port) {
846 if (tb_port_is_dpout(port) && min_dp_main < 0) {
847 tb_sw_warn(sw, "missing baMinDPmain");
848 goto err_invalid;
849 }
850 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
851 min_dp_aux < 0) {
852 tb_sw_warn(sw, "missing baMinDPaux");
853 goto err_invalid;
854 }
855 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
856 max_usb3 < 0) {
857 tb_sw_warn(sw, "missing baMaxUSB3");
858 goto err_invalid;
859 }
860 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
861 max_pcie < 0) {
862 tb_sw_warn(sw, "missing baMaxPCIe");
863 goto err_invalid;
864 }
865 }
866
867 /*
868 * Buffer allocation passed the validation so we can use it in
869 * path creation.
870 */
871 sw->credit_allocation = true;
872 if (max_usb3 > 0)
873 sw->max_usb3_credits = max_usb3;
874 if (min_dp_aux > 0)
875 sw->min_dp_aux_credits = min_dp_aux;
876 if (min_dp_main > 0)
877 sw->min_dp_main_credits = min_dp_main;
878 if (max_pcie > 0)
879 sw->max_pcie_credits = max_pcie;
880 if (max_dma > 0)
881 sw->max_dma_credits = max_dma;
882
883 return 0;
884
885err_invalid:
886 return -EINVAL;
887}
888
889/**
890 * usb4_switch_query_dp_resource() - Query availability of DP IN resource
891 * @sw: USB4 router
892 * @in: DP IN adapter
893 *
894 * For DP tunneling this function can be used to query availability of
895 * DP IN resource.
896 *
897 * Return: %true if the resource is available for DP tunneling, %false
898 * otherwise.
899 */
900bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
901{
902 u32 metadata = in->port;
903 u8 status;
904 int ret;
905
906 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
907 &status);
908 /*
909 * If DP resource allocation is not supported assume it is
910 * always available.
911 */
912 if (ret == -EOPNOTSUPP)
913 return true;
914 if (ret)
915 return false;
916
917 return !status;
918}
919
920/**
921 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
922 * @sw: USB4 router
923 * @in: DP IN adapter
924 *
925 * Allocates DP IN resource for DP tunneling using USB4 router
926 * operations.
927 *
928 * Return:
929 * * %0 - Resource allocated successfully.
930 * * %-EBUSY - Resource is already allocated.
931 * * Negative errno - Other failure occurred.
932 */
933int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
934{
935 u32 metadata = in->port;
936 u8 status;
937 int ret;
938
939 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
940 &status);
941 if (ret == -EOPNOTSUPP)
942 return 0;
943 if (ret)
944 return ret;
945
946 return status ? -EBUSY : 0;
947}
948
949/**
950 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
951 * @sw: USB4 router
952 * @in: DP IN adapter
953 *
954 * Releases the previously allocated DP IN resource.
955 *
956 * Return: %0 on success, negative errno otherwise.
957 */
958int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
959{
960 u32 metadata = in->port;
961 u8 status;
962 int ret;
963
964 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
965 &status);
966 if (ret == -EOPNOTSUPP)
967 return 0;
968 if (ret)
969 return ret;
970
971 return status ? -EIO : 0;
972}
973
974/**
975 * usb4_port_index() - Finds matching USB4 port index
976 * @sw: USB4 router
977 * @port: USB4 protocol or lane adapter
978 *
979 * Finds matching USB4 port index (starting from %0) that given @port goes
980 * through.
981 */
982int usb4_port_index(const struct tb_switch *sw, const struct tb_port *port)
983{
984 struct tb_port *p;
985 int usb4_idx = 0;
986
987 /* Assume port is primary */
988 tb_switch_for_each_port(sw, p) {
989 if (!tb_port_is_null(p))
990 continue;
991 if (tb_is_upstream_port(p))
992 continue;
993 if (!p->link_nr) {
994 if (p == port)
995 break;
996 usb4_idx++;
997 }
998 }
999
1000 return usb4_idx;
1001}
1002
1003/**
1004 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
1005 * @sw: USB4 router
1006 * @port: USB4 port
1007 *
1008 * USB4 routers have direct mapping between USB4 ports and PCIe
1009 * downstream adapters where the PCIe topology is extended. This
1010 * function returns the corresponding downstream PCIe adapter or %NULL
1011 * if no such mapping was possible.
1012 *
1013 * Return: Pointer to &struct tb_port or %NULL if not found.
1014 */
1015struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
1016 const struct tb_port *port)
1017{
1018 int usb4_idx = usb4_port_index(sw, port);
1019 struct tb_port *p;
1020 int pcie_idx = 0;
1021
1022 /* Find PCIe down port matching usb4_port */
1023 tb_switch_for_each_port(sw, p) {
1024 if (!tb_port_is_pcie_down(p))
1025 continue;
1026
1027 if (pcie_idx == usb4_idx)
1028 return p;
1029
1030 pcie_idx++;
1031 }
1032
1033 return NULL;
1034}
1035
1036/**
1037 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
1038 * @sw: USB4 router
1039 * @port: USB4 port
1040 *
1041 * USB4 routers have direct mapping between USB4 ports and USB 3.x
1042 * downstream adapters where the USB 3.x topology is extended. This
1043 * function returns the corresponding downstream USB 3.x adapter or
1044 * %NULL if no such mapping was possible.
1045 *
1046 * Return: Pointer to &struct tb_port or %NULL if not found.
1047 */
1048struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1049 const struct tb_port *port)
1050{
1051 int usb4_idx = usb4_port_index(sw, port);
1052 struct tb_port *p;
1053 int usb_idx = 0;
1054
1055 /* Find USB3 down port matching usb4_port */
1056 tb_switch_for_each_port(sw, p) {
1057 if (!tb_port_is_usb3_down(p))
1058 continue;
1059
1060 if (usb_idx == usb4_idx)
1061 return p;
1062
1063 usb_idx++;
1064 }
1065
1066 return NULL;
1067}
1068
1069/**
1070 * usb4_switch_add_ports() - Add USB4 ports for this router
1071 * @sw: USB4 router
1072 *
1073 * For USB4 router finds all USB4 ports and registers devices for each.
1074 * Can be called to any router.
1075 *
1076 * Return: %0 on success, negative errno otherwise.
1077 */
1078int usb4_switch_add_ports(struct tb_switch *sw)
1079{
1080 struct tb_port *port;
1081
1082 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1083 return 0;
1084
1085 tb_switch_for_each_port(sw, port) {
1086 struct usb4_port *usb4;
1087
1088 if (!tb_port_is_null(port))
1089 continue;
1090 if (!port->cap_usb4)
1091 continue;
1092
1093 usb4 = usb4_port_device_add(port);
1094 if (IS_ERR(usb4)) {
1095 usb4_switch_remove_ports(sw);
1096 return PTR_ERR(usb4);
1097 }
1098
1099 port->usb4 = usb4;
1100 }
1101
1102 return 0;
1103}
1104
1105/**
1106 * usb4_switch_remove_ports() - Removes USB4 ports from this router
1107 * @sw: USB4 router
1108 *
1109 * Unregisters previously registered USB4 ports.
1110 */
1111void usb4_switch_remove_ports(struct tb_switch *sw)
1112{
1113 struct tb_port *port;
1114
1115 tb_switch_for_each_port(sw, port) {
1116 if (port->usb4) {
1117 usb4_port_device_remove(port->usb4);
1118 port->usb4 = NULL;
1119 }
1120 }
1121}
1122
1123/**
1124 * usb4_port_unlock() - Unlock USB4 downstream port
1125 * @port: USB4 port to unlock
1126 *
1127 * Unlocks USB4 downstream port so that the connection manager can
1128 * access the router below this port.
1129 *
1130 * Return: %0 on success, negative errno otherwise.
1131 */
1132int usb4_port_unlock(struct tb_port *port)
1133{
1134 int ret;
1135 u32 val;
1136
1137 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1138 if (ret)
1139 return ret;
1140
1141 val &= ~ADP_CS_4_LCK;
1142 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1143}
1144
1145/**
1146 * usb4_port_hotplug_enable() - Enables hotplug for a port
1147 * @port: USB4 port to operate on
1148 *
1149 * Enables hot plug events on a given port. This is only intended
1150 * to be used on lane, DP-IN, and DP-OUT adapters.
1151 *
1152 * Return: %0 on success, negative errno otherwise.
1153 */
1154int usb4_port_hotplug_enable(struct tb_port *port)
1155{
1156 int ret;
1157 u32 val;
1158
1159 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1160 if (ret)
1161 return ret;
1162
1163 val &= ~ADP_CS_5_DHP;
1164 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1165}
1166
1167/**
1168 * usb4_port_reset() - Issue downstream port reset
1169 * @port: USB4 port to reset
1170 *
1171 * Issues downstream port reset to @port.
1172 *
1173 * Return: %0 on success, negative errno otherwise.
1174 */
1175int usb4_port_reset(struct tb_port *port)
1176{
1177 int ret;
1178 u32 val;
1179
1180 if (!port->cap_usb4)
1181 return -EINVAL;
1182
1183 ret = tb_port_read(port, &val, TB_CFG_PORT,
1184 port->cap_usb4 + PORT_CS_19, 1);
1185 if (ret)
1186 return ret;
1187
1188 val |= PORT_CS_19_DPR;
1189
1190 ret = tb_port_write(port, &val, TB_CFG_PORT,
1191 port->cap_usb4 + PORT_CS_19, 1);
1192 if (ret)
1193 return ret;
1194
1195 fsleep(10000);
1196
1197 ret = tb_port_read(port, &val, TB_CFG_PORT,
1198 port->cap_usb4 + PORT_CS_19, 1);
1199 if (ret)
1200 return ret;
1201
1202 val &= ~PORT_CS_19_DPR;
1203
1204 return tb_port_write(port, &val, TB_CFG_PORT,
1205 port->cap_usb4 + PORT_CS_19, 1);
1206}
1207
1208static int usb4_port_set_configured(struct tb_port *port, bool configured)
1209{
1210 int ret;
1211 u32 val;
1212
1213 if (!port->cap_usb4)
1214 return -EINVAL;
1215
1216 ret = tb_port_read(port, &val, TB_CFG_PORT,
1217 port->cap_usb4 + PORT_CS_19, 1);
1218 if (ret)
1219 return ret;
1220
1221 if (configured)
1222 val |= PORT_CS_19_PC;
1223 else
1224 val &= ~PORT_CS_19_PC;
1225
1226 return tb_port_write(port, &val, TB_CFG_PORT,
1227 port->cap_usb4 + PORT_CS_19, 1);
1228}
1229
1230/**
1231 * usb4_port_configure() - Set USB4 port configured
1232 * @port: USB4 router
1233 *
1234 * Sets the USB4 link to be configured for power management purposes.
1235 *
1236 * Return: %0 on success, negative errno otherwise.
1237 */
1238int usb4_port_configure(struct tb_port *port)
1239{
1240 return usb4_port_set_configured(port, true);
1241}
1242
1243/**
1244 * usb4_port_unconfigure() - Set USB4 port unconfigured
1245 * @port: USB4 router
1246 *
1247 * Sets the USB4 link to be unconfigured for power management purposes.
1248 *
1249 * Return: %0 on success, negative errno otherwise.
1250 */
1251void usb4_port_unconfigure(struct tb_port *port)
1252{
1253 usb4_port_set_configured(port, false);
1254}
1255
1256static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1257{
1258 int ret;
1259 u32 val;
1260
1261 if (!port->cap_usb4)
1262 return -EINVAL;
1263
1264 ret = tb_port_read(port, &val, TB_CFG_PORT,
1265 port->cap_usb4 + PORT_CS_19, 1);
1266 if (ret)
1267 return ret;
1268
1269 if (configured)
1270 val |= PORT_CS_19_PID;
1271 else
1272 val &= ~PORT_CS_19_PID;
1273
1274 return tb_port_write(port, &val, TB_CFG_PORT,
1275 port->cap_usb4 + PORT_CS_19, 1);
1276}
1277
1278/**
1279 * usb4_port_configure_xdomain() - Configure port for XDomain
1280 * @port: USB4 port connected to another host
1281 * @xd: XDomain that is connected to the port
1282 *
1283 * Marks the USB4 port as being connected to another host and updates
1284 * the link type.
1285 *
1286 * Return: %0 on success, negative errno otherwise.
1287 */
1288int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1289{
1290 xd->link_usb4 = link_is_usb4(port);
1291 return usb4_set_xdomain_configured(port, true);
1292}
1293
1294/**
1295 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1296 * @port: USB4 port that was connected to another host
1297 *
1298 * Clears USB4 port from being marked as XDomain.
1299 */
1300void usb4_port_unconfigure_xdomain(struct tb_port *port)
1301{
1302 usb4_set_xdomain_configured(port, false);
1303}
1304
1305static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1306 u32 value, int timeout_msec, unsigned long delay_usec)
1307{
1308 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1309
1310 do {
1311 u32 val;
1312 int ret;
1313
1314 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1315 if (ret)
1316 return ret;
1317
1318 if ((val & bit) == value)
1319 return 0;
1320
1321 fsleep(delay_usec);
1322 } while (ktime_before(ktime_get(), timeout));
1323
1324 return -ETIMEDOUT;
1325}
1326
1327static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1328{
1329 if (dwords > USB4_DATA_DWORDS)
1330 return -EINVAL;
1331
1332 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1333 dwords);
1334}
1335
1336static int usb4_port_write_data(struct tb_port *port, const void *data,
1337 size_t dwords)
1338{
1339 if (dwords > USB4_DATA_DWORDS)
1340 return -EINVAL;
1341
1342 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1343 dwords);
1344}
1345
1346/**
1347 * usb4_port_sb_read() - Read from sideband register
1348 * @port: USB4 port to read
1349 * @target: Sideband target
1350 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1351 * @reg: Sideband register index
1352 * @buf: Buffer where the sideband data is copied
1353 * @size: Size of @buf
1354 *
1355 * Reads data from sideband register @reg and copies it into @buf.
1356 *
1357 * Return: %0 on success, negative errno otherwise.
1358 */
1359int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, u8 index,
1360 u8 reg, void *buf, u8 size)
1361{
1362 size_t dwords = DIV_ROUND_UP(size, 4);
1363 int ret;
1364 u32 val;
1365
1366 if (!port->cap_usb4)
1367 return -EINVAL;
1368
1369 val = reg;
1370 val |= size << PORT_CS_1_LENGTH_SHIFT;
1371 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1372 if (target == USB4_SB_TARGET_RETIMER)
1373 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1374 val |= PORT_CS_1_PND;
1375
1376 ret = tb_port_write(port, &val, TB_CFG_PORT,
1377 port->cap_usb4 + PORT_CS_1, 1);
1378 if (ret)
1379 return ret;
1380
1381 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1382 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1383 if (ret)
1384 return ret;
1385
1386 ret = tb_port_read(port, &val, TB_CFG_PORT,
1387 port->cap_usb4 + PORT_CS_1, 1);
1388 if (ret)
1389 return ret;
1390
1391 if (val & PORT_CS_1_NR)
1392 return -ENODEV;
1393 if (val & PORT_CS_1_RC)
1394 return -EIO;
1395
1396 return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1397}
1398
1399/**
1400 * usb4_port_sb_write() - Write to sideband register
1401 * @port: USB4 port to write
1402 * @target: Sideband target
1403 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1404 * @reg: Sideband register index
1405 * @buf: Data to write
1406 * @size: Size of @buf
1407 *
1408 * Writes @buf to sideband register @reg.
1409 *
1410 * Return: %0 on success, negative errno otherwise.
1411 */
1412int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1413 u8 index, u8 reg, const void *buf, u8 size)
1414{
1415 size_t dwords = DIV_ROUND_UP(size, 4);
1416 int ret;
1417 u32 val;
1418
1419 if (!port->cap_usb4)
1420 return -EINVAL;
1421
1422 if (buf) {
1423 ret = usb4_port_write_data(port, buf, dwords);
1424 if (ret)
1425 return ret;
1426 }
1427
1428 val = reg;
1429 val |= size << PORT_CS_1_LENGTH_SHIFT;
1430 val |= PORT_CS_1_WNR_WRITE;
1431 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1432 if (target == USB4_SB_TARGET_RETIMER)
1433 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1434 val |= PORT_CS_1_PND;
1435
1436 ret = tb_port_write(port, &val, TB_CFG_PORT,
1437 port->cap_usb4 + PORT_CS_1, 1);
1438 if (ret)
1439 return ret;
1440
1441 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1442 PORT_CS_1_PND, 0, 500, USB4_PORT_SB_DELAY);
1443 if (ret)
1444 return ret;
1445
1446 ret = tb_port_read(port, &val, TB_CFG_PORT,
1447 port->cap_usb4 + PORT_CS_1, 1);
1448 if (ret)
1449 return ret;
1450
1451 if (val & PORT_CS_1_NR)
1452 return -ENODEV;
1453 if (val & PORT_CS_1_RC)
1454 return -EIO;
1455
1456 return 0;
1457}
1458
1459static int usb4_port_sb_opcode_err_to_errno(u32 val)
1460{
1461 switch (val) {
1462 case 0:
1463 return 0;
1464 case USB4_SB_OPCODE_ERR:
1465 return -EAGAIN;
1466 case USB4_SB_OPCODE_ONS:
1467 return -EOPNOTSUPP;
1468 default:
1469 return -EIO;
1470 }
1471}
1472
1473static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1474 u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1475{
1476 ktime_t timeout;
1477 u32 val;
1478 int ret;
1479
1480 val = opcode;
1481 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1482 sizeof(val));
1483 if (ret)
1484 return ret;
1485
1486 timeout = ktime_add_ms(ktime_get(), timeout_msec);
1487
1488 do {
1489 /* Check results */
1490 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1491 &val, sizeof(val));
1492 if (ret)
1493 return ret;
1494
1495 if (val != opcode)
1496 return usb4_port_sb_opcode_err_to_errno(val);
1497
1498 fsleep(USB4_PORT_SB_DELAY);
1499 } while (ktime_before(ktime_get(), timeout));
1500
1501 return -ETIMEDOUT;
1502}
1503
1504static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1505{
1506 u32 val = !offline;
1507 int ret;
1508
1509 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1510 USB4_SB_METADATA, &val, sizeof(val));
1511 if (ret)
1512 return ret;
1513
1514 val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1515 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1516 USB4_SB_OPCODE, &val, sizeof(val));
1517}
1518
1519/**
1520 * usb4_port_router_offline() - Put the USB4 port to offline mode
1521 * @port: USB4 port
1522 *
1523 * This function puts the USB4 port into offline mode. In this mode the
1524 * port does not react on hotplug events anymore. This needs to be
1525 * called before retimer access is done when the USB4 links is not up.
1526 *
1527 * Return: %0 on success, negative errno otherwise.
1528 */
1529int usb4_port_router_offline(struct tb_port *port)
1530{
1531 return usb4_port_set_router_offline(port, true);
1532}
1533
1534/**
1535 * usb4_port_router_online() - Put the USB4 port back online
1536 * @port: USB4 port
1537 *
1538 * Makes the USB4 port functional again.
1539 *
1540 * Return: %0 on success, negative errno otherwise.
1541 */
1542int usb4_port_router_online(struct tb_port *port)
1543{
1544 return usb4_port_set_router_offline(port, false);
1545}
1546
1547/**
1548 * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1549 * @port: USB4 port
1550 *
1551 * This forces the USB4 port to send broadcast RT transaction which
1552 * makes the retimers on the link assign index to themselves.
1553 *
1554 * Return: %0 on success, negative errno otherwise.
1555 */
1556int usb4_port_enumerate_retimers(struct tb_port *port)
1557{
1558 u32 val;
1559
1560 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1561 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1562 USB4_SB_OPCODE, &val, sizeof(val));
1563}
1564
1565/**
1566 * usb4_port_clx_supported() - Check if CLx is supported by the link
1567 * @port: Port to check for CLx support for
1568 *
1569 * PORT_CS_18_CPS bit reflects if the link supports CLx including
1570 * active cables (if connected on the link).
1571 *
1572 * Return: %true if Clx is supported, %false otherwise.
1573 */
1574bool usb4_port_clx_supported(struct tb_port *port)
1575{
1576 int ret;
1577 u32 val;
1578
1579 ret = tb_port_read(port, &val, TB_CFG_PORT,
1580 port->cap_usb4 + PORT_CS_18, 1);
1581 if (ret)
1582 return false;
1583
1584 return !!(val & PORT_CS_18_CPS);
1585}
1586
1587/**
1588 * usb4_port_asym_supported() - If the port supports asymmetric link
1589 * @port: USB4 port
1590 *
1591 * Checks if the port and the cable support asymmetric link.
1592 *
1593 * Return: %true if asymmetric link is supported, %false otherwise.
1594 */
1595bool usb4_port_asym_supported(struct tb_port *port)
1596{
1597 u32 val;
1598
1599 if (!port->cap_usb4)
1600 return false;
1601
1602 if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
1603 return false;
1604
1605 return !!(val & PORT_CS_18_CSA);
1606}
1607
1608/**
1609 * usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
1610 * @port: USB4 port
1611 * @width: Asymmetric width to configure
1612 *
1613 * Sets USB4 port link width to @width. Can be called for widths where
1614 * usb4_port_asym_width_supported() returned @true.
1615 *
1616 * Return: %0 on success, negative errno otherwise.
1617 */
1618int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
1619{
1620 u32 val;
1621 int ret;
1622
1623 if (!port->cap_phy)
1624 return -EINVAL;
1625
1626 ret = tb_port_read(port, &val, TB_CFG_PORT,
1627 port->cap_phy + LANE_ADP_CS_1, 1);
1628 if (ret)
1629 return ret;
1630
1631 val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
1632 switch (width) {
1633 case TB_LINK_WIDTH_DUAL:
1634 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1635 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
1636 break;
1637 case TB_LINK_WIDTH_ASYM_TX:
1638 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1639 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
1640 break;
1641 case TB_LINK_WIDTH_ASYM_RX:
1642 val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
1643 LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
1644 break;
1645 default:
1646 return -EINVAL;
1647 }
1648
1649 return tb_port_write(port, &val, TB_CFG_PORT,
1650 port->cap_phy + LANE_ADP_CS_1, 1);
1651}
1652
1653/**
1654 * usb4_port_asym_start() - Start symmetry change and wait for completion
1655 * @port: USB4 port
1656 *
1657 * Start symmetry change of the link to asymmetric or symmetric
1658 * (according to what was previously set in tb_port_set_link_width().
1659 * Wait for completion of the change.
1660 *
1661 * Return:
1662 * * %0 - Symmetry change was successful.
1663 * * %-ETIMEDOUT - Timeout occurred.
1664 * * Negative errno - Other failure occurred.
1665 */
1666int usb4_port_asym_start(struct tb_port *port)
1667{
1668 int ret;
1669 u32 val;
1670
1671 ret = tb_port_read(port, &val, TB_CFG_PORT,
1672 port->cap_usb4 + PORT_CS_19, 1);
1673 if (ret)
1674 return ret;
1675
1676 val &= ~PORT_CS_19_START_ASYM;
1677 val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
1678
1679 ret = tb_port_write(port, &val, TB_CFG_PORT,
1680 port->cap_usb4 + PORT_CS_19, 1);
1681 if (ret)
1682 return ret;
1683
1684 /*
1685 * Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
1686 * port started the symmetry transition.
1687 */
1688 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
1689 PORT_CS_19_START_ASYM, 0, 1000,
1690 USB4_PORT_DELAY);
1691 if (ret)
1692 return ret;
1693
1694 /* Then wait for the transtion to be completed */
1695 return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
1696 PORT_CS_18_TIP, 0, 5000, USB4_PORT_DELAY);
1697}
1698
1699/**
1700 * usb4_port_margining_caps() - Read USB4 port margining capabilities
1701 * @port: USB4 port
1702 * @target: Sideband target
1703 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1704 * @caps: Array with at least two elements to hold the results
1705 * @ncaps: Number of elements in the caps array
1706 *
1707 * Reads the USB4 port lane margining capabilities into @caps.
1708 *
1709 * Return: %0 on success, negative errno otherwise.
1710 */
1711int usb4_port_margining_caps(struct tb_port *port, enum usb4_sb_target target,
1712 u8 index, u32 *caps, size_t ncaps)
1713{
1714 int ret;
1715
1716 ret = usb4_port_sb_op(port, target, index,
1717 USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1718 if (ret)
1719 return ret;
1720
1721 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, caps,
1722 sizeof(*caps) * ncaps);
1723}
1724
1725/**
1726 * usb4_port_hw_margin() - Run hardware lane margining on port
1727 * @port: USB4 port
1728 * @target: Sideband target
1729 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1730 * @params: Parameters for USB4 hardware margining
1731 * @results: Array to hold the results
1732 * @nresults: Number of elements in the results array
1733 *
1734 * Runs hardware lane margining on USB4 port and returns the result in
1735 * @results.
1736 *
1737 * Return: %0 on success, negative errno otherwise.
1738 */
1739int usb4_port_hw_margin(struct tb_port *port, enum usb4_sb_target target,
1740 u8 index, const struct usb4_port_margining_params *params,
1741 u32 *results, size_t nresults)
1742{
1743 u32 val;
1744 int ret;
1745
1746 if (WARN_ON_ONCE(!params))
1747 return -EINVAL;
1748
1749 val = params->lanes;
1750 if (params->time)
1751 val |= USB4_MARGIN_HW_TIME;
1752 if (params->right_high || params->upper_eye)
1753 val |= USB4_MARGIN_HW_RHU;
1754 if (params->ber_level)
1755 val |= FIELD_PREP(USB4_MARGIN_HW_BER_MASK, params->ber_level);
1756 if (params->optional_voltage_offset_range)
1757 val |= USB4_MARGIN_HW_OPT_VOLTAGE;
1758
1759 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1760 sizeof(val));
1761 if (ret)
1762 return ret;
1763
1764 ret = usb4_port_sb_op(port, target, index,
1765 USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1766 if (ret)
1767 return ret;
1768
1769 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
1770 sizeof(*results) * nresults);
1771}
1772
1773/**
1774 * usb4_port_sw_margin() - Run software lane margining on port
1775 * @port: USB4 port
1776 * @target: Sideband target
1777 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1778 * @params: Parameters for USB4 software margining
1779 * @results: Data word for the operation completion data
1780 *
1781 * Runs software lane margining on USB4 port. Read back the error
1782 * counters by calling usb4_port_sw_margin_errors().
1783 *
1784 * Return: %0 on success, negative errno otherwise.
1785 */
1786int usb4_port_sw_margin(struct tb_port *port, enum usb4_sb_target target,
1787 u8 index, const struct usb4_port_margining_params *params,
1788 u32 *results)
1789{
1790 u32 val;
1791 int ret;
1792
1793 if (WARN_ON_ONCE(!params))
1794 return -EINVAL;
1795
1796 val = params->lanes;
1797 if (params->time)
1798 val |= USB4_MARGIN_SW_TIME;
1799 if (params->optional_voltage_offset_range)
1800 val |= USB4_MARGIN_SW_OPT_VOLTAGE;
1801 if (params->right_high)
1802 val |= USB4_MARGIN_SW_RH;
1803 if (params->upper_eye)
1804 val |= USB4_MARGIN_SW_UPPER_EYE;
1805 val |= FIELD_PREP(USB4_MARGIN_SW_COUNTER_MASK, params->error_counter);
1806 val |= FIELD_PREP(USB4_MARGIN_SW_VT_MASK, params->voltage_time_offset);
1807
1808 ret = usb4_port_sb_write(port, target, index, USB4_SB_METADATA, &val,
1809 sizeof(val));
1810 if (ret)
1811 return ret;
1812
1813 ret = usb4_port_sb_op(port, target, index,
1814 USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1815 if (ret)
1816 return ret;
1817
1818 return usb4_port_sb_read(port, target, index, USB4_SB_DATA, results,
1819 sizeof(*results));
1820
1821}
1822
1823/**
1824 * usb4_port_sw_margin_errors() - Read the software margining error counters
1825 * @port: USB4 port
1826 * @target: Sideband target
1827 * @index: Retimer index if target is %USB4_SB_TARGET_RETIMER
1828 * @errors: Error metadata is copied here.
1829 *
1830 * This reads back the software margining error counters from the port.
1831 *
1832 * Return: %0 on success, negative errno otherwise.
1833 */
1834int usb4_port_sw_margin_errors(struct tb_port *port, enum usb4_sb_target target,
1835 u8 index, u32 *errors)
1836{
1837 int ret;
1838
1839 ret = usb4_port_sb_op(port, target, index,
1840 USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1841 if (ret)
1842 return ret;
1843
1844 return usb4_port_sb_read(port, target, index, USB4_SB_METADATA, errors,
1845 sizeof(*errors));
1846}
1847
1848static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1849 enum usb4_sb_opcode opcode,
1850 int timeout_msec)
1851{
1852 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1853 timeout_msec);
1854}
1855
1856/**
1857 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1858 * @port: USB4 port
1859 * @index: Retimer index
1860 *
1861 * Enables sideband channel transactions on SBTX. Can be used when USB4
1862 * link does not go up, for example if there is no device connected.
1863 *
1864 * Return: %0 on success, negative errno otherwise.
1865 */
1866int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1867{
1868 int ret;
1869
1870 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1871 500);
1872
1873 if (ret != -ENODEV)
1874 return ret;
1875
1876 /*
1877 * Per the USB4 retimer spec, the retimer is not required to
1878 * send an RT (Retimer Transaction) response for the first
1879 * SET_INBOUND_SBTX command
1880 */
1881 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1882 500);
1883}
1884
1885/**
1886 * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1887 * @port: USB4 port
1888 * @index: Retimer index
1889 *
1890 * Disables sideband channel transactions on SBTX. The reverse of
1891 * usb4_port_retimer_set_inbound_sbtx().
1892 *
1893 * Return: %0 on success, negative errno otherwise.
1894 */
1895int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1896{
1897 return usb4_port_retimer_op(port, index,
1898 USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1899}
1900
1901/**
1902 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1903 * @port: USB4 port
1904 * @index: Retimer index
1905 *
1906 * Return:
1907 * * %1 - Retimer at @index is the last one (connected directly to the
1908 * Type-C port).
1909 * * %0 - Retimer at @index is not the last one.
1910 * * %-ENODEV - Retimer is not present.
1911 * * Negative errno - Other failure occurred.
1912 */
1913int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1914{
1915 u32 metadata;
1916 int ret;
1917
1918 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1919 500);
1920 if (ret)
1921 return ret;
1922
1923 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1924 USB4_SB_METADATA, &metadata, sizeof(metadata));
1925 return ret ? ret : metadata & 1;
1926}
1927
1928/**
1929 * usb4_port_retimer_is_cable() - Is the retimer cable retimer
1930 * @port: USB4 port
1931 * @index: Retimer index
1932 *
1933 * Return:
1934 * * %1 - Retimer at @index is the last cable retimer.
1935 * * %0 - Retimer at @index is on-board retimer.
1936 * * %-ENODEV - Retimer is not present.
1937 * * Negative errno - Other failure occurred.
1938 */
1939int usb4_port_retimer_is_cable(struct tb_port *port, u8 index)
1940{
1941 u32 metadata;
1942 int ret;
1943
1944 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_CABLE_RETIMER,
1945 500);
1946 if (ret)
1947 return ret;
1948
1949 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1950 USB4_SB_METADATA, &metadata, sizeof(metadata));
1951 return ret ? ret : metadata & 1;
1952}
1953
1954/**
1955 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1956 * @port: USB4 port
1957 * @index: Retimer index
1958 *
1959 * Reads NVM sector size (in bytes) of a retimer at @index. This
1960 * operation can be used to determine whether the retimer supports NVM
1961 * upgrade for example.
1962 *
1963 * Return:
1964 * * Sector size in bytes.
1965 * * %-ENODEV - If there is no retimer at @index.
1966 * * Negative errno - In case of an error.
1967 */
1968int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1969{
1970 u32 metadata;
1971 int ret;
1972
1973 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1974 500);
1975 if (ret)
1976 return ret;
1977
1978 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
1979 USB4_SB_METADATA, &metadata, sizeof(metadata));
1980 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1981}
1982
1983/**
1984 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1985 * @port: USB4 port
1986 * @index: Retimer index
1987 * @address: Start offset
1988 *
1989 * Explicitly sets NVM write offset. Normally when writing to NVM this is
1990 * done automatically by usb4_port_retimer_nvm_write().
1991 *
1992 * Return: %0 on success, negative errno otherwise.
1993 */
1994int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1995 unsigned int address)
1996{
1997 u32 metadata, dwaddress;
1998 int ret;
1999
2000 dwaddress = address / 4;
2001 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
2002 USB4_NVM_SET_OFFSET_MASK;
2003
2004 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2005 USB4_SB_METADATA, &metadata, sizeof(metadata));
2006 if (ret)
2007 return ret;
2008
2009 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
2010 500);
2011}
2012
2013struct retimer_info {
2014 struct tb_port *port;
2015 u8 index;
2016};
2017
2018static int usb4_port_retimer_nvm_write_next_block(void *data,
2019 unsigned int dwaddress, const void *buf, size_t dwords)
2020
2021{
2022 const struct retimer_info *info = data;
2023 struct tb_port *port = info->port;
2024 u8 index = info->index;
2025 int ret;
2026
2027 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2028 USB4_SB_DATA, buf, dwords * 4);
2029 if (ret)
2030 return ret;
2031
2032 return usb4_port_retimer_op(port, index,
2033 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
2034}
2035
2036/**
2037 * usb4_port_retimer_nvm_write() - Write to retimer NVM
2038 * @port: USB4 port
2039 * @index: Retimer index
2040 * @address: Byte address where to start the write
2041 * @buf: Data to write
2042 * @size: Size in bytes how much to write
2043 *
2044 * Writes @size bytes from @buf to the retimer NVM. Used for NVM
2045 * upgrade.
2046 *
2047 * Return:
2048 * * %0 - If the data was written successfully.
2049 * * %-ENODEV - If there is no retimer at @index.
2050 * * Negative errno - In case of an error.
2051 */
2052int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
2053 const void *buf, size_t size)
2054{
2055 struct retimer_info info = { .port = port, .index = index };
2056 int ret;
2057
2058 ret = usb4_port_retimer_nvm_set_offset(port, index, address);
2059 if (ret)
2060 return ret;
2061
2062 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
2063 usb4_port_retimer_nvm_write_next_block, &info);
2064}
2065
2066/**
2067 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
2068 * @port: USB4 port
2069 * @index: Retimer index
2070 *
2071 * After the new NVM image has been written via usb4_port_retimer_nvm_write()
2072 * this function can be used to trigger the NVM upgrade process. If
2073 * successful the retimer restarts with the new NVM and may not have the
2074 * index set so one needs to call usb4_port_enumerate_retimers() to
2075 * force index to be assigned.
2076 *
2077 * Return: %0 on success, negative errno otherwise.
2078 */
2079int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
2080{
2081 u32 val;
2082
2083 /*
2084 * We need to use the raw operation here because once the
2085 * authentication completes the retimer index is not set anymore
2086 * so we do not get back the status now.
2087 */
2088 val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
2089 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2090 USB4_SB_OPCODE, &val, sizeof(val));
2091}
2092
2093/**
2094 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
2095 * @port: USB4 port
2096 * @index: Retimer index
2097 * @status: Raw status code read from metadata
2098 *
2099 * This can be called after usb4_port_retimer_nvm_authenticate() and
2100 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
2101 *
2102 * Return: %0 if the authentication status was successfully read. The
2103 * completion metadata (the result) is then stored into @status. If
2104 * status read fails, returns negative errno.
2105 */
2106int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
2107 u32 *status)
2108{
2109 u32 metadata, val;
2110 int ret;
2111
2112 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2113 USB4_SB_OPCODE, &val, sizeof(val));
2114 if (ret)
2115 return ret;
2116
2117 ret = usb4_port_sb_opcode_err_to_errno(val);
2118 switch (ret) {
2119 case 0:
2120 *status = 0;
2121 return 0;
2122
2123 case -EAGAIN:
2124 ret = usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2125 USB4_SB_METADATA, &metadata,
2126 sizeof(metadata));
2127 if (ret)
2128 return ret;
2129
2130 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
2131 return 0;
2132
2133 default:
2134 return ret;
2135 }
2136}
2137
2138static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
2139 void *buf, size_t dwords)
2140{
2141 const struct retimer_info *info = data;
2142 struct tb_port *port = info->port;
2143 u8 index = info->index;
2144 u32 metadata;
2145 int ret;
2146
2147 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
2148 if (dwords < USB4_DATA_DWORDS)
2149 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
2150
2151 ret = usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
2152 USB4_SB_METADATA, &metadata, sizeof(metadata));
2153 if (ret)
2154 return ret;
2155
2156 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
2157 if (ret)
2158 return ret;
2159
2160 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index,
2161 USB4_SB_DATA, buf, dwords * 4);
2162}
2163
2164/**
2165 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
2166 * @port: USB4 port
2167 * @index: Retimer index
2168 * @address: NVM address (in bytes) to start reading
2169 * @buf: Data read from NVM is stored here
2170 * @size: Number of bytes to read
2171 *
2172 * Reads retimer NVM and copies the contents to @buf.
2173 *
2174 * Return:
2175 * * %0 - If the read was successful.
2176 * * %-ENODEV - If there is no retimer at @index.
2177 * * Negative errno - In case of an error.
2178 */
2179int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
2180 unsigned int address, void *buf, size_t size)
2181{
2182 struct retimer_info info = { .port = port, .index = index };
2183
2184 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
2185 usb4_port_retimer_nvm_read_block, &info);
2186}
2187
2188static inline unsigned int
2189usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
2190{
2191 /* Take the possible bandwidth limitation into account */
2192 if (port->max_bw)
2193 return min(bw, port->max_bw);
2194 return bw;
2195}
2196
2197/**
2198 * usb4_usb3_port_max_link_rate() - Maximum supported USB3 link rate
2199 * @port: USB3 adapter port
2200 *
2201 * Return: Maximum supported link rate of a USB3 adapter in Mb/s.
2202 * Negative errno in case of an error.
2203 */
2204int usb4_usb3_port_max_link_rate(struct tb_port *port)
2205{
2206 int ret, lr;
2207 u32 val;
2208
2209 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2210 return -EINVAL;
2211
2212 ret = tb_port_read(port, &val, TB_CFG_PORT,
2213 port->cap_adap + ADP_USB3_CS_4, 1);
2214 if (ret)
2215 return ret;
2216
2217 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
2218 ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
2219
2220 return usb4_usb3_port_max_bandwidth(port, ret);
2221}
2222
2223static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2224{
2225 int ret;
2226 u32 val;
2227
2228 if (!tb_port_is_usb3_down(port))
2229 return -EINVAL;
2230 if (tb_route(port->sw))
2231 return -EINVAL;
2232
2233 ret = tb_port_read(port, &val, TB_CFG_PORT,
2234 port->cap_adap + ADP_USB3_CS_2, 1);
2235 if (ret)
2236 return ret;
2237
2238 if (request)
2239 val |= ADP_USB3_CS_2_CMR;
2240 else
2241 val &= ~ADP_USB3_CS_2_CMR;
2242
2243 ret = tb_port_write(port, &val, TB_CFG_PORT,
2244 port->cap_adap + ADP_USB3_CS_2, 1);
2245 if (ret)
2246 return ret;
2247
2248 /*
2249 * We can use val here directly as the CMR bit is in the same place
2250 * as HCA. Just mask out others.
2251 */
2252 val &= ADP_USB3_CS_2_CMR;
2253 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2254 ADP_USB3_CS_1_HCA, val, 1500,
2255 USB4_PORT_DELAY);
2256}
2257
2258static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2259{
2260 return usb4_usb3_port_cm_request(port, true);
2261}
2262
2263static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2264{
2265 return usb4_usb3_port_cm_request(port, false);
2266}
2267
2268static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2269{
2270 unsigned long uframes;
2271
2272 uframes = bw * 512UL << scale;
2273 return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2274}
2275
2276static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2277{
2278 unsigned long uframes;
2279
2280 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2281 uframes = ((unsigned long)mbps * MEGA) / 8000;
2282 return DIV_ROUND_UP(uframes, 512UL << scale);
2283}
2284
2285static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2286 int *upstream_bw,
2287 int *downstream_bw)
2288{
2289 u32 val, bw, scale;
2290 int ret;
2291
2292 ret = tb_port_read(port, &val, TB_CFG_PORT,
2293 port->cap_adap + ADP_USB3_CS_2, 1);
2294 if (ret)
2295 return ret;
2296
2297 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2298 port->cap_adap + ADP_USB3_CS_3, 1);
2299 if (ret)
2300 return ret;
2301
2302 scale &= ADP_USB3_CS_3_SCALE_MASK;
2303
2304 bw = val & ADP_USB3_CS_2_AUBW_MASK;
2305 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2306
2307 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2308 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2309
2310 return 0;
2311}
2312
2313/**
2314 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2315 * @port: USB3 adapter port
2316 * @upstream_bw: Allocated upstream bandwidth is stored here
2317 * @downstream_bw: Allocated downstream bandwidth is stored here
2318 *
2319 * Stores currently allocated USB3 bandwidth into @upstream_bw and
2320 * @downstream_bw in Mb/s.
2321 *
2322 * Return: %0 on success, negative errno otherwise.
2323 */
2324int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2325 int *downstream_bw)
2326{
2327 int ret;
2328
2329 ret = usb4_usb3_port_set_cm_request(port);
2330 if (ret)
2331 return ret;
2332
2333 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2334 downstream_bw);
2335 usb4_usb3_port_clear_cm_request(port);
2336
2337 return ret;
2338}
2339
2340static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2341 int *upstream_bw,
2342 int *downstream_bw)
2343{
2344 u32 val, bw, scale;
2345 int ret;
2346
2347 ret = tb_port_read(port, &val, TB_CFG_PORT,
2348 port->cap_adap + ADP_USB3_CS_1, 1);
2349 if (ret)
2350 return ret;
2351
2352 ret = tb_port_read(port, &scale, TB_CFG_PORT,
2353 port->cap_adap + ADP_USB3_CS_3, 1);
2354 if (ret)
2355 return ret;
2356
2357 scale &= ADP_USB3_CS_3_SCALE_MASK;
2358
2359 bw = val & ADP_USB3_CS_1_CUBW_MASK;
2360 *upstream_bw = usb3_bw_to_mbps(bw, scale);
2361
2362 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2363 *downstream_bw = usb3_bw_to_mbps(bw, scale);
2364
2365 return 0;
2366}
2367
2368static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2369 int upstream_bw,
2370 int downstream_bw)
2371{
2372 u32 val, ubw, dbw, scale;
2373 int ret, max_bw;
2374
2375 /* Figure out suitable scale */
2376 scale = 0;
2377 max_bw = max(upstream_bw, downstream_bw);
2378 while (scale < 64) {
2379 if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2380 break;
2381 scale++;
2382 }
2383
2384 if (WARN_ON(scale >= 64))
2385 return -EINVAL;
2386
2387 ret = tb_port_write(port, &scale, TB_CFG_PORT,
2388 port->cap_adap + ADP_USB3_CS_3, 1);
2389 if (ret)
2390 return ret;
2391
2392 ubw = mbps_to_usb3_bw(upstream_bw, scale);
2393 dbw = mbps_to_usb3_bw(downstream_bw, scale);
2394
2395 tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2396
2397 ret = tb_port_read(port, &val, TB_CFG_PORT,
2398 port->cap_adap + ADP_USB3_CS_2, 1);
2399 if (ret)
2400 return ret;
2401
2402 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2403 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2404 val |= ubw;
2405
2406 return tb_port_write(port, &val, TB_CFG_PORT,
2407 port->cap_adap + ADP_USB3_CS_2, 1);
2408}
2409
2410/**
2411 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2412 * @port: USB3 adapter port
2413 * @upstream_bw: New upstream bandwidth
2414 * @downstream_bw: New downstream bandwidth
2415 *
2416 * This can be used to set how much bandwidth is allocated for the USB3
2417 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2418 * new values programmed to the USB3 adapter allocation registers. If
2419 * the values are lower than what is currently consumed the allocation
2420 * is set to what is currently consumed instead (consumed bandwidth
2421 * cannot be taken away by CM). The actual new values are returned in
2422 * @upstream_bw and @downstream_bw.
2423 *
2424 * Return: %0 on success, negative errno otherwise.
2425 */
2426int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2427 int *downstream_bw)
2428{
2429 int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2430
2431 ret = usb4_usb3_port_set_cm_request(port);
2432 if (ret)
2433 return ret;
2434
2435 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2436 &consumed_down);
2437 if (ret)
2438 goto err_request;
2439
2440 /* Don't allow it go lower than what is consumed */
2441 allocate_up = max(*upstream_bw, consumed_up);
2442 allocate_down = max(*downstream_bw, consumed_down);
2443
2444 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2445 allocate_down);
2446 if (ret)
2447 goto err_request;
2448
2449 *upstream_bw = allocate_up;
2450 *downstream_bw = allocate_down;
2451
2452err_request:
2453 usb4_usb3_port_clear_cm_request(port);
2454 return ret;
2455}
2456
2457/**
2458 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2459 * @port: USB3 adapter port
2460 * @upstream_bw: New allocated upstream bandwidth
2461 * @downstream_bw: New allocated downstream bandwidth
2462 *
2463 * Releases USB3 allocated bandwidth down to what is actually consumed.
2464 * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2465 *
2466 * Return: %0 on success, negative errno otherwise.
2467 */
2468int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2469 int *downstream_bw)
2470{
2471 int ret, consumed_up, consumed_down;
2472
2473 ret = usb4_usb3_port_set_cm_request(port);
2474 if (ret)
2475 return ret;
2476
2477 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2478 &consumed_down);
2479 if (ret)
2480 goto err_request;
2481
2482 /*
2483 * Always keep 900 Mb/s to make sure xHCI has at least some
2484 * bandwidth available for isochronous traffic.
2485 */
2486 if (consumed_up < 900)
2487 consumed_up = 900;
2488 if (consumed_down < 900)
2489 consumed_down = 900;
2490
2491 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2492 consumed_down);
2493 if (ret)
2494 goto err_request;
2495
2496 *upstream_bw = consumed_up;
2497 *downstream_bw = consumed_down;
2498
2499err_request:
2500 usb4_usb3_port_clear_cm_request(port);
2501 return ret;
2502}
2503
2504static bool is_usb4_dpin(const struct tb_port *port)
2505{
2506 if (!tb_port_is_dpin(port))
2507 return false;
2508 if (!tb_switch_is_usb4(port->sw))
2509 return false;
2510 return true;
2511}
2512
2513/**
2514 * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2515 * @port: DP IN adapter
2516 * @cm_id: CM ID to assign
2517 *
2518 * Sets CM ID for the @port.
2519 *
2520 * Return:
2521 * * %0 - On success.
2522 * * %-EOPNOTSUPP - If the @port does not support this.
2523 * * Negative errno - Another error occurred.
2524 */
2525int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2526{
2527 u32 val;
2528 int ret;
2529
2530 if (!is_usb4_dpin(port))
2531 return -EOPNOTSUPP;
2532
2533 ret = tb_port_read(port, &val, TB_CFG_PORT,
2534 port->cap_adap + ADP_DP_CS_2, 1);
2535 if (ret)
2536 return ret;
2537
2538 val &= ~ADP_DP_CS_2_CM_ID_MASK;
2539 val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2540
2541 return tb_port_write(port, &val, TB_CFG_PORT,
2542 port->cap_adap + ADP_DP_CS_2, 1);
2543}
2544
2545/**
2546 * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2547 * supported
2548 * @port: DP IN adapter to check
2549 *
2550 * Can be called to any DP IN adapter.
2551 *
2552 * Return: %true if the adapter supports USB4 bandwidth allocation mode,
2553 * %false otherwise.
2554 */
2555bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2556{
2557 int ret;
2558 u32 val;
2559
2560 if (!is_usb4_dpin(port))
2561 return false;
2562
2563 ret = tb_port_read(port, &val, TB_CFG_PORT,
2564 port->cap_adap + DP_LOCAL_CAP, 1);
2565 if (ret)
2566 return false;
2567
2568 return !!(val & DP_COMMON_CAP_BW_MODE);
2569}
2570
2571/**
2572 * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2573 * enabled
2574 * @port: DP IN adapter to check
2575 *
2576 * Can be called to any DP IN adapter.
2577 *
2578 * Return: %true if the bandwidth allocation mode has been enabled,
2579 * %false otherwise.
2580 */
2581bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2582{
2583 int ret;
2584 u32 val;
2585
2586 if (!is_usb4_dpin(port))
2587 return false;
2588
2589 ret = tb_port_read(port, &val, TB_CFG_PORT,
2590 port->cap_adap + ADP_DP_CS_8, 1);
2591 if (ret)
2592 return false;
2593
2594 return !!(val & ADP_DP_CS_8_DPME);
2595}
2596
2597/**
2598 * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2599 * bandwidth allocation mode
2600 * @port: DP IN adapter
2601 * @supported: Does the CM support bandwidth allocation mode
2602 *
2603 * Can be called to any DP IN adapter. Sets or clears the CM support bit
2604 * of the DP IN adapter.
2605 *
2606 * * Return:
2607 * * %0 - On success.
2608 * * %-EOPNOTSUPP - If the passed IN adapter does not support this.
2609 * * Negative errno - Another error occurred.
2610 */
2611int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2612 bool supported)
2613{
2614 u32 val;
2615 int ret;
2616
2617 if (!is_usb4_dpin(port))
2618 return -EOPNOTSUPP;
2619
2620 ret = tb_port_read(port, &val, TB_CFG_PORT,
2621 port->cap_adap + ADP_DP_CS_2, 1);
2622 if (ret)
2623 return ret;
2624
2625 if (supported)
2626 val |= ADP_DP_CS_2_CMMS;
2627 else
2628 val &= ~ADP_DP_CS_2_CMMS;
2629
2630 return tb_port_write(port, &val, TB_CFG_PORT,
2631 port->cap_adap + ADP_DP_CS_2, 1);
2632}
2633
2634/**
2635 * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2636 * @port: DP IN adapter
2637 *
2638 * Reads bandwidth allocation Group ID from the DP IN adapter and
2639 * returns it.
2640 *
2641 * Return:
2642 * * Group ID assigned to adapter @port.
2643 * * %-EOPNOTSUPP - If adapter does not support setting GROUP_ID.
2644 * * Negative errno - Another error occurred.
2645 */
2646int usb4_dp_port_group_id(struct tb_port *port)
2647{
2648 u32 val;
2649 int ret;
2650
2651 if (!is_usb4_dpin(port))
2652 return -EOPNOTSUPP;
2653
2654 ret = tb_port_read(port, &val, TB_CFG_PORT,
2655 port->cap_adap + ADP_DP_CS_2, 1);
2656 if (ret)
2657 return ret;
2658
2659 return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2660}
2661
2662/**
2663 * usb4_dp_port_set_group_id() - Set adapter Group ID
2664 * @port: DP IN adapter
2665 * @group_id: Group ID for the adapter
2666 *
2667 * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2668 *
2669 * Return:
2670 * * %0 - On success.
2671 * * %-EOPNOTSUPP - If the adapter does not support this.
2672 * * Negative errno - Another error occurred.
2673 */
2674int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2675{
2676 u32 val;
2677 int ret;
2678
2679 if (!is_usb4_dpin(port))
2680 return -EOPNOTSUPP;
2681
2682 ret = tb_port_read(port, &val, TB_CFG_PORT,
2683 port->cap_adap + ADP_DP_CS_2, 1);
2684 if (ret)
2685 return ret;
2686
2687 val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2688 val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2689
2690 return tb_port_write(port, &val, TB_CFG_PORT,
2691 port->cap_adap + ADP_DP_CS_2, 1);
2692}
2693
2694/**
2695 * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2696 * @port: DP IN adapter
2697 * @rate: Non-reduced rate in Mb/s is placed here
2698 * @lanes: Non-reduced lanes are placed here
2699 *
2700 * Reads the non-reduced rate and lanes from the DP IN adapter.
2701 *
2702 * Return:
2703 * * %0 - On success.
2704 * * %-EOPNOTSUPP - If the adapter does not support this.
2705 * * Negative errno - Another error occurred.
2706 */
2707int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2708{
2709 u32 val, tmp;
2710 int ret;
2711
2712 if (!is_usb4_dpin(port))
2713 return -EOPNOTSUPP;
2714
2715 ret = tb_port_read(port, &val, TB_CFG_PORT,
2716 port->cap_adap + ADP_DP_CS_2, 1);
2717 if (ret)
2718 return ret;
2719
2720 tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2721 switch (tmp) {
2722 case DP_COMMON_CAP_RATE_RBR:
2723 *rate = 1620;
2724 break;
2725 case DP_COMMON_CAP_RATE_HBR:
2726 *rate = 2700;
2727 break;
2728 case DP_COMMON_CAP_RATE_HBR2:
2729 *rate = 5400;
2730 break;
2731 case DP_COMMON_CAP_RATE_HBR3:
2732 *rate = 8100;
2733 break;
2734 }
2735
2736 tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2737 switch (tmp) {
2738 case DP_COMMON_CAP_1_LANE:
2739 *lanes = 1;
2740 break;
2741 case DP_COMMON_CAP_2_LANES:
2742 *lanes = 2;
2743 break;
2744 case DP_COMMON_CAP_4_LANES:
2745 *lanes = 4;
2746 break;
2747 }
2748
2749 return 0;
2750}
2751
2752/**
2753 * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2754 * @port: DP IN adapter
2755 * @rate: Non-reduced rate in Mb/s
2756 * @lanes: Non-reduced lanes
2757 *
2758 * Before the capabilities reduction, this function can be used to set
2759 * the non-reduced values for the DP IN adapter.
2760 *
2761 * Return:
2762 * * %0 - On success.
2763 * * %-EOPNOTSUPP - If the adapter does not support this.
2764 * * Negative errno - Another error occurred.
2765 */
2766int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2767{
2768 u32 val;
2769 int ret;
2770
2771 if (!is_usb4_dpin(port))
2772 return -EOPNOTSUPP;
2773
2774 ret = tb_port_read(port, &val, TB_CFG_PORT,
2775 port->cap_adap + ADP_DP_CS_2, 1);
2776 if (ret)
2777 return ret;
2778
2779 val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2780
2781 switch (rate) {
2782 case 1620:
2783 break;
2784 case 2700:
2785 val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2786 & ADP_DP_CS_2_NRD_MLR_MASK;
2787 break;
2788 case 5400:
2789 val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2790 & ADP_DP_CS_2_NRD_MLR_MASK;
2791 break;
2792 case 8100:
2793 val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2794 & ADP_DP_CS_2_NRD_MLR_MASK;
2795 break;
2796 default:
2797 return -EINVAL;
2798 }
2799
2800 val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2801
2802 switch (lanes) {
2803 case 1:
2804 break;
2805 case 2:
2806 val |= DP_COMMON_CAP_2_LANES;
2807 break;
2808 case 4:
2809 val |= DP_COMMON_CAP_4_LANES;
2810 break;
2811 default:
2812 return -EINVAL;
2813 }
2814
2815 return tb_port_write(port, &val, TB_CFG_PORT,
2816 port->cap_adap + ADP_DP_CS_2, 1);
2817}
2818
2819/**
2820 * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2821 * @port: DP IN adapter
2822 *
2823 * Reads the programmed granularity from @port.
2824 *
2825 * Return:
2826 * * Granularity value of a @port.
2827 * * %-EOPNOTSUPP - If the DP IN adapter does not support bandwidth
2828 * allocation mode.
2829 * * Negative errno - Another error occurred.
2830 */
2831int usb4_dp_port_granularity(struct tb_port *port)
2832{
2833 u32 val;
2834 int ret;
2835
2836 if (!is_usb4_dpin(port))
2837 return -EOPNOTSUPP;
2838
2839 ret = tb_port_read(port, &val, TB_CFG_PORT,
2840 port->cap_adap + ADP_DP_CS_2, 1);
2841 if (ret)
2842 return ret;
2843
2844 val &= ADP_DP_CS_2_GR_MASK;
2845 val >>= ADP_DP_CS_2_GR_SHIFT;
2846
2847 switch (val) {
2848 case ADP_DP_CS_2_GR_0_25G:
2849 return 250;
2850 case ADP_DP_CS_2_GR_0_5G:
2851 return 500;
2852 case ADP_DP_CS_2_GR_1G:
2853 return 1000;
2854 }
2855
2856 return -EINVAL;
2857}
2858
2859/**
2860 * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2861 * @port: DP IN adapter
2862 * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2863 *
2864 * Sets the granularity used with the estimated, allocated and requested
2865 * bandwidth.
2866 *
2867 * Return:
2868 * * %0 - On success.
2869 * * %-EOPNOTSUPP - If the adapter does not support this.
2870 * * Negative errno - Another error occurred.
2871 */
2872int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2873{
2874 u32 val;
2875 int ret;
2876
2877 if (!is_usb4_dpin(port))
2878 return -EOPNOTSUPP;
2879
2880 ret = tb_port_read(port, &val, TB_CFG_PORT,
2881 port->cap_adap + ADP_DP_CS_2, 1);
2882 if (ret)
2883 return ret;
2884
2885 val &= ~ADP_DP_CS_2_GR_MASK;
2886
2887 switch (granularity) {
2888 case 250:
2889 val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2890 break;
2891 case 500:
2892 val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2893 break;
2894 case 1000:
2895 val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2896 break;
2897 default:
2898 return -EINVAL;
2899 }
2900
2901 return tb_port_write(port, &val, TB_CFG_PORT,
2902 port->cap_adap + ADP_DP_CS_2, 1);
2903}
2904
2905/**
2906 * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2907 * @port: DP IN adapter
2908 * @bw: Estimated bandwidth in Mb/s.
2909 *
2910 * Sets the estimated bandwidth to @bw. Set the granularity by calling
2911 * usb4_dp_port_set_granularity() before calling this. The @bw is rounded
2912 * down to the closest granularity multiplier.
2913 *
2914 * Return:
2915 * * %0 - On success.
2916 * * %-EOPNOTSUPP - If the adapter does not support this.
2917 * * Negative errno - Another error occurred.
2918 */
2919int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2920{
2921 u32 val, granularity;
2922 int ret;
2923
2924 if (!is_usb4_dpin(port))
2925 return -EOPNOTSUPP;
2926
2927 ret = usb4_dp_port_granularity(port);
2928 if (ret < 0)
2929 return ret;
2930 granularity = ret;
2931
2932 ret = tb_port_read(port, &val, TB_CFG_PORT,
2933 port->cap_adap + ADP_DP_CS_2, 1);
2934 if (ret)
2935 return ret;
2936
2937 val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2938 val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2939
2940 return tb_port_write(port, &val, TB_CFG_PORT,
2941 port->cap_adap + ADP_DP_CS_2, 1);
2942}
2943
2944/**
2945 * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2946 * @port: DP IN adapter
2947 *
2948 * Reads the allocated bandwidth for @port in Mb/s (taking into account
2949 * the programmed granularity).
2950 *
2951 * Return: Allocated bandwidth in Mb/s or negative errno in case of an error.
2952 */
2953int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2954{
2955 u32 val, granularity;
2956 int ret;
2957
2958 if (!is_usb4_dpin(port))
2959 return -EOPNOTSUPP;
2960
2961 ret = usb4_dp_port_granularity(port);
2962 if (ret < 0)
2963 return ret;
2964 granularity = ret;
2965
2966 ret = tb_port_read(port, &val, TB_CFG_PORT,
2967 port->cap_adap + DP_STATUS, 1);
2968 if (ret)
2969 return ret;
2970
2971 val &= DP_STATUS_ALLOCATED_BW_MASK;
2972 val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2973
2974 return val * granularity;
2975}
2976
2977static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2978{
2979 u32 val;
2980 int ret;
2981
2982 ret = tb_port_read(port, &val, TB_CFG_PORT,
2983 port->cap_adap + ADP_DP_CS_2, 1);
2984 if (ret)
2985 return ret;
2986
2987 if (ack)
2988 val |= ADP_DP_CS_2_CA;
2989 else
2990 val &= ~ADP_DP_CS_2_CA;
2991
2992 return tb_port_write(port, &val, TB_CFG_PORT,
2993 port->cap_adap + ADP_DP_CS_2, 1);
2994}
2995
2996static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2997{
2998 return __usb4_dp_port_set_cm_ack(port, true);
2999}
3000
3001static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
3002 int timeout_msec)
3003{
3004 ktime_t end;
3005 u32 val;
3006 int ret;
3007
3008 ret = __usb4_dp_port_set_cm_ack(port, false);
3009 if (ret)
3010 return ret;
3011
3012 end = ktime_add_ms(ktime_get(), timeout_msec);
3013 do {
3014 ret = tb_port_read(port, &val, TB_CFG_PORT,
3015 port->cap_adap + ADP_DP_CS_8, 1);
3016 if (ret)
3017 return ret;
3018
3019 if (!(val & ADP_DP_CS_8_DR))
3020 break;
3021
3022 usleep_range(50, 100);
3023 } while (ktime_before(ktime_get(), end));
3024
3025 if (val & ADP_DP_CS_8_DR) {
3026 tb_port_warn(port, "timeout waiting for DPTX request to clear\n");
3027 return -ETIMEDOUT;
3028 }
3029
3030 ret = tb_port_read(port, &val, TB_CFG_PORT,
3031 port->cap_adap + ADP_DP_CS_2, 1);
3032 if (ret)
3033 return ret;
3034
3035 val &= ~ADP_DP_CS_2_CA;
3036 return tb_port_write(port, &val, TB_CFG_PORT,
3037 port->cap_adap + ADP_DP_CS_2, 1);
3038}
3039
3040/**
3041 * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
3042 * @port: DP IN adapter
3043 * @bw: New allocated bandwidth in Mb/s
3044 *
3045 * Communicates the new allocated bandwidth with the DPCD (graphics
3046 * driver). Takes into account the programmed granularity.
3047 *
3048 * Return: %0 on success, negative errno otherwise.
3049 */
3050int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
3051{
3052 u32 val, granularity;
3053 int ret;
3054
3055 if (!is_usb4_dpin(port))
3056 return -EOPNOTSUPP;
3057
3058 ret = usb4_dp_port_granularity(port);
3059 if (ret < 0)
3060 return ret;
3061 granularity = ret;
3062
3063 ret = tb_port_read(port, &val, TB_CFG_PORT,
3064 port->cap_adap + DP_STATUS, 1);
3065 if (ret)
3066 return ret;
3067
3068 val &= ~DP_STATUS_ALLOCATED_BW_MASK;
3069 val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
3070
3071 ret = tb_port_write(port, &val, TB_CFG_PORT,
3072 port->cap_adap + DP_STATUS, 1);
3073 if (ret)
3074 return ret;
3075
3076 ret = usb4_dp_port_set_cm_ack(port);
3077 if (ret)
3078 return ret;
3079
3080 return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
3081}
3082
3083/**
3084 * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
3085 * @port: DP IN adapter
3086 *
3087 * Reads the DPCD (graphics driver) requested bandwidth and returns it
3088 * in Mb/s. Takes the programmed granularity into account.
3089 *
3090 * Return:
3091 * * Requested bandwidth in Mb/s - On success.
3092 * * %-EOPNOTSUPP - If the adapter does not support bandwidth allocation
3093 * mode.
3094 * * %ENODATA - If there is no active bandwidth request from the graphics
3095 * driver.
3096 * * Negative errno - On failure.
3097 */
3098int usb4_dp_port_requested_bandwidth(struct tb_port *port)
3099{
3100 u32 val, granularity;
3101 int ret;
3102
3103 if (!is_usb4_dpin(port))
3104 return -EOPNOTSUPP;
3105
3106 ret = usb4_dp_port_granularity(port);
3107 if (ret < 0)
3108 return ret;
3109 granularity = ret;
3110
3111 ret = tb_port_read(port, &val, TB_CFG_PORT,
3112 port->cap_adap + ADP_DP_CS_8, 1);
3113 if (ret)
3114 return ret;
3115
3116 if (!(val & ADP_DP_CS_8_DR))
3117 return -ENODATA;
3118
3119 return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
3120}
3121
3122/**
3123 * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
3124 * @port: PCIe adapter
3125 * @enable: Enable/disable extended encapsulation
3126 *
3127 * Enables or disables extended encapsulation used in PCIe tunneling. Caller
3128 * needs to make sure both adapters support this before enabling.
3129 *
3130 * Return: %0 on success, negative errno otherwise.
3131 */
3132int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
3133{
3134 u32 val;
3135 int ret;
3136
3137 if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
3138 return -EINVAL;
3139
3140 ret = tb_port_read(port, &val, TB_CFG_PORT,
3141 port->cap_adap + ADP_PCIE_CS_1, 1);
3142 if (ret)
3143 return ret;
3144
3145 if (enable)
3146 val |= ADP_PCIE_CS_1_EE;
3147 else
3148 val &= ~ADP_PCIE_CS_1_EE;
3149
3150 return tb_port_write(port, &val, TB_CFG_PORT,
3151 port->cap_adap + ADP_PCIE_CS_1, 1);
3152}
3153
3154/**
3155 * usb4_pci_port_ltssm_state() - Read PCIe adapter LTSSM state
3156 * @port: PCIe adapter
3157 *
3158 * Return:
3159 * * LTSSM state of @port.
3160 * * Negative errno - On failure.
3161 */
3162int usb4_pci_port_ltssm_state(struct tb_port *port)
3163{
3164 u32 val;
3165 int ret;
3166
3167 if (!tb_port_is_pcie_down(port) && !tb_port_is_pcie_up(port))
3168 return -EINVAL;
3169
3170 ret = tb_port_read(port, &val, TB_CFG_PORT,
3171 port->cap_adap + ADP_PCIE_CS_0, 1);
3172 if (ret)
3173 return ret;
3174
3175 return FIELD_GET(ADP_PCIE_CS_0_LTSSM_MASK, val);
3176}