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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
4 *
5 * Copyright (C) 1997 Eddie C. Dost ([email protected])
6 * Copyright (C) 1998-1999 Pete Zaitcev ([email protected])
7 *
8 * This is mainly a variation of 8250.c, credits go to authors mentioned
9 * therein. In fact this driver should be merged into the generic 8250.c
10 * infrastructure perhaps using a 8250_sparc.c module.
11 *
12 * Fixed to use tty_get_baud_rate().
13 * Theodore Ts'o <[email protected]>, 2001-Oct-12
14 *
15 * Converted to new 2.5.x UART layer.
16 * David S. Miller ([email protected]), 2002-Jul-29
17 */
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/spinlock.h>
22#include <linux/errno.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/major.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/ioport.h>
29#include <linux/circ_buf.h>
30#include <linux/serial.h>
31#include <linux/sysrq.h>
32#include <linux/console.h>
33#include <linux/slab.h>
34#ifdef CONFIG_SERIO
35#include <linux/serio.h>
36#endif
37#include <linux/serial_reg.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/of.h>
41#include <linux/platform_device.h>
42
43#include <linux/io.h>
44#include <asm/irq.h>
45#include <asm/setup.h>
46
47#include <linux/serial_core.h>
48#include <linux/sunserialcore.h>
49
50/* We are on a NS PC87303 clocked with 24.0 MHz, which results
51 * in a UART clock of 1.8462 MHz.
52 */
53#define SU_BASE_BAUD (1846200 / 16)
54
55enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
56static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
57
58struct serial_uart_config {
59 char *name;
60 int dfl_xmit_fifo_size;
61 int flags;
62};
63
64/*
65 * Here we define the default xmit fifo size used for each type of UART.
66 */
67static const struct serial_uart_config uart_config[] = {
68 { "unknown", 1, 0 },
69 { "8250", 1, 0 },
70 { "16450", 1, 0 },
71 { "16550", 1, 0 },
72 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
73 { "Cirrus", 1, 0 },
74 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
75 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
76 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
77 { "Startech", 1, 0 },
78 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
79 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
80 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
81 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
82};
83
84struct uart_sunsu_port {
85 struct uart_port port;
86 unsigned char acr;
87 unsigned char ier;
88 unsigned short rev;
89 unsigned char lcr;
90 unsigned int lsr_break_flag;
91 unsigned int cflag;
92
93 /* Probing information. */
94 enum su_type su_type;
95 unsigned int type_probed; /* XXX Stupid */
96 unsigned long reg_size;
97
98#ifdef CONFIG_SERIO
99 struct serio serio;
100 int serio_open;
101#endif
102};
103
104static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
105{
106 offset <<= up->port.regshift;
107
108 switch (up->port.iotype) {
109 case UPIO_HUB6:
110 outb(up->port.hub6 - 1 + offset, up->port.iobase);
111 return inb(up->port.iobase + 1);
112
113 case UPIO_MEM:
114 return readb(up->port.membase + offset);
115
116 default:
117 return inb(up->port.iobase + offset);
118 }
119}
120
121static void serial_out(struct uart_sunsu_port *up, int offset, int value)
122{
123#ifndef CONFIG_SPARC64
124 /*
125 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
126 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
127 * gate outputs a logical one. Since we use level triggered interrupts
128 * we have lockup and watchdog reset. We cannot mask IRQ because
129 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
130 * This problem is similar to what Alpha people suffer, see
131 * 8250_alpha.c.
132 */
133 if (offset == UART_MCR)
134 value |= UART_MCR_OUT2;
135#endif
136 offset <<= up->port.regshift;
137
138 switch (up->port.iotype) {
139 case UPIO_HUB6:
140 outb(up->port.hub6 - 1 + offset, up->port.iobase);
141 outb(value, up->port.iobase + 1);
142 break;
143
144 case UPIO_MEM:
145 writeb(value, up->port.membase + offset);
146 break;
147
148 default:
149 outb(value, up->port.iobase + offset);
150 }
151}
152
153/*
154 * For the 16C950
155 */
156static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
157{
158 serial_out(up, UART_SCR, offset);
159 serial_out(up, UART_ICR, value);
160}
161
162#ifdef CONFIG_SERIAL_8250_RSA
163/*
164 * Attempts to turn on the RSA FIFO. Returns zero on failure.
165 * We set the port uart clock rate if we succeed.
166 */
167static int __enable_rsa(struct uart_sunsu_port *up)
168{
169 unsigned char mode;
170 int result;
171
172 mode = serial_in(up, UART_RSA_MSR);
173 result = mode & UART_RSA_MSR_FIFO;
174
175 if (!result) {
176 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
177 mode = serial_in(up, UART_RSA_MSR);
178 result = mode & UART_RSA_MSR_FIFO;
179 }
180
181 if (result)
182 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
183
184 return result;
185}
186
187static void enable_rsa(struct uart_sunsu_port *up)
188{
189 if (up->port.type == PORT_RSA) {
190 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
191 uart_port_lock_irq(&up->port);
192 __enable_rsa(up);
193 uart_port_unlock_irq(&up->port);
194 }
195 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
196 serial_out(up, UART_RSA_FRR, 0);
197 }
198}
199
200/*
201 * Attempts to turn off the RSA FIFO. Returns zero on failure.
202 * It is unknown why interrupts were disabled in here. However,
203 * the caller is expected to preserve this behaviour by grabbing
204 * the spinlock before calling this function.
205 */
206static void disable_rsa(struct uart_sunsu_port *up)
207{
208 unsigned char mode;
209 int result;
210
211 if (up->port.type == PORT_RSA &&
212 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
213 uart_port_lock_irq(&up->port);
214
215 mode = serial_in(up, UART_RSA_MSR);
216 result = !(mode & UART_RSA_MSR_FIFO);
217
218 if (!result) {
219 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
220 mode = serial_in(up, UART_RSA_MSR);
221 result = !(mode & UART_RSA_MSR_FIFO);
222 }
223
224 if (result)
225 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
226 uart_port_unlock_irq(&up->port);
227 }
228}
229#endif /* CONFIG_SERIAL_8250_RSA */
230
231static inline void __stop_tx(struct uart_sunsu_port *p)
232{
233 if (p->ier & UART_IER_THRI) {
234 p->ier &= ~UART_IER_THRI;
235 serial_out(p, UART_IER, p->ier);
236 }
237}
238
239static void sunsu_stop_tx(struct uart_port *port)
240{
241 struct uart_sunsu_port *up =
242 container_of(port, struct uart_sunsu_port, port);
243
244 __stop_tx(up);
245
246 /*
247 * We really want to stop the transmitter from sending.
248 */
249 if (up->port.type == PORT_16C950) {
250 up->acr |= UART_ACR_TXDIS;
251 serial_icr_write(up, UART_ACR, up->acr);
252 }
253}
254
255static void sunsu_start_tx(struct uart_port *port)
256{
257 struct uart_sunsu_port *up =
258 container_of(port, struct uart_sunsu_port, port);
259
260 if (!(up->ier & UART_IER_THRI)) {
261 up->ier |= UART_IER_THRI;
262 serial_out(up, UART_IER, up->ier);
263 }
264
265 /*
266 * Re-enable the transmitter if we disabled it.
267 */
268 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
269 up->acr &= ~UART_ACR_TXDIS;
270 serial_icr_write(up, UART_ACR, up->acr);
271 }
272}
273
274static void sunsu_stop_rx(struct uart_port *port)
275{
276 struct uart_sunsu_port *up =
277 container_of(port, struct uart_sunsu_port, port);
278
279 up->ier &= ~UART_IER_RLSI;
280 up->port.read_status_mask &= ~UART_LSR_DR;
281 serial_out(up, UART_IER, up->ier);
282}
283
284static void sunsu_enable_ms(struct uart_port *port)
285{
286 struct uart_sunsu_port *up =
287 container_of(port, struct uart_sunsu_port, port);
288 unsigned long flags;
289
290 uart_port_lock_irqsave(&up->port, &flags);
291 up->ier |= UART_IER_MSI;
292 serial_out(up, UART_IER, up->ier);
293 uart_port_unlock_irqrestore(&up->port, flags);
294}
295
296static void
297receive_chars(struct uart_sunsu_port *up, unsigned char *status)
298{
299 struct tty_port *port = &up->port.state->port;
300 unsigned char ch, flag;
301 int max_count = 256;
302 int saw_console_brk = 0;
303
304 do {
305 ch = serial_in(up, UART_RX);
306 flag = TTY_NORMAL;
307 up->port.icount.rx++;
308
309 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
310 UART_LSR_FE | UART_LSR_OE))) {
311 /*
312 * For statistics only
313 */
314 if (*status & UART_LSR_BI) {
315 *status &= ~(UART_LSR_FE | UART_LSR_PE);
316 up->port.icount.brk++;
317 if (up->port.cons != NULL &&
318 up->port.line == up->port.cons->index)
319 saw_console_brk = 1;
320 /*
321 * We do the SysRQ and SAK checking
322 * here because otherwise the break
323 * may get masked by ignore_status_mask
324 * or read_status_mask.
325 */
326 if (uart_handle_break(&up->port))
327 goto ignore_char;
328 } else if (*status & UART_LSR_PE)
329 up->port.icount.parity++;
330 else if (*status & UART_LSR_FE)
331 up->port.icount.frame++;
332 if (*status & UART_LSR_OE)
333 up->port.icount.overrun++;
334
335 /*
336 * Mask off conditions which should be ingored.
337 */
338 *status &= up->port.read_status_mask;
339
340 if (up->port.cons != NULL &&
341 up->port.line == up->port.cons->index) {
342 /* Recover the break flag from console xmit */
343 *status |= up->lsr_break_flag;
344 up->lsr_break_flag = 0;
345 }
346
347 if (*status & UART_LSR_BI) {
348 flag = TTY_BREAK;
349 } else if (*status & UART_LSR_PE)
350 flag = TTY_PARITY;
351 else if (*status & UART_LSR_FE)
352 flag = TTY_FRAME;
353 }
354 if (uart_handle_sysrq_char(&up->port, ch))
355 goto ignore_char;
356 if ((*status & up->port.ignore_status_mask) == 0)
357 tty_insert_flip_char(port, ch, flag);
358 if (*status & UART_LSR_OE)
359 /*
360 * Overrun is special, since it's reported
361 * immediately, and doesn't affect the current
362 * character.
363 */
364 tty_insert_flip_char(port, 0, TTY_OVERRUN);
365 ignore_char:
366 *status = serial_in(up, UART_LSR);
367 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
368
369 if (saw_console_brk)
370 sun_do_break();
371}
372
373static void transmit_chars(struct uart_sunsu_port *up)
374{
375 struct tty_port *tport = &up->port.state->port;
376 unsigned char ch;
377 int count;
378
379 if (up->port.x_char) {
380 serial_out(up, UART_TX, up->port.x_char);
381 up->port.icount.tx++;
382 up->port.x_char = 0;
383 return;
384 }
385 if (uart_tx_stopped(&up->port)) {
386 sunsu_stop_tx(&up->port);
387 return;
388 }
389 if (kfifo_is_empty(&tport->xmit_fifo)) {
390 __stop_tx(up);
391 return;
392 }
393
394 count = up->port.fifosize;
395 do {
396 if (!uart_fifo_get(&up->port, &ch))
397 break;
398
399 serial_out(up, UART_TX, ch);
400 } while (--count > 0);
401
402 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
403 uart_write_wakeup(&up->port);
404
405 if (kfifo_is_empty(&tport->xmit_fifo))
406 __stop_tx(up);
407}
408
409static void check_modem_status(struct uart_sunsu_port *up)
410{
411 int status;
412
413 status = serial_in(up, UART_MSR);
414
415 if ((status & UART_MSR_ANY_DELTA) == 0)
416 return;
417
418 if (status & UART_MSR_TERI)
419 up->port.icount.rng++;
420 if (status & UART_MSR_DDSR)
421 up->port.icount.dsr++;
422 if (status & UART_MSR_DDCD)
423 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
424 if (status & UART_MSR_DCTS)
425 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
426
427 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
428}
429
430static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id)
431{
432 struct uart_sunsu_port *up = dev_id;
433 unsigned long flags;
434 unsigned char status;
435
436 uart_port_lock_irqsave(&up->port, &flags);
437
438 do {
439 status = serial_in(up, UART_LSR);
440 if (status & UART_LSR_DR)
441 receive_chars(up, &status);
442 check_modem_status(up);
443 if (status & UART_LSR_THRE)
444 transmit_chars(up);
445
446 tty_flip_buffer_push(&up->port.state->port);
447
448 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
449
450 uart_port_unlock_irqrestore(&up->port, flags);
451
452 return IRQ_HANDLED;
453}
454
455/* Separate interrupt handling path for keyboard/mouse ports. */
456
457static void
458sunsu_change_speed(struct uart_port *port, unsigned int cflag,
459 unsigned int iflag, unsigned int quot);
460
461static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
462{
463 unsigned int cur_cflag = up->cflag;
464 int quot, new_baud;
465
466 up->cflag &= ~CBAUD;
467 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
468
469 quot = up->port.uartclk / (16 * new_baud);
470
471 sunsu_change_speed(&up->port, up->cflag, 0, quot);
472}
473
474static void receive_kbd_ms_chars(struct uart_sunsu_port *up, int is_break)
475{
476 do {
477 unsigned char ch = serial_in(up, UART_RX);
478
479 /* Stop-A is handled by drivers/char/keyboard.c now. */
480 if (up->su_type == SU_PORT_KBD) {
481#ifdef CONFIG_SERIO
482 serio_interrupt(&up->serio, ch, 0);
483#endif
484 } else if (up->su_type == SU_PORT_MS) {
485 int ret = suncore_mouse_baud_detection(ch, is_break);
486
487 switch (ret) {
488 case 2:
489 sunsu_change_mouse_baud(up);
490 fallthrough;
491 case 1:
492 break;
493
494 case 0:
495#ifdef CONFIG_SERIO
496 serio_interrupt(&up->serio, ch, 0);
497#endif
498 break;
499 }
500 }
501 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
502}
503
504static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id)
505{
506 struct uart_sunsu_port *up = dev_id;
507
508 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
509 unsigned char status = serial_in(up, UART_LSR);
510
511 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
512 receive_kbd_ms_chars(up, (status & UART_LSR_BI) != 0);
513 }
514
515 return IRQ_HANDLED;
516}
517
518static unsigned int sunsu_tx_empty(struct uart_port *port)
519{
520 struct uart_sunsu_port *up =
521 container_of(port, struct uart_sunsu_port, port);
522 unsigned long flags;
523 unsigned int ret;
524
525 uart_port_lock_irqsave(&up->port, &flags);
526 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
527 uart_port_unlock_irqrestore(&up->port, flags);
528
529 return ret;
530}
531
532static unsigned int sunsu_get_mctrl(struct uart_port *port)
533{
534 struct uart_sunsu_port *up =
535 container_of(port, struct uart_sunsu_port, port);
536 unsigned char status;
537 unsigned int ret;
538
539 status = serial_in(up, UART_MSR);
540
541 ret = 0;
542 if (status & UART_MSR_DCD)
543 ret |= TIOCM_CAR;
544 if (status & UART_MSR_RI)
545 ret |= TIOCM_RNG;
546 if (status & UART_MSR_DSR)
547 ret |= TIOCM_DSR;
548 if (status & UART_MSR_CTS)
549 ret |= TIOCM_CTS;
550 return ret;
551}
552
553static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
554{
555 struct uart_sunsu_port *up =
556 container_of(port, struct uart_sunsu_port, port);
557 unsigned char mcr = 0;
558
559 if (mctrl & TIOCM_RTS)
560 mcr |= UART_MCR_RTS;
561 if (mctrl & TIOCM_DTR)
562 mcr |= UART_MCR_DTR;
563 if (mctrl & TIOCM_OUT1)
564 mcr |= UART_MCR_OUT1;
565 if (mctrl & TIOCM_OUT2)
566 mcr |= UART_MCR_OUT2;
567 if (mctrl & TIOCM_LOOP)
568 mcr |= UART_MCR_LOOP;
569
570 serial_out(up, UART_MCR, mcr);
571}
572
573static void sunsu_break_ctl(struct uart_port *port, int break_state)
574{
575 struct uart_sunsu_port *up =
576 container_of(port, struct uart_sunsu_port, port);
577 unsigned long flags;
578
579 uart_port_lock_irqsave(&up->port, &flags);
580 if (break_state == -1)
581 up->lcr |= UART_LCR_SBC;
582 else
583 up->lcr &= ~UART_LCR_SBC;
584 serial_out(up, UART_LCR, up->lcr);
585 uart_port_unlock_irqrestore(&up->port, flags);
586}
587
588static int sunsu_startup(struct uart_port *port)
589{
590 struct uart_sunsu_port *up =
591 container_of(port, struct uart_sunsu_port, port);
592 unsigned long flags;
593 int retval;
594
595 if (up->port.type == PORT_16C950) {
596 /* Wake up and initialize UART */
597 up->acr = 0;
598 serial_out(up, UART_LCR, 0xBF);
599 serial_out(up, UART_EFR, UART_EFR_ECB);
600 serial_out(up, UART_IER, 0);
601 serial_out(up, UART_LCR, 0);
602 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
603 serial_out(up, UART_LCR, 0xBF);
604 serial_out(up, UART_EFR, UART_EFR_ECB);
605 serial_out(up, UART_LCR, 0);
606 }
607
608#ifdef CONFIG_SERIAL_8250_RSA
609 /*
610 * If this is an RSA port, see if we can kick it up to the
611 * higher speed clock.
612 */
613 enable_rsa(up);
614#endif
615
616 /*
617 * Clear the FIFO buffers and disable them.
618 * (they will be reenabled in set_termios())
619 */
620 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
621 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
622 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
623 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
624 serial_out(up, UART_FCR, 0);
625 }
626
627 /*
628 * Clear the interrupt registers.
629 */
630 (void) serial_in(up, UART_LSR);
631 (void) serial_in(up, UART_RX);
632 (void) serial_in(up, UART_IIR);
633 (void) serial_in(up, UART_MSR);
634
635 /*
636 * At this point, there's no way the LSR could still be 0xff;
637 * if it is, then bail out, because there's likely no UART
638 * here.
639 */
640 if (!(up->port.flags & UPF_BUGGY_UART) &&
641 (serial_in(up, UART_LSR) == 0xff)) {
642 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
643 return -ENODEV;
644 }
645
646 if (up->su_type != SU_PORT_PORT) {
647 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
648 IRQF_SHARED, su_typev[up->su_type], up);
649 } else {
650 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
651 IRQF_SHARED, su_typev[up->su_type], up);
652 }
653 if (retval) {
654 printk("su: Cannot register IRQ %d\n", up->port.irq);
655 return retval;
656 }
657
658 /*
659 * Now, initialize the UART
660 */
661 serial_out(up, UART_LCR, UART_LCR_WLEN8);
662
663 uart_port_lock_irqsave(&up->port, &flags);
664
665 up->port.mctrl |= TIOCM_OUT2;
666
667 sunsu_set_mctrl(&up->port, up->port.mctrl);
668 uart_port_unlock_irqrestore(&up->port, flags);
669
670 /*
671 * Finally, enable interrupts. Note: Modem status interrupts
672 * are set via set_termios(), which will be occurring imminently
673 * anyway, so we don't enable them here.
674 */
675 up->ier = UART_IER_RLSI | UART_IER_RDI;
676 serial_out(up, UART_IER, up->ier);
677
678 if (up->port.flags & UPF_FOURPORT) {
679 unsigned int icp;
680 /*
681 * Enable interrupts on the AST Fourport board
682 */
683 icp = (up->port.iobase & 0xfe0) | 0x01f;
684 outb_p(0x80, icp);
685 (void) inb_p(icp);
686 }
687
688 /*
689 * And clear the interrupt registers again for luck.
690 */
691 (void) serial_in(up, UART_LSR);
692 (void) serial_in(up, UART_RX);
693 (void) serial_in(up, UART_IIR);
694 (void) serial_in(up, UART_MSR);
695
696 return 0;
697}
698
699static void sunsu_shutdown(struct uart_port *port)
700{
701 struct uart_sunsu_port *up =
702 container_of(port, struct uart_sunsu_port, port);
703 unsigned long flags;
704
705 /*
706 * Disable interrupts from this port
707 */
708 up->ier = 0;
709 serial_out(up, UART_IER, 0);
710
711 uart_port_lock_irqsave(&up->port, &flags);
712 if (up->port.flags & UPF_FOURPORT) {
713 /* reset interrupts on the AST Fourport board */
714 inb((up->port.iobase & 0xfe0) | 0x1f);
715 up->port.mctrl |= TIOCM_OUT1;
716 } else
717 up->port.mctrl &= ~TIOCM_OUT2;
718
719 sunsu_set_mctrl(&up->port, up->port.mctrl);
720 uart_port_unlock_irqrestore(&up->port, flags);
721
722 /*
723 * Disable break condition and FIFOs
724 */
725 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
726 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
727 UART_FCR_CLEAR_RCVR |
728 UART_FCR_CLEAR_XMIT);
729 serial_out(up, UART_FCR, 0);
730
731#ifdef CONFIG_SERIAL_8250_RSA
732 /*
733 * Reset the RSA board back to 115kbps compat mode.
734 */
735 disable_rsa(up);
736#endif
737
738 /*
739 * Read data port to reset things.
740 */
741 (void) serial_in(up, UART_RX);
742
743 free_irq(up->port.irq, up);
744}
745
746static void
747sunsu_change_speed(struct uart_port *port, unsigned int cflag,
748 unsigned int iflag, unsigned int quot)
749{
750 struct uart_sunsu_port *up =
751 container_of(port, struct uart_sunsu_port, port);
752 unsigned char cval, fcr = 0;
753 unsigned long flags;
754
755 switch (cflag & CSIZE) {
756 case CS5:
757 cval = 0x00;
758 break;
759 case CS6:
760 cval = 0x01;
761 break;
762 case CS7:
763 cval = 0x02;
764 break;
765 default:
766 case CS8:
767 cval = 0x03;
768 break;
769 }
770
771 if (cflag & CSTOPB)
772 cval |= 0x04;
773 if (cflag & PARENB)
774 cval |= UART_LCR_PARITY;
775 if (!(cflag & PARODD))
776 cval |= UART_LCR_EPAR;
777 if (cflag & CMSPAR)
778 cval |= UART_LCR_SPAR;
779
780 /*
781 * Work around a bug in the Oxford Semiconductor 952 rev B
782 * chip which causes it to seriously miscalculate baud rates
783 * when DLL is 0.
784 */
785 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
786 up->rev == 0x5201)
787 quot ++;
788
789 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
790 if ((up->port.uartclk / quot) < (2400 * 16))
791 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
792#ifdef CONFIG_SERIAL_8250_RSA
793 else if (up->port.type == PORT_RSA)
794 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
795#endif
796 else
797 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
798 }
799 if (up->port.type == PORT_16750)
800 fcr |= UART_FCR7_64BYTE;
801
802 /*
803 * Ok, we're now changing the port state. Do it with
804 * interrupts disabled.
805 */
806 uart_port_lock_irqsave(&up->port, &flags);
807
808 /*
809 * Update the per-port timeout.
810 */
811 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
812
813 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
814 if (iflag & INPCK)
815 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
816 if (iflag & (IGNBRK | BRKINT | PARMRK))
817 up->port.read_status_mask |= UART_LSR_BI;
818
819 /*
820 * Characteres to ignore
821 */
822 up->port.ignore_status_mask = 0;
823 if (iflag & IGNPAR)
824 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
825 if (iflag & IGNBRK) {
826 up->port.ignore_status_mask |= UART_LSR_BI;
827 /*
828 * If we're ignoring parity and break indicators,
829 * ignore overruns too (for real raw support).
830 */
831 if (iflag & IGNPAR)
832 up->port.ignore_status_mask |= UART_LSR_OE;
833 }
834
835 /*
836 * ignore all characters if CREAD is not set
837 */
838 if ((cflag & CREAD) == 0)
839 up->port.ignore_status_mask |= UART_LSR_DR;
840
841 /*
842 * CTS flow control flag and modem status interrupts
843 */
844 up->ier &= ~UART_IER_MSI;
845 if (UART_ENABLE_MS(&up->port, cflag))
846 up->ier |= UART_IER_MSI;
847
848 serial_out(up, UART_IER, up->ier);
849
850 if (uart_config[up->port.type].flags & UART_STARTECH) {
851 serial_out(up, UART_LCR, 0xBF);
852 serial_out(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
853 }
854 serial_out(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
855 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
856 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
857 if (up->port.type == PORT_16750)
858 serial_out(up, UART_FCR, fcr); /* set fcr */
859 serial_out(up, UART_LCR, cval); /* reset DLAB */
860 up->lcr = cval; /* Save LCR */
861 if (up->port.type != PORT_16750) {
862 if (fcr & UART_FCR_ENABLE_FIFO) {
863 /* emulated UARTs (Lucent Venus 167x) need two steps */
864 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
865 }
866 serial_out(up, UART_FCR, fcr); /* set fcr */
867 }
868
869 up->cflag = cflag;
870
871 uart_port_unlock_irqrestore(&up->port, flags);
872}
873
874static void
875sunsu_set_termios(struct uart_port *port, struct ktermios *termios,
876 const struct ktermios *old)
877{
878 unsigned int baud, quot;
879
880 /*
881 * Ask the core to calculate the divisor for us.
882 */
883 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
884 quot = uart_get_divisor(port, baud);
885
886 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
887}
888
889static void sunsu_release_port(struct uart_port *port)
890{
891}
892
893static int sunsu_request_port(struct uart_port *port)
894{
895 return 0;
896}
897
898static void sunsu_config_port(struct uart_port *port, int flags)
899{
900 struct uart_sunsu_port *up =
901 container_of(port, struct uart_sunsu_port, port);
902
903 if (flags & UART_CONFIG_TYPE) {
904 /*
905 * We are supposed to call autoconfig here, but this requires
906 * splitting all the OBP probing crap from the UART probing.
907 * We'll do it when we kill sunsu.c altogether.
908 */
909 port->type = up->type_probed; /* XXX */
910 }
911}
912
913static int
914sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
915{
916 return -EINVAL;
917}
918
919static const char *
920sunsu_type(struct uart_port *port)
921{
922 int type = port->type;
923
924 if (type >= ARRAY_SIZE(uart_config))
925 type = 0;
926 return uart_config[type].name;
927}
928
929static const struct uart_ops sunsu_pops = {
930 .tx_empty = sunsu_tx_empty,
931 .set_mctrl = sunsu_set_mctrl,
932 .get_mctrl = sunsu_get_mctrl,
933 .stop_tx = sunsu_stop_tx,
934 .start_tx = sunsu_start_tx,
935 .stop_rx = sunsu_stop_rx,
936 .enable_ms = sunsu_enable_ms,
937 .break_ctl = sunsu_break_ctl,
938 .startup = sunsu_startup,
939 .shutdown = sunsu_shutdown,
940 .set_termios = sunsu_set_termios,
941 .type = sunsu_type,
942 .release_port = sunsu_release_port,
943 .request_port = sunsu_request_port,
944 .config_port = sunsu_config_port,
945 .verify_port = sunsu_verify_port,
946};
947
948#define UART_NR 4
949
950static struct uart_sunsu_port sunsu_ports[UART_NR];
951static int nr_inst; /* Number of already registered ports */
952
953#ifdef CONFIG_SERIO
954
955static DEFINE_SPINLOCK(sunsu_serio_lock);
956
957static int sunsu_serio_write(struct serio *serio, unsigned char ch)
958{
959 struct uart_sunsu_port *up = serio->port_data;
960 unsigned long flags;
961 int lsr;
962
963 spin_lock_irqsave(&sunsu_serio_lock, flags);
964
965 do {
966 lsr = serial_in(up, UART_LSR);
967 } while (!(lsr & UART_LSR_THRE));
968
969 /* Send the character out. */
970 serial_out(up, UART_TX, ch);
971
972 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
973
974 return 0;
975}
976
977static int sunsu_serio_open(struct serio *serio)
978{
979 struct uart_sunsu_port *up = serio->port_data;
980 unsigned long flags;
981 int ret;
982
983 spin_lock_irqsave(&sunsu_serio_lock, flags);
984 if (!up->serio_open) {
985 up->serio_open = 1;
986 ret = 0;
987 } else
988 ret = -EBUSY;
989 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
990
991 return ret;
992}
993
994static void sunsu_serio_close(struct serio *serio)
995{
996 struct uart_sunsu_port *up = serio->port_data;
997 unsigned long flags;
998
999 spin_lock_irqsave(&sunsu_serio_lock, flags);
1000 up->serio_open = 0;
1001 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1002}
1003
1004#endif /* CONFIG_SERIO */
1005
1006static void sunsu_autoconfig(struct uart_sunsu_port *up)
1007{
1008 unsigned char status1, status2, scratch, scratch2, scratch3;
1009 unsigned char save_lcr, save_mcr;
1010 unsigned long flags;
1011
1012 if (up->su_type == SU_PORT_NONE)
1013 return;
1014
1015 up->type_probed = PORT_UNKNOWN;
1016 up->port.iotype = UPIO_MEM;
1017
1018 uart_port_lock_irqsave(&up->port, &flags);
1019
1020 if (!(up->port.flags & UPF_BUGGY_UART)) {
1021 /*
1022 * Do a simple existence test first; if we fail this, there's
1023 * no point trying anything else.
1024 *
1025 * 0x80 is used as a nonsense port to prevent against false
1026 * positives due to ISA bus float. The assumption is that
1027 * 0x80 is a non-existent port; which should be safe since
1028 * include/asm/io.h also makes this assumption.
1029 */
1030 scratch = serial_in(up, UART_IER);
1031 serial_out(up, UART_IER, 0);
1032#ifdef __i386__
1033 outb(0xff, 0x080);
1034#endif
1035 scratch2 = serial_in(up, UART_IER);
1036 serial_out(up, UART_IER, 0x0f);
1037#ifdef __i386__
1038 outb(0, 0x080);
1039#endif
1040 scratch3 = serial_in(up, UART_IER);
1041 serial_out(up, UART_IER, scratch);
1042 if (scratch2 != 0 || scratch3 != 0x0F)
1043 goto out; /* We failed; there's nothing here */
1044 }
1045
1046 save_mcr = serial_in(up, UART_MCR);
1047 save_lcr = serial_in(up, UART_LCR);
1048
1049 /*
1050 * Check to see if a UART is really there. Certain broken
1051 * internal modems based on the Rockwell chipset fail this
1052 * test, because they apparently don't implement the loopback
1053 * test mode. So this test is skipped on the COM 1 through
1054 * COM 4 ports. This *should* be safe, since no board
1055 * manufacturer would be stupid enough to design a board
1056 * that conflicts with COM 1-4 --- we hope!
1057 */
1058 if (!(up->port.flags & UPF_SKIP_TEST)) {
1059 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1060 status1 = serial_in(up, UART_MSR) & 0xF0;
1061 serial_out(up, UART_MCR, save_mcr);
1062 if (status1 != 0x90)
1063 goto out; /* We failed loopback test */
1064 }
1065 serial_out(up, UART_LCR, 0xBF); /* set up for StarTech test */
1066 serial_out(up, UART_EFR, 0); /* EFR is the same as FCR */
1067 serial_out(up, UART_LCR, 0);
1068 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1069 scratch = serial_in(up, UART_IIR) >> 6;
1070 switch (scratch) {
1071 case 0:
1072 up->port.type = PORT_16450;
1073 break;
1074 case 1:
1075 up->port.type = PORT_UNKNOWN;
1076 break;
1077 case 2:
1078 up->port.type = PORT_16550;
1079 break;
1080 case 3:
1081 up->port.type = PORT_16550A;
1082 break;
1083 }
1084 if (up->port.type == PORT_16550A) {
1085 /* Check for Startech UART's */
1086 serial_out(up, UART_LCR, UART_LCR_DLAB);
1087 if (serial_in(up, UART_EFR) == 0) {
1088 up->port.type = PORT_16650;
1089 } else {
1090 serial_out(up, UART_LCR, 0xBF);
1091 if (serial_in(up, UART_EFR) == 0)
1092 up->port.type = PORT_16650V2;
1093 }
1094 }
1095 if (up->port.type == PORT_16550A) {
1096 /* Check for TI 16750 */
1097 serial_out(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1098 serial_out(up, UART_FCR,
1099 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1100 scratch = serial_in(up, UART_IIR) >> 5;
1101 if (scratch == 7) {
1102 /*
1103 * If this is a 16750, and not a cheap UART
1104 * clone, then it should only go into 64 byte
1105 * mode if the UART_FCR7_64BYTE bit was set
1106 * while UART_LCR_DLAB was latched.
1107 */
1108 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1109 serial_out(up, UART_LCR, 0);
1110 serial_out(up, UART_FCR,
1111 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1112 scratch = serial_in(up, UART_IIR) >> 5;
1113 if (scratch == 6)
1114 up->port.type = PORT_16750;
1115 }
1116 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1117 }
1118 serial_out(up, UART_LCR, save_lcr);
1119 if (up->port.type == PORT_16450) {
1120 scratch = serial_in(up, UART_SCR);
1121 serial_out(up, UART_SCR, 0xa5);
1122 status1 = serial_in(up, UART_SCR);
1123 serial_out(up, UART_SCR, 0x5a);
1124 status2 = serial_in(up, UART_SCR);
1125 serial_out(up, UART_SCR, scratch);
1126
1127 if ((status1 != 0xa5) || (status2 != 0x5a))
1128 up->port.type = PORT_8250;
1129 }
1130
1131 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1132
1133 if (up->port.type == PORT_UNKNOWN)
1134 goto out;
1135 up->type_probed = up->port.type; /* XXX */
1136
1137 /*
1138 * Reset the UART.
1139 */
1140#ifdef CONFIG_SERIAL_8250_RSA
1141 if (up->port.type == PORT_RSA)
1142 serial_out(up, UART_RSA_FRR, 0);
1143#endif
1144 serial_out(up, UART_MCR, save_mcr);
1145 serial_out(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1146 UART_FCR_CLEAR_RCVR |
1147 UART_FCR_CLEAR_XMIT));
1148 serial_out(up, UART_FCR, 0);
1149 (void)serial_in(up, UART_RX);
1150 serial_out(up, UART_IER, 0);
1151
1152out:
1153 uart_port_unlock_irqrestore(&up->port, flags);
1154}
1155
1156static struct uart_driver sunsu_reg = {
1157 .owner = THIS_MODULE,
1158 .driver_name = "sunsu",
1159 .dev_name = "ttyS",
1160 .major = TTY_MAJOR,
1161};
1162
1163static int sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1164{
1165 int quot, baud;
1166#ifdef CONFIG_SERIO
1167 struct serio *serio;
1168#endif
1169
1170 if (up->su_type == SU_PORT_KBD) {
1171 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1172 baud = 1200;
1173 } else {
1174 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1175 baud = 4800;
1176 }
1177 quot = up->port.uartclk / (16 * baud);
1178
1179 sunsu_autoconfig(up);
1180 if (up->port.type == PORT_UNKNOWN)
1181 return -ENODEV;
1182
1183 printk("%pOF: %s port at %llx, irq %u\n",
1184 up->port.dev->of_node,
1185 (up->su_type == SU_PORT_KBD) ? "Keyboard" : "Mouse",
1186 (unsigned long long) up->port.mapbase,
1187 up->port.irq);
1188
1189#ifdef CONFIG_SERIO
1190 serio = &up->serio;
1191 serio->port_data = up;
1192
1193 serio->id.type = SERIO_RS232;
1194 if (up->su_type == SU_PORT_KBD) {
1195 serio->id.proto = SERIO_SUNKBD;
1196 strscpy(serio->name, "sukbd", sizeof(serio->name));
1197 } else {
1198 serio->id.proto = SERIO_SUN;
1199 serio->id.extra = 1;
1200 strscpy(serio->name, "sums", sizeof(serio->name));
1201 }
1202 strscpy(serio->phys,
1203 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1204 sizeof(serio->phys));
1205
1206 serio->write = sunsu_serio_write;
1207 serio->open = sunsu_serio_open;
1208 serio->close = sunsu_serio_close;
1209 serio->dev.parent = up->port.dev;
1210
1211 serio_register_port(serio);
1212#endif
1213
1214 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1215
1216 sunsu_startup(&up->port);
1217 return 0;
1218}
1219
1220/*
1221 * ------------------------------------------------------------
1222 * Serial console driver
1223 * ------------------------------------------------------------
1224 */
1225
1226#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1227
1228/*
1229 * Wait for transmitter & holding register to empty
1230 */
1231static void wait_for_xmitr(struct uart_sunsu_port *up)
1232{
1233 unsigned int status, tmout = 10000;
1234
1235 /* Wait up to 10ms for the character(s) to be sent. */
1236 do {
1237 status = serial_in(up, UART_LSR);
1238
1239 if (status & UART_LSR_BI)
1240 up->lsr_break_flag = UART_LSR_BI;
1241
1242 if (--tmout == 0)
1243 break;
1244 udelay(1);
1245 } while (!uart_lsr_tx_empty(status));
1246
1247 /* Wait up to 1s for flow control if necessary */
1248 if (uart_cons_flow_enabled(&up->port)) {
1249 tmout = 1000000;
1250 while (--tmout &&
1251 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1252 udelay(1);
1253 }
1254}
1255
1256static void sunsu_console_putchar(struct uart_port *port, unsigned char ch)
1257{
1258 struct uart_sunsu_port *up =
1259 container_of(port, struct uart_sunsu_port, port);
1260
1261 wait_for_xmitr(up);
1262 serial_out(up, UART_TX, ch);
1263}
1264
1265/*
1266 * Print a string to the serial port trying not to disturb
1267 * any possible real use of the port...
1268 */
1269static void sunsu_console_write(struct console *co, const char *s,
1270 unsigned int count)
1271{
1272 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1273 unsigned long flags;
1274 unsigned int ier;
1275 int locked = 1;
1276
1277 if (up->port.sysrq || oops_in_progress)
1278 locked = uart_port_trylock_irqsave(&up->port, &flags);
1279 else
1280 uart_port_lock_irqsave(&up->port, &flags);
1281
1282 /*
1283 * First save the UER then disable the interrupts
1284 */
1285 ier = serial_in(up, UART_IER);
1286 serial_out(up, UART_IER, 0);
1287
1288 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1289
1290 /*
1291 * Finally, wait for transmitter to become empty
1292 * and restore the IER
1293 */
1294 wait_for_xmitr(up);
1295 serial_out(up, UART_IER, ier);
1296
1297 if (locked)
1298 uart_port_unlock_irqrestore(&up->port, flags);
1299}
1300
1301/*
1302 * Setup initial baud/bits/parity. We do two things here:
1303 * - construct a cflag setting for the first su_open()
1304 * - initialize the serial port
1305 * Return non-zero if we didn't find a serial port.
1306 */
1307static int __init sunsu_console_setup(struct console *co, char *options)
1308{
1309 static struct ktermios dummy;
1310 struct ktermios termios;
1311 struct uart_port *port;
1312
1313 printk("Console: ttyS%d (SU)\n",
1314 (sunsu_reg.minor - 64) + co->index);
1315
1316 if (co->index > nr_inst)
1317 return -ENODEV;
1318 port = &sunsu_ports[co->index].port;
1319
1320 /*
1321 * Temporary fix.
1322 */
1323 spin_lock_init(&port->lock);
1324
1325 /* Get firmware console settings. */
1326 sunserial_console_termios(co, port->dev->of_node);
1327
1328 memset(&termios, 0, sizeof(struct ktermios));
1329 termios.c_cflag = co->cflag;
1330 port->mctrl |= TIOCM_DTR;
1331 port->ops->set_termios(port, &termios, &dummy);
1332
1333 return 0;
1334}
1335
1336static struct console sunsu_console = {
1337 .name = "ttyS",
1338 .write = sunsu_console_write,
1339 .device = uart_console_device,
1340 .setup = sunsu_console_setup,
1341 .flags = CON_PRINTBUFFER,
1342 .index = -1,
1343 .data = &sunsu_reg,
1344};
1345
1346/*
1347 * Register console.
1348 */
1349
1350static inline struct console *SUNSU_CONSOLE(void)
1351{
1352 return &sunsu_console;
1353}
1354#else
1355#define SUNSU_CONSOLE() (NULL)
1356#define sunsu_serial_console_init() do { } while (0)
1357#endif
1358
1359static enum su_type su_get_type(struct device_node *dp)
1360{
1361 struct device_node *ap __free(device_node) =
1362 of_find_node_by_path("/aliases");
1363
1364 if (ap) {
1365 const char *keyb = of_get_property(ap, "keyboard", NULL);
1366 const char *ms = of_get_property(ap, "mouse", NULL);
1367
1368 if (keyb) {
1369 struct device_node *match __free(device_node) =
1370 of_find_node_by_path(keyb);
1371
1372 if (dp == match)
1373 return SU_PORT_KBD;
1374 }
1375 if (ms) {
1376 struct device_node *match __free(device_node) =
1377 of_find_node_by_path(ms);
1378
1379 if (dp == match)
1380 return SU_PORT_MS;
1381 }
1382 }
1383 return SU_PORT_PORT;
1384}
1385
1386static int su_probe(struct platform_device *op)
1387{
1388 struct device_node *dp = op->dev.of_node;
1389 struct uart_sunsu_port *up;
1390 struct resource *rp;
1391 enum su_type type;
1392 bool ignore_line;
1393 int err;
1394
1395 type = su_get_type(dp);
1396 if (type == SU_PORT_PORT) {
1397 if (nr_inst >= UART_NR)
1398 return -EINVAL;
1399 up = &sunsu_ports[nr_inst];
1400 } else {
1401 up = kzalloc_obj(*up);
1402 if (!up)
1403 return -ENOMEM;
1404 }
1405
1406 up->port.line = nr_inst;
1407
1408 spin_lock_init(&up->port.lock);
1409
1410 up->su_type = type;
1411
1412 rp = &op->resource[0];
1413 up->port.mapbase = rp->start;
1414 up->reg_size = resource_size(rp);
1415 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
1416 if (!up->port.membase) {
1417 if (type != SU_PORT_PORT)
1418 kfree(up);
1419 return -ENOMEM;
1420 }
1421
1422 up->port.irq = op->archdata.irqs[0];
1423
1424 up->port.dev = &op->dev;
1425
1426 up->port.type = PORT_UNKNOWN;
1427 up->port.uartclk = (SU_BASE_BAUD * 16);
1428 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSU_CONSOLE);
1429
1430 err = 0;
1431 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1432 err = sunsu_kbd_ms_init(up);
1433 if (err) {
1434 of_iounmap(&op->resource[0],
1435 up->port.membase, up->reg_size);
1436 kfree(up);
1437 return err;
1438 }
1439 platform_set_drvdata(op, up);
1440
1441 nr_inst++;
1442
1443 return 0;
1444 }
1445
1446 up->port.flags |= UPF_BOOT_AUTOCONF;
1447
1448 sunsu_autoconfig(up);
1449
1450 err = -ENODEV;
1451 if (up->port.type == PORT_UNKNOWN)
1452 goto out_unmap;
1453
1454 up->port.ops = &sunsu_pops;
1455
1456 ignore_line = false;
1457 if (of_node_name_eq(dp, "rsc-console") ||
1458 of_node_name_eq(dp, "lom-console"))
1459 ignore_line = true;
1460
1461 sunserial_console_match(SUNSU_CONSOLE(), dp,
1462 &sunsu_reg, up->port.line,
1463 ignore_line);
1464 err = uart_add_one_port(&sunsu_reg, &up->port);
1465 if (err)
1466 goto out_unmap;
1467
1468 platform_set_drvdata(op, up);
1469
1470 nr_inst++;
1471
1472 return 0;
1473
1474out_unmap:
1475 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1476 kfree(up);
1477 return err;
1478}
1479
1480static void su_remove(struct platform_device *op)
1481{
1482 struct uart_sunsu_port *up = platform_get_drvdata(op);
1483 bool kbdms = false;
1484
1485 if (up->su_type == SU_PORT_MS ||
1486 up->su_type == SU_PORT_KBD)
1487 kbdms = true;
1488
1489 if (kbdms) {
1490#ifdef CONFIG_SERIO
1491 serio_unregister_port(&up->serio);
1492#endif
1493 } else if (up->port.type != PORT_UNKNOWN)
1494 uart_remove_one_port(&sunsu_reg, &up->port);
1495
1496 if (up->port.membase)
1497 of_iounmap(&op->resource[0], up->port.membase, up->reg_size);
1498
1499 if (kbdms)
1500 kfree(up);
1501}
1502
1503static const struct of_device_id su_match[] = {
1504 {
1505 .name = "su",
1506 },
1507 {
1508 .name = "su_pnp",
1509 },
1510 {
1511 .name = "serial",
1512 .compatible = "su",
1513 },
1514 {
1515 .type = "serial",
1516 .compatible = "su",
1517 },
1518 {},
1519};
1520MODULE_DEVICE_TABLE(of, su_match);
1521
1522static struct platform_driver su_driver = {
1523 .driver = {
1524 .name = "su",
1525 .of_match_table = su_match,
1526 },
1527 .probe = su_probe,
1528 .remove = su_remove,
1529};
1530
1531static int __init sunsu_init(void)
1532{
1533 struct device_node *dp;
1534 int err;
1535 int num_uart = 0;
1536
1537 for_each_node_by_name(dp, "su") {
1538 if (su_get_type(dp) == SU_PORT_PORT)
1539 num_uart++;
1540 }
1541 for_each_node_by_name(dp, "su_pnp") {
1542 if (su_get_type(dp) == SU_PORT_PORT)
1543 num_uart++;
1544 }
1545 for_each_node_by_name(dp, "serial") {
1546 if (of_device_is_compatible(dp, "su")) {
1547 if (su_get_type(dp) == SU_PORT_PORT)
1548 num_uart++;
1549 }
1550 }
1551 for_each_node_by_type(dp, "serial") {
1552 if (of_device_is_compatible(dp, "su")) {
1553 if (su_get_type(dp) == SU_PORT_PORT)
1554 num_uart++;
1555 }
1556 }
1557
1558 if (num_uart) {
1559 err = sunserial_register_minors(&sunsu_reg, num_uart);
1560 if (err)
1561 return err;
1562 }
1563
1564 err = platform_driver_register(&su_driver);
1565 if (err && num_uart)
1566 sunserial_unregister_minors(&sunsu_reg, num_uart);
1567
1568 return err;
1569}
1570
1571static void __exit sunsu_exit(void)
1572{
1573 platform_driver_unregister(&su_driver);
1574 if (sunsu_reg.nr)
1575 sunserial_unregister_minors(&sunsu_reg, sunsu_reg.nr);
1576}
1577
1578module_init(sunsu_init);
1579module_exit(sunsu_exit);
1580
1581MODULE_AUTHOR("Eddie C. Dost, Peter Zaitcev, and David S. Miller");
1582MODULE_DESCRIPTION("Sun SU serial port driver");
1583MODULE_VERSION("2.0");
1584MODULE_LICENSE("GPL");