projects/linux·blob master · refs

949 lines · 22.2 KiB

1// SPDX-License-Identifier: GPL-2.0
2/*
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
4 *
5 * Copyright (C) 2006 Peter Korsgaard <[email protected]>
6 * Copyright (C) 2007 Secret Lab Technologies Ltd.
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/bitfield.h>
12#include <linux/console.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/iopoll.h>
22#include <linux/of.h>
23#include <linux/clk.h>
24#include <linux/pm_runtime.h>
25
26#define ULITE_NAME "ttyUL"
27#if CONFIG_SERIAL_UARTLITE_NR_UARTS > 4
28#define ULITE_MAJOR 0 /* use dynamic node allocation */
29#define ULITE_MINOR 0
30#else
31#define ULITE_MAJOR 204
32#define ULITE_MINOR 187
33#endif
34#define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
35
36/* ---------------------------------------------------------------------
37 * Register definitions
38 *
39 * For register details see datasheet:
40 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
41 */
42
43#define ULITE_RX 0x00
44#define ULITE_TX 0x04
45#define ULITE_STATUS 0x08
46#define ULITE_CONTROL 0x0c
47
48#define ULITE_REGION 16
49
50#define ULITE_STATUS_RXVALID 0x01
51#define ULITE_STATUS_RXFULL 0x02
52#define ULITE_STATUS_TXEMPTY 0x04
53#define ULITE_STATUS_TXFULL 0x08
54#define ULITE_STATUS_IE 0x10
55#define ULITE_STATUS_OVERRUN 0x20
56#define ULITE_STATUS_FRAME 0x40
57#define ULITE_STATUS_PARITY 0x80
58
59#define ULITE_CONTROL_RST_TX 0x01
60#define ULITE_CONTROL_RST_RX 0x02
61#define ULITE_CONTROL_IE 0x10
62#define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */
63
64/* Static pointer to console port */
65#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
66static struct uart_port *console_port;
67#endif
68
69/**
70 * struct uartlite_data - Driver private data
71 * @reg_ops: Functions to read/write registers
72 * @clk: Our parent clock, if present
73 * @baud: The baud rate configured when this device was synthesized
74 * @cflags: The cflags for parity and data bits
75 */
76struct uartlite_data {
77 const struct uartlite_reg_ops *reg_ops;
78 struct clk *clk;
79 unsigned int baud;
80 tcflag_t cflags;
81};
82
83struct uartlite_reg_ops {
84 u32 (*in)(void __iomem *addr);
85 void (*out)(u32 val, void __iomem *addr);
86};
87
88static u32 uartlite_inbe32(void __iomem *addr)
89{
90 return ioread32be(addr);
91}
92
93static void uartlite_outbe32(u32 val, void __iomem *addr)
94{
95 iowrite32be(val, addr);
96}
97
98static const struct uartlite_reg_ops uartlite_be = {
99 .in = uartlite_inbe32,
100 .out = uartlite_outbe32,
101};
102
103static u32 uartlite_inle32(void __iomem *addr)
104{
105 return ioread32(addr);
106}
107
108static void uartlite_outle32(u32 val, void __iomem *addr)
109{
110 iowrite32(val, addr);
111}
112
113static const struct uartlite_reg_ops uartlite_le = {
114 .in = uartlite_inle32,
115 .out = uartlite_outle32,
116};
117
118static inline u32 uart_in32(u32 offset, struct uart_port *port)
119{
120 struct uartlite_data *pdata = port->private_data;
121
122 return pdata->reg_ops->in(port->membase + offset);
123}
124
125static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
126{
127 struct uartlite_data *pdata = port->private_data;
128
129 pdata->reg_ops->out(val, port->membase + offset);
130}
131
132static struct uart_port ulite_ports[ULITE_NR_UARTS];
133
134static struct uart_driver ulite_uart_driver;
135
136/* ---------------------------------------------------------------------
137 * Core UART driver operations
138 */
139
140static int ulite_receive(struct uart_port *port, int stat)
141{
142 struct tty_port *tport = &port->state->port;
143 unsigned char ch = 0;
144 char flag = TTY_NORMAL;
145
146 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
147 | ULITE_STATUS_FRAME)) == 0)
148 return 0;
149
150 /* stats */
151 if (stat & ULITE_STATUS_RXVALID) {
152 port->icount.rx++;
153 ch = uart_in32(ULITE_RX, port);
154
155 if (stat & ULITE_STATUS_PARITY)
156 port->icount.parity++;
157 }
158
159 if (stat & ULITE_STATUS_OVERRUN)
160 port->icount.overrun++;
161
162 if (stat & ULITE_STATUS_FRAME)
163 port->icount.frame++;
164
165
166 /* drop byte with parity error if IGNPAR specificed */
167 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
168 stat &= ~ULITE_STATUS_RXVALID;
169
170 stat &= port->read_status_mask;
171
172 if (stat & ULITE_STATUS_PARITY)
173 flag = TTY_PARITY;
174
175
176 stat &= ~port->ignore_status_mask;
177
178 if (stat & ULITE_STATUS_RXVALID)
179 tty_insert_flip_char(tport, ch, flag);
180
181 if (stat & ULITE_STATUS_FRAME)
182 tty_insert_flip_char(tport, 0, TTY_FRAME);
183
184 if (stat & ULITE_STATUS_OVERRUN)
185 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
186
187 return 1;
188}
189
190static int ulite_transmit(struct uart_port *port, int stat)
191{
192 struct tty_port *tport = &port->state->port;
193 unsigned char ch;
194
195 if (stat & ULITE_STATUS_TXFULL)
196 return 0;
197
198 if (port->x_char) {
199 uart_out32(port->x_char, ULITE_TX, port);
200 port->x_char = 0;
201 port->icount.tx++;
202 return 1;
203 }
204
205 if (uart_tx_stopped(port))
206 return 0;
207
208 if (!uart_fifo_get(port, &ch))
209 return 0;
210
211 uart_out32(ch, ULITE_TX, port);
212
213 /* wake up */
214 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
215 uart_write_wakeup(port);
216
217 return 1;
218}
219
220static irqreturn_t ulite_isr(int irq, void *dev_id)
221{
222 struct uart_port *port = dev_id;
223 int stat, busy, n = 0;
224 unsigned long flags;
225
226 do {
227 uart_port_lock_irqsave(port, &flags);
228 stat = uart_in32(ULITE_STATUS, port);
229 busy = ulite_receive(port, stat);
230 busy |= ulite_transmit(port, stat);
231 uart_port_unlock_irqrestore(port, flags);
232 n++;
233 } while (busy);
234
235 /* work done? */
236 if (n > 1) {
237 tty_flip_buffer_push(&port->state->port);
238 return IRQ_HANDLED;
239 } else {
240 return IRQ_NONE;
241 }
242}
243
244static unsigned int ulite_tx_empty(struct uart_port *port)
245{
246 unsigned long flags;
247 unsigned int ret;
248
249 uart_port_lock_irqsave(port, &flags);
250 ret = uart_in32(ULITE_STATUS, port);
251 uart_port_unlock_irqrestore(port, flags);
252
253 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
254}
255
256static unsigned int ulite_get_mctrl(struct uart_port *port)
257{
258 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
259}
260
261static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
262{
263 /* N/A */
264}
265
266static void ulite_stop_tx(struct uart_port *port)
267{
268 /* N/A */
269}
270
271static void ulite_start_tx(struct uart_port *port)
272{
273 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
274}
275
276static void ulite_stop_rx(struct uart_port *port)
277{
278 /* don't forward any more data (like !CREAD) */
279 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
280 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
281}
282
283static void ulite_break_ctl(struct uart_port *port, int ctl)
284{
285 /* N/A */
286}
287
288static int ulite_startup(struct uart_port *port)
289{
290 struct uartlite_data *pdata = port->private_data;
291 int ret;
292
293 ret = clk_enable(pdata->clk);
294 if (ret) {
295 dev_err(port->dev, "Failed to enable clock\n");
296 return ret;
297 }
298
299 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
300 "uartlite", port);
301 if (ret)
302 return ret;
303
304 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
305 ULITE_CONTROL, port);
306 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
307
308 return 0;
309}
310
311static void ulite_shutdown(struct uart_port *port)
312{
313 struct uartlite_data *pdata = port->private_data;
314
315 uart_out32(0, ULITE_CONTROL, port);
316 uart_in32(ULITE_CONTROL, port); /* dummy */
317 free_irq(port->irq, port);
318 clk_disable(pdata->clk);
319}
320
321static void ulite_set_termios(struct uart_port *port,
322 struct ktermios *termios,
323 const struct ktermios *old)
324{
325 unsigned long flags;
326 struct uartlite_data *pdata = port->private_data;
327
328 /* Set termios to what the hardware supports */
329 termios->c_iflag &= ~BRKINT;
330 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE);
331 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
332 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
333
334 uart_port_lock_irqsave(port, &flags);
335
336 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
337 | ULITE_STATUS_TXFULL;
338
339 if (termios->c_iflag & INPCK)
340 port->read_status_mask |=
341 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
342
343 port->ignore_status_mask = 0;
344 if (termios->c_iflag & IGNPAR)
345 port->ignore_status_mask |= ULITE_STATUS_PARITY
346 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
347
348 /* ignore all characters if CREAD is not set */
349 if ((termios->c_cflag & CREAD) == 0)
350 port->ignore_status_mask |=
351 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
352 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
353
354 /* update timeout */
355 uart_update_timeout(port, termios->c_cflag, pdata->baud);
356
357 uart_port_unlock_irqrestore(port, flags);
358}
359
360static const char *ulite_type(struct uart_port *port)
361{
362 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
363}
364
365static void ulite_release_port(struct uart_port *port)
366{
367 release_mem_region(port->mapbase, ULITE_REGION);
368 iounmap(port->membase);
369 port->membase = NULL;
370}
371
372static int ulite_request_port(struct uart_port *port)
373{
374 struct uartlite_data *pdata = port->private_data;
375 int ret;
376
377 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
378 port, (unsigned long long) port->mapbase);
379
380 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
381 dev_err(port->dev, "Memory region busy\n");
382 return -EBUSY;
383 }
384
385 port->membase = ioremap(port->mapbase, ULITE_REGION);
386 if (!port->membase) {
387 dev_err(port->dev, "Unable to map registers\n");
388 release_mem_region(port->mapbase, ULITE_REGION);
389 return -EBUSY;
390 }
391
392 pdata->reg_ops = &uartlite_be;
393 ret = uart_in32(ULITE_CONTROL, port);
394 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
395 ret = uart_in32(ULITE_STATUS, port);
396 /* Endianess detection */
397 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
398 pdata->reg_ops = &uartlite_le;
399
400 return 0;
401}
402
403static void ulite_config_port(struct uart_port *port, int flags)
404{
405 if (!ulite_request_port(port))
406 port->type = PORT_UARTLITE;
407}
408
409static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
410{
411 /* we don't want the core code to modify any port params */
412 return -EINVAL;
413}
414
415static void ulite_pm(struct uart_port *port, unsigned int state,
416 unsigned int oldstate)
417{
418 int ret;
419
420 if (!state) {
421 ret = pm_runtime_get_sync(port->dev);
422 if (ret < 0)
423 dev_err(port->dev, "Failed to enable clocks\n");
424 } else {
425 pm_runtime_mark_last_busy(port->dev);
426 pm_runtime_put_autosuspend(port->dev);
427 }
428}
429
430#ifdef CONFIG_CONSOLE_POLL
431static int ulite_get_poll_char(struct uart_port *port)
432{
433 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
434 return NO_POLL_CHAR;
435
436 return uart_in32(ULITE_RX, port);
437}
438
439static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
440{
441 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
442 cpu_relax();
443
444 /* write char to device */
445 uart_out32(ch, ULITE_TX, port);
446}
447#endif
448
449static const struct uart_ops ulite_ops = {
450 .tx_empty = ulite_tx_empty,
451 .set_mctrl = ulite_set_mctrl,
452 .get_mctrl = ulite_get_mctrl,
453 .stop_tx = ulite_stop_tx,
454 .start_tx = ulite_start_tx,
455 .stop_rx = ulite_stop_rx,
456 .break_ctl = ulite_break_ctl,
457 .startup = ulite_startup,
458 .shutdown = ulite_shutdown,
459 .set_termios = ulite_set_termios,
460 .type = ulite_type,
461 .release_port = ulite_release_port,
462 .request_port = ulite_request_port,
463 .config_port = ulite_config_port,
464 .verify_port = ulite_verify_port,
465 .pm = ulite_pm,
466#ifdef CONFIG_CONSOLE_POLL
467 .poll_get_char = ulite_get_poll_char,
468 .poll_put_char = ulite_put_poll_char,
469#endif
470};
471
472/* ---------------------------------------------------------------------
473 * Console driver operations
474 */
475
476#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
477static void ulite_console_wait_tx(struct uart_port *port)
478{
479 u8 val;
480
481 /*
482 * Spin waiting for TX fifo to have space available.
483 * When using the Microblaze Debug Module this can take up to 1s
484 */
485 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL),
486 0, 1000000, false, ULITE_STATUS, port))
487 dev_warn(port->dev,
488 "timeout waiting for TX buffer empty\n");
489}
490
491static void ulite_console_putchar(struct uart_port *port, unsigned char ch)
492{
493 ulite_console_wait_tx(port);
494 uart_out32(ch, ULITE_TX, port);
495}
496
497static void ulite_console_write(struct console *co, const char *s,
498 unsigned int count)
499{
500 struct uart_port *port = console_port;
501 unsigned long flags;
502 unsigned int ier;
503 int locked = 1;
504
505 if (oops_in_progress) {
506 locked = uart_port_trylock_irqsave(port, &flags);
507 } else
508 uart_port_lock_irqsave(port, &flags);
509
510 /* save and disable interrupt */
511 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
512 uart_out32(0, ULITE_CONTROL, port);
513
514 uart_console_write(port, s, count, ulite_console_putchar);
515
516 ulite_console_wait_tx(port);
517
518 /* restore interrupt state */
519 if (ier)
520 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
521
522 if (locked)
523 uart_port_unlock_irqrestore(port, flags);
524}
525
526static int ulite_console_setup(struct console *co, char *options)
527{
528 struct uart_port *port = NULL;
529 int baud = 9600;
530 int bits = 8;
531 int parity = 'n';
532 int flow = 'n';
533
534 if (co->index >= 0 && co->index < ULITE_NR_UARTS)
535 port = ulite_ports + co->index;
536
537 /* Has the device been initialized yet? */
538 if (!port || !port->mapbase) {
539 pr_debug("console on ttyUL%i not present\n", co->index);
540 return -ENODEV;
541 }
542
543 console_port = port;
544
545 /* not initialized yet? */
546 if (!port->membase) {
547 if (ulite_request_port(port))
548 return -ENODEV;
549 }
550
551 if (options)
552 uart_parse_options(options, &baud, &parity, &bits, &flow);
553
554 return uart_set_options(port, co, baud, parity, bits, flow);
555}
556
557static struct console ulite_console = {
558 .name = ULITE_NAME,
559 .write = ulite_console_write,
560 .device = uart_console_device,
561 .setup = ulite_console_setup,
562 .flags = CON_PRINTBUFFER,
563 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
564 .data = &ulite_uart_driver,
565};
566
567static void early_uartlite_putc(struct uart_port *port, unsigned char c)
568{
569 /*
570 * Limit how many times we'll spin waiting for TX FIFO status.
571 * This will prevent lockups if the base address is incorrectly
572 * set, or any other issue on the UARTLITE.
573 * This limit is pretty arbitrary, unless we are at about 10 baud
574 * we'll never timeout on a working UART.
575 */
576 unsigned retries = 1000000;
577
578 while (--retries &&
579 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL))
580 ;
581
582 /* Only attempt the iowrite if we didn't timeout */
583 if (retries)
584 writel(c & 0xff, port->membase + ULITE_TX);
585}
586
587static void early_uartlite_write(struct console *console,
588 const char *s, unsigned n)
589{
590 struct earlycon_device *device = console->data;
591 uart_console_write(&device->port, s, n, early_uartlite_putc);
592}
593
594static int __init early_uartlite_setup(struct earlycon_device *device,
595 const char *options)
596{
597 if (!device->port.membase)
598 return -ENODEV;
599
600 device->con->write = early_uartlite_write;
601 return 0;
602}
603EARLYCON_DECLARE(uartlite, early_uartlite_setup);
604OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
605OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
606
607#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
608
609static struct uart_driver ulite_uart_driver = {
610 .owner = THIS_MODULE,
611 .driver_name = "uartlite",
612 .dev_name = ULITE_NAME,
613 .major = ULITE_MAJOR,
614 .minor = ULITE_MINOR,
615 .nr = ULITE_NR_UARTS,
616#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
617 .cons = &ulite_console,
618#endif
619};
620
621/* ---------------------------------------------------------------------
622 * Port assignment functions (mapping devices to uart_port structures)
623 */
624
625/** ulite_assign: register a uartlite device with the driver
626 *
627 * @dev: pointer to device structure
628 * @id: requested id number. Pass -1 for automatic port assignment
629 * @base: base address of uartlite registers
630 * @irq: irq number for uartlite
631 * @pdata: private data for uartlite
632 *
633 * Returns: 0 on success, <0 otherwise
634 */
635static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
636 struct uartlite_data *pdata)
637{
638 struct uart_port *port;
639 int rc;
640
641 /* if id = -1; then scan for a free id and use that */
642 if (id < 0) {
643 for (id = 0; id < ULITE_NR_UARTS; id++)
644 if (ulite_ports[id].mapbase == 0)
645 break;
646 }
647 if (id < 0 || id >= ULITE_NR_UARTS) {
648 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
649 return -EINVAL;
650 }
651
652 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
653 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
654 ULITE_NAME, id);
655 return -EBUSY;
656 }
657
658 port = &ulite_ports[id];
659
660 spin_lock_init(&port->lock);
661 port->fifosize = 16;
662 port->regshift = 2;
663 port->iotype = UPIO_MEM;
664 port->iobase = 1; /* mark port in use */
665 port->mapbase = base;
666 port->membase = NULL;
667 port->ops = &ulite_ops;
668 port->irq = irq;
669 port->flags = UPF_BOOT_AUTOCONF;
670 port->dev = dev;
671 port->type = PORT_UNKNOWN;
672 port->line = id;
673 port->private_data = pdata;
674
675 dev_set_drvdata(dev, port);
676
677 /* Register the port */
678 rc = uart_add_one_port(&ulite_uart_driver, port);
679 if (rc) {
680 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
681 port->mapbase = 0;
682 dev_set_drvdata(dev, NULL);
683 return rc;
684 }
685
686 return 0;
687}
688
689/** ulite_release: register a uartlite device with the driver
690 *
691 * @dev: pointer to device structure
692 */
693static void ulite_release(struct device *dev)
694{
695 struct uart_port *port = dev_get_drvdata(dev);
696
697 if (port) {
698 uart_remove_one_port(&ulite_uart_driver, port);
699 dev_set_drvdata(dev, NULL);
700 port->mapbase = 0;
701 }
702}
703
704/**
705 * ulite_suspend - Stop the device.
706 *
707 * @dev: handle to the device structure.
708 * Return: 0 always.
709 */
710static int __maybe_unused ulite_suspend(struct device *dev)
711{
712 struct uart_port *port = dev_get_drvdata(dev);
713
714 if (port)
715 uart_suspend_port(&ulite_uart_driver, port);
716
717 return 0;
718}
719
720/**
721 * ulite_resume - Resume the device.
722 *
723 * @dev: handle to the device structure.
724 * Return: 0 on success, errno otherwise.
725 */
726static int __maybe_unused ulite_resume(struct device *dev)
727{
728 struct uart_port *port = dev_get_drvdata(dev);
729
730 if (port)
731 uart_resume_port(&ulite_uart_driver, port);
732
733 return 0;
734}
735
736static int __maybe_unused ulite_runtime_suspend(struct device *dev)
737{
738 struct uart_port *port = dev_get_drvdata(dev);
739 struct uartlite_data *pdata = port->private_data;
740
741 clk_disable(pdata->clk);
742 return 0;
743};
744
745static int __maybe_unused ulite_runtime_resume(struct device *dev)
746{
747 struct uart_port *port = dev_get_drvdata(dev);
748 struct uartlite_data *pdata = port->private_data;
749 int ret;
750
751 ret = clk_enable(pdata->clk);
752 if (ret) {
753 dev_err(dev, "Cannot enable clock.\n");
754 return ret;
755 }
756 return 0;
757}
758
759/* ---------------------------------------------------------------------
760 * Platform bus binding
761 */
762
763static const struct dev_pm_ops ulite_pm_ops = {
764 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
765 SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
766 ulite_runtime_resume, NULL)
767};
768
769#if defined(CONFIG_OF)
770/* Match table for of_platform binding */
771static const struct of_device_id ulite_of_match[] = {
772 { .compatible = "xlnx,opb-uartlite-1.00.b", },
773 { .compatible = "xlnx,xps-uartlite-1.00.a", },
774 {}
775};
776MODULE_DEVICE_TABLE(of, ulite_of_match);
777#endif /* CONFIG_OF */
778
779static int ulite_probe(struct platform_device *pdev)
780{
781 struct resource *res;
782 struct uartlite_data *pdata;
783 int irq, ret;
784 int id = pdev->id;
785
786 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
787 GFP_KERNEL);
788 if (!pdata)
789 return -ENOMEM;
790
791 if (IS_ENABLED(CONFIG_OF)) {
792 const char *prop;
793 struct device_node *np = pdev->dev.of_node;
794 u32 val = 0;
795
796 prop = "port-number";
797 ret = of_property_read_u32(np, prop, &id);
798 if (ret && ret != -EINVAL)
799of_err:
800 return dev_err_probe(&pdev->dev, ret,
801 "could not read %s\n", prop);
802
803 prop = "current-speed";
804 ret = of_property_read_u32(np, prop, &pdata->baud);
805 if (ret)
806 goto of_err;
807
808 prop = "xlnx,use-parity";
809 ret = of_property_read_u32(np, prop, &val);
810 if (ret && ret != -EINVAL)
811 goto of_err;
812
813 if (val) {
814 prop = "xlnx,odd-parity";
815 ret = of_property_read_u32(np, prop, &val);
816 if (ret)
817 goto of_err;
818
819 if (val)
820 pdata->cflags |= PARODD;
821 pdata->cflags |= PARENB;
822 }
823
824 val = 8;
825 prop = "xlnx,data-bits";
826 ret = of_property_read_u32(np, prop, &val);
827 if (ret && ret != -EINVAL)
828 goto of_err;
829
830 switch (val) {
831 case 5:
832 pdata->cflags |= CS5;
833 break;
834 case 6:
835 pdata->cflags |= CS6;
836 break;
837 case 7:
838 pdata->cflags |= CS7;
839 break;
840 case 8:
841 pdata->cflags |= CS8;
842 break;
843 default:
844 return dev_err_probe(&pdev->dev, -EINVAL,
845 "bad data bits %d\n", val);
846 }
847 } else {
848 pdata->baud = 9600;
849 pdata->cflags = CS8;
850 }
851
852 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
853 if (!res)
854 return -ENODEV;
855
856 irq = platform_get_irq(pdev, 0);
857 if (irq < 0)
858 return irq;
859
860 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
861 if (IS_ERR(pdata->clk)) {
862 if (PTR_ERR(pdata->clk) != -ENOENT)
863 return PTR_ERR(pdata->clk);
864
865 /*
866 * Clock framework support is optional, continue on
867 * anyways if we don't find a matching clock.
868 */
869 pdata->clk = NULL;
870 }
871
872 ret = clk_prepare_enable(pdata->clk);
873 if (ret) {
874 dev_err(&pdev->dev, "Failed to prepare clock\n");
875 return ret;
876 }
877
878 pm_runtime_use_autosuspend(&pdev->dev);
879 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
880 pm_runtime_set_active(&pdev->dev);
881 pm_runtime_get_noresume(&pdev->dev);
882 pm_runtime_enable(&pdev->dev);
883
884 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
885
886 pm_runtime_mark_last_busy(&pdev->dev);
887 pm_runtime_put_autosuspend(&pdev->dev);
888
889 return ret;
890}
891
892static void ulite_remove(struct platform_device *pdev)
893{
894 struct uart_port *port = dev_get_drvdata(&pdev->dev);
895 struct uartlite_data *pdata = port->private_data;
896
897 clk_disable_unprepare(pdata->clk);
898 ulite_release(&pdev->dev);
899 pm_runtime_disable(&pdev->dev);
900 pm_runtime_set_suspended(&pdev->dev);
901 pm_runtime_dont_use_autosuspend(&pdev->dev);
902}
903
904/* work with hotplug and coldplug */
905MODULE_ALIAS("platform:uartlite");
906
907static struct platform_driver ulite_platform_driver = {
908 .probe = ulite_probe,
909 .remove = ulite_remove,
910 .driver = {
911 .name = "uartlite",
912 .of_match_table = of_match_ptr(ulite_of_match),
913 .pm = &ulite_pm_ops,
914 },
915};
916
917/* ---------------------------------------------------------------------
918 * Module setup/teardown
919 */
920
921static int __init ulite_init(void)
922{
923 int ret;
924
925 pr_debug("uartlite: calling uart_register_driver()\n");
926 ret = uart_register_driver(&ulite_uart_driver);
927 if (ret)
928 return ret;
929
930 pr_debug("uartlite: calling platform_driver_register()\n");
931 ret = platform_driver_register(&ulite_platform_driver);
932 if (ret)
933 uart_unregister_driver(&ulite_uart_driver);
934
935 return ret;
936}
937
938static void __exit ulite_exit(void)
939{
940 platform_driver_unregister(&ulite_platform_driver);
941 uart_unregister_driver(&ulite_uart_driver);
942}
943
944module_init(ulite_init);
945module_exit(ulite_exit);
946
947MODULE_AUTHOR("Peter Korsgaard <[email protected]>");
948MODULE_DESCRIPTION("Xilinx uartlite serial driver");
949MODULE_LICENSE("GPL");