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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
7
8/*
9 * This file contains the functions to manage Queue Heads and Queue
10 * Transfer Descriptors for Host mode
11 */
12#include <linux/gcd.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/interrupt.h>
17#include <linux/dma-mapping.h>
18#include <linux/io.h>
19#include <linux/seq_buf.h>
20#include <linux/slab.h>
21#include <linux/usb.h>
22
23#include <linux/usb/hcd.h>
24#include <linux/usb/ch11.h>
25
26#include "core.h"
27#include "hcd.h"
28
29/* Wait this long before releasing periodic reservation */
30#define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
31
32/* If we get a NAK, wait this long before retrying */
33#define DWC2_RETRY_WAIT_DELAY (1 * NSEC_PER_MSEC)
34
35/**
36 * dwc2_periodic_channel_available() - Checks that a channel is available for a
37 * periodic transfer
38 *
39 * @hsotg: The HCD state structure for the DWC OTG controller
40 *
41 * Return: 0 if successful, negative error code otherwise
42 */
43static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
44{
45 /*
46 * Currently assuming that there is a dedicated host channel for
47 * each periodic transaction plus at least one host channel for
48 * non-periodic transactions
49 */
50 int status;
51 int num_channels;
52
53 num_channels = hsotg->params.host_channels;
54 if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
55 num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
56 status = 0;
57 } else {
58 dev_dbg(hsotg->dev,
59 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
60 __func__, num_channels,
61 hsotg->periodic_channels, hsotg->non_periodic_channels);
62 status = -ENOSPC;
63 }
64
65 return status;
66}
67
68/**
69 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
70 * for the specified QH in the periodic schedule
71 *
72 * @hsotg: The HCD state structure for the DWC OTG controller
73 * @qh: QH containing periodic bandwidth required
74 *
75 * Return: 0 if successful, negative error code otherwise
76 *
77 * For simplicity, this calculation assumes that all the transfers in the
78 * periodic schedule may occur in the same (micro)frame
79 */
80static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
81 struct dwc2_qh *qh)
82{
83 int status;
84 s16 max_claimed_usecs;
85
86 status = 0;
87
88 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
89 /*
90 * High speed mode
91 * Max periodic usecs is 80% x 125 usec = 100 usec
92 */
93 max_claimed_usecs = 100 - qh->host_us;
94 } else {
95 /*
96 * Full speed mode
97 * Max periodic usecs is 90% x 1000 usec = 900 usec
98 */
99 max_claimed_usecs = 900 - qh->host_us;
100 }
101
102 if (hsotg->periodic_usecs > max_claimed_usecs) {
103 dev_err(hsotg->dev,
104 "%s: already claimed usecs %d, required usecs %d\n",
105 __func__, hsotg->periodic_usecs, qh->host_us);
106 status = -ENOSPC;
107 }
108
109 return status;
110}
111
112/**
113 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
114 *
115 * @map: The bitmap representing the schedule; will be updated
116 * upon success.
117 * @bits_per_period: The schedule represents several periods. This is how many
118 * bits are in each period. It's assumed that the beginning
119 * of the schedule will repeat after its end.
120 * @periods_in_map: The number of periods in the schedule.
121 * @num_bits: The number of bits we need per period we want to reserve
122 * in this function call.
123 * @interval: How often we need to be scheduled for the reservation this
124 * time. 1 means every period. 2 means every other period.
125 * ...you get the picture?
126 * @start: The bit number to start at. Normally 0. Must be within
127 * the interval or we return failure right away.
128 * @only_one_period: Normally we'll allow picking a start anywhere within the
129 * first interval, since we can still make all repetition
130 * requirements by doing that. However, if you pass true
131 * here then we'll return failure if we can't fit within
132 * the period that "start" is in.
133 *
134 * The idea here is that we want to schedule time for repeating events that all
135 * want the same resource. The resource is divided into fixed-sized periods
136 * and the events want to repeat every "interval" periods. The schedule
137 * granularity is one bit.
138 *
139 * To keep things "simple", we'll represent our schedule with a bitmap that
140 * contains a fixed number of periods. This gets rid of a lot of complexity
141 * but does mean that we need to handle things specially (and non-ideally) if
142 * the number of the periods in the schedule doesn't match well with the
143 * intervals that we're trying to schedule.
144 *
145 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
146 * - If interval is 1, we need to take up space in each of the 8
147 * periods we're scheduling. Easy.
148 * - If interval is 2, we need to take up space in half of the
149 * periods. Again, easy.
150 * - If interval is 3, we actually need to fall back to interval 1.
151 * Why? Because we might need time in any period. AKA for the
152 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
153 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
154 * 0, 3, and 6. Since we could be in any frame we need to reserve
155 * for all of them. Sucks, but that's what you gotta do. Note that
156 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
157 * then we need more memory and time to do scheduling.
158 * - If interval is 4, easy.
159 * - If interval is 5, we again need interval 1. The schedule will be
160 * 0, 5, 2, 7, 4, 1, 6, 3, 0
161 * - If interval is 6, we need interval 2. 0, 6, 4, 2.
162 * - If interval is 7, we need interval 1.
163 * - If interval is 8, we need interval 8.
164 *
165 * If you do the math, you'll see that we need to pretend that interval is
166 * equal to the greatest_common_divisor(interval, periods_in_map).
167 *
168 * Note that at the moment this function tends to front-pack the schedule.
169 * In some cases that's really non-ideal (it's hard to schedule things that
170 * need to repeat every period). In other cases it's perfect (you can easily
171 * schedule bigger, less often repeating things).
172 *
173 * Here's the algorithm in action (8 periods, 5 bits per period):
174 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
175 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
176 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
177 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
178 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
179 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
180 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
181 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
182 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
183 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
184 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
185 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
186 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
187 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
188 * | | | | | | | | | Remv 1 bits, intv 1 at 4
189 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
190 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
191 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
192 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
193 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
194 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
195 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
196 *
197 * This function is pretty generic and could be easily abstracted if anything
198 * needed similar scheduling.
199 *
200 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
201 * unschedule routine. The map bitmap will be updated on a non-error result.
202 */
203static int pmap_schedule(unsigned long *map, int bits_per_period,
204 int periods_in_map, int num_bits,
205 int interval, int start, bool only_one_period)
206{
207 int interval_bits;
208 int to_reserve;
209 int first_end;
210 int i;
211
212 if (num_bits > bits_per_period)
213 return -ENOSPC;
214
215 /* Adjust interval as per description */
216 interval = gcd(interval, periods_in_map);
217
218 interval_bits = bits_per_period * interval;
219 to_reserve = periods_in_map / interval;
220
221 /* If start has gotten us past interval then we can't schedule */
222 if (start >= interval_bits)
223 return -ENOSPC;
224
225 if (only_one_period)
226 /* Must fit within same period as start; end at begin of next */
227 first_end = (start / bits_per_period + 1) * bits_per_period;
228 else
229 /* Can fit anywhere in the first interval */
230 first_end = interval_bits;
231
232 /*
233 * We'll try to pick the first repetition, then see if that time
234 * is free for each of the subsequent repetitions. If it's not
235 * we'll adjust the start time for the next search of the first
236 * repetition.
237 */
238 while (start + num_bits <= first_end) {
239 int end;
240
241 /* Need to stay within this period */
242 end = (start / bits_per_period + 1) * bits_per_period;
243
244 /* Look for num_bits us in this microframe starting at start */
245 start = bitmap_find_next_zero_area(map, end, start, num_bits,
246 0);
247
248 /*
249 * We should get start >= end if we fail. We might be
250 * able to check the next microframe depending on the
251 * interval, so continue on (start already updated).
252 */
253 if (start >= end) {
254 start = end;
255 continue;
256 }
257
258 /* At this point we have a valid point for first one */
259 for (i = 1; i < to_reserve; i++) {
260 int ith_start = start + interval_bits * i;
261 int ith_end = end + interval_bits * i;
262 int ret;
263
264 /* Use this as a dumb "check if bits are 0" */
265 ret = bitmap_find_next_zero_area(
266 map, ith_start + num_bits, ith_start, num_bits,
267 0);
268
269 /* We got the right place, continue checking */
270 if (ret == ith_start)
271 continue;
272
273 /* Move start up for next time and exit for loop */
274 ith_start = bitmap_find_next_zero_area(
275 map, ith_end, ith_start, num_bits, 0);
276 if (ith_start >= ith_end)
277 /* Need a while new period next time */
278 start = end;
279 else
280 start = ith_start - interval_bits * i;
281 break;
282 }
283
284 /* If didn't exit the for loop with a break, we have success */
285 if (i == to_reserve)
286 break;
287 }
288
289 if (start + num_bits > first_end)
290 return -ENOSPC;
291
292 for (i = 0; i < to_reserve; i++) {
293 int ith_start = start + interval_bits * i;
294
295 bitmap_set(map, ith_start, num_bits);
296 }
297
298 return start;
299}
300
301/**
302 * pmap_unschedule() - Undo work done by pmap_schedule()
303 *
304 * @map: See pmap_schedule().
305 * @bits_per_period: See pmap_schedule().
306 * @periods_in_map: See pmap_schedule().
307 * @num_bits: The number of bits that was passed to schedule.
308 * @interval: The interval that was passed to schedule.
309 * @start: The return value from pmap_schedule().
310 */
311static void pmap_unschedule(unsigned long *map, int bits_per_period,
312 int periods_in_map, int num_bits,
313 int interval, int start)
314{
315 int interval_bits;
316 int to_release;
317 int i;
318
319 /* Adjust interval as per description in pmap_schedule() */
320 interval = gcd(interval, periods_in_map);
321
322 interval_bits = bits_per_period * interval;
323 to_release = periods_in_map / interval;
324
325 for (i = 0; i < to_release; i++) {
326 int ith_start = start + interval_bits * i;
327
328 bitmap_clear(map, ith_start, num_bits);
329 }
330}
331
332/**
333 * dwc2_get_ls_map() - Get the map used for the given qh
334 *
335 * @hsotg: The HCD state structure for the DWC OTG controller.
336 * @qh: QH for the periodic transfer.
337 *
338 * We'll always get the periodic map out of our TT. Note that even if we're
339 * running the host straight in low speed / full speed mode it appears as if
340 * a TT is allocated for us, so we'll use it. If that ever changes we can
341 * add logic here to get a map out of "hsotg" if !qh->do_split.
342 *
343 * Returns: the map or NULL if a map couldn't be found.
344 */
345static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
346 struct dwc2_qh *qh)
347{
348 unsigned long *map;
349
350 /* Don't expect to be missing a TT and be doing low speed scheduling */
351 if (WARN_ON(!qh->dwc_tt))
352 return NULL;
353
354 /* Get the map and adjust if this is a multi_tt hub */
355 map = qh->dwc_tt->periodic_bitmaps;
356 if (qh->dwc_tt->usb_tt->multi)
357 map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1);
358
359 return map;
360}
361
362#ifdef DWC2_PRINT_SCHEDULE
363/*
364 * pmap_print() - Print the given periodic map
365 *
366 * Will attempt to print out the periodic schedule.
367 *
368 * @map: See pmap_schedule().
369 * @bits_per_period: See pmap_schedule().
370 * @periods_in_map: See pmap_schedule().
371 * @period_name: The name of 1 period, like "uFrame"
372 * @units: The name of the units, like "us".
373 * @print_fn: The function to call for printing.
374 * @print_data: Opaque data to pass to the print function.
375 */
376static void pmap_print(unsigned long *map, int bits_per_period,
377 int periods_in_map, const char *period_name,
378 const char *units,
379 void (*print_fn)(const char *str, void *data),
380 void *print_data)
381{
382 int period;
383
384 for (period = 0; period < periods_in_map; period++) {
385 DECLARE_SEQ_BUF(buf, 64);
386 int period_start = period * bits_per_period;
387 int period_end = period_start + bits_per_period;
388 int start = 0;
389 int count = 0;
390 bool printed = false;
391 int i;
392
393 for (i = period_start; i < period_end + 1; i++) {
394 /* Handle case when ith bit is set */
395 if (i < period_end &&
396 bitmap_find_next_zero_area(map, i + 1,
397 i, 1, 0) != i) {
398 if (count == 0)
399 start = i - period_start;
400 count++;
401 continue;
402 }
403
404 /* ith bit isn't set; don't care if count == 0 */
405 if (count == 0)
406 continue;
407
408 if (!printed)
409 seq_buf_printf(&buf, "%s %d: ",
410 period_name, period);
411 else
412 seq_buf_puts(&buf, ", ");
413 printed = true;
414
415 seq_buf_printf(&buf, "%d %s -%3d %s", start,
416 units, start + count - 1, units);
417 count = 0;
418 }
419
420 if (printed)
421 print_fn(seq_buf_str(&buf), print_data);
422 }
423}
424
425struct dwc2_qh_print_data {
426 struct dwc2_hsotg *hsotg;
427 struct dwc2_qh *qh;
428};
429
430/**
431 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
432 *
433 * @str: The string to print
434 * @data: A pointer to a struct dwc2_qh_print_data
435 */
436static void dwc2_qh_print(const char *str, void *data)
437{
438 struct dwc2_qh_print_data *print_data = data;
439
440 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
441}
442
443/**
444 * dwc2_qh_schedule_print() - Print the periodic schedule
445 *
446 * @hsotg: The HCD state structure for the DWC OTG controller.
447 * @qh: QH to print.
448 */
449static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
450 struct dwc2_qh *qh)
451{
452 struct dwc2_qh_print_data print_data = { hsotg, qh };
453 int i;
454
455 /*
456 * The printing functions are quite slow and inefficient.
457 * If we don't have tracing turned on, don't run unless the special
458 * define is turned on.
459 */
460
461 if (qh->schedule_low_speed) {
462 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
463
464 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
465 qh, qh->device_us,
466 DWC2_ROUND_US_TO_SLICE(qh->device_us),
467 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
468
469 if (map) {
470 dwc2_sch_dbg(hsotg,
471 "QH=%p Whole low/full speed map %p now:\n",
472 qh, map);
473 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
474 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
475 dwc2_qh_print, &print_data);
476 }
477 }
478
479 for (i = 0; i < qh->num_hs_transfers; i++) {
480 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
481 int uframe = trans_time->start_schedule_us /
482 DWC2_HS_PERIODIC_US_PER_UFRAME;
483 int rel_us = trans_time->start_schedule_us %
484 DWC2_HS_PERIODIC_US_PER_UFRAME;
485
486 dwc2_sch_dbg(hsotg,
487 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
488 qh, i, trans_time->duration_us, uframe, rel_us);
489 }
490 if (qh->num_hs_transfers) {
491 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
492 pmap_print(hsotg->hs_periodic_bitmap,
493 DWC2_HS_PERIODIC_US_PER_UFRAME,
494 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
495 dwc2_qh_print, &print_data);
496 }
497}
498#else
499static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
500 struct dwc2_qh *qh) {};
501#endif
502
503/**
504 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
505 *
506 * @hsotg: The HCD state structure for the DWC OTG controller.
507 * @qh: QH for the periodic transfer.
508 * @search_slice: We'll start trying to schedule at the passed slice.
509 * Remember that slices are the units of the low speed
510 * schedule (think 25us or so).
511 *
512 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
513 *
514 * Normally we schedule low speed devices on the map associated with the TT.
515 *
516 * Returns: 0 for success or an error code.
517 */
518static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
519 int search_slice)
520{
521 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
522 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
523 int slice;
524
525 if (!map)
526 return -EINVAL;
527
528 /*
529 * Schedule on the proper low speed map with our low speed scheduling
530 * parameters. Note that we use the "device_interval" here since
531 * we want the low speed interval and the only way we'd be in this
532 * function is if the device is low speed.
533 *
534 * If we happen to be doing low speed and high speed scheduling for the
535 * same transaction (AKA we have a split) we always do low speed first.
536 * That means we can always pass "false" for only_one_period (that
537 * parameters is only useful when we're trying to get one schedule to
538 * match what we already planned in the other schedule).
539 */
540 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
541 DWC2_LS_SCHEDULE_FRAMES, slices,
542 qh->device_interval, search_slice, false);
543
544 if (slice < 0)
545 return slice;
546
547 qh->ls_start_schedule_slice = slice;
548 return 0;
549}
550
551/**
552 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
553 *
554 * @hsotg: The HCD state structure for the DWC OTG controller.
555 * @qh: QH for the periodic transfer.
556 */
557static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
558 struct dwc2_qh *qh)
559{
560 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
561 unsigned long *map = dwc2_get_ls_map(hsotg, qh);
562
563 /* Schedule should have failed, so no worries about no error code */
564 if (!map)
565 return;
566
567 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
568 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
569 qh->ls_start_schedule_slice);
570}
571
572/**
573 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
574 *
575 * This will schedule something on the main dwc2 schedule.
576 *
577 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
578 * update this with the result upon success. We also use the duration from
579 * the same structure.
580 *
581 * @hsotg: The HCD state structure for the DWC OTG controller.
582 * @qh: QH for the periodic transfer.
583 * @only_one_period: If true we will limit ourselves to just looking at
584 * one period (aka one 100us chunk). This is used if we have
585 * already scheduled something on the low speed schedule and
586 * need to find something that matches on the high speed one.
587 * @index: The index into qh->hs_transfers that we're working with.
588 *
589 * Returns: 0 for success or an error code. Upon success the
590 * dwc2_hs_transfer_time specified by "index" will be updated.
591 */
592static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
593 bool only_one_period, int index)
594{
595 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
596 int us;
597
598 us = pmap_schedule(hsotg->hs_periodic_bitmap,
599 DWC2_HS_PERIODIC_US_PER_UFRAME,
600 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
601 qh->host_interval, trans_time->start_schedule_us,
602 only_one_period);
603
604 if (us < 0)
605 return us;
606
607 trans_time->start_schedule_us = us;
608 return 0;
609}
610
611/**
612 * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
613 *
614 * @hsotg: The HCD state structure for the DWC OTG controller.
615 * @qh: QH for the periodic transfer.
616 * @index: Transfer index
617 */
618static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
619 struct dwc2_qh *qh, int index)
620{
621 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
622
623 pmap_unschedule(hsotg->hs_periodic_bitmap,
624 DWC2_HS_PERIODIC_US_PER_UFRAME,
625 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
626 qh->host_interval, trans_time->start_schedule_us);
627}
628
629/**
630 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
631 *
632 * This is the most complicated thing in USB. We have to find matching time
633 * in both the global high speed schedule for the port and the low speed
634 * schedule for the TT associated with the given device.
635 *
636 * Being here means that the host must be running in high speed mode and the
637 * device is in low or full speed mode (and behind a hub).
638 *
639 * @hsotg: The HCD state structure for the DWC OTG controller.
640 * @qh: QH for the periodic transfer.
641 */
642static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
643 struct dwc2_qh *qh)
644{
645 int bytecount = qh->maxp_mult * qh->maxp;
646 int ls_search_slice;
647 int err = 0;
648 int host_interval_in_sched;
649
650 /*
651 * The interval (how often to repeat) in the actual host schedule.
652 * See pmap_schedule() for gcd() explanation.
653 */
654 host_interval_in_sched = gcd(qh->host_interval,
655 DWC2_HS_SCHEDULE_UFRAMES);
656
657 /*
658 * We always try to find space in the low speed schedule first, then
659 * try to find high speed time that matches. If we don't, we'll bump
660 * up the place we start searching in the low speed schedule and try
661 * again. To start we'll look right at the beginning of the low speed
662 * schedule.
663 *
664 * Note that this will tend to front-load the high speed schedule.
665 * We may eventually want to try to avoid this by either considering
666 * both schedules together or doing some sort of round robin.
667 */
668 ls_search_slice = 0;
669
670 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
671 int start_s_uframe;
672 int ssplit_s_uframe;
673 int second_s_uframe;
674 int rel_uframe;
675 int first_count;
676 int middle_count;
677 int end_count;
678 int first_data_bytes;
679 int other_data_bytes;
680 int i;
681
682 if (qh->schedule_low_speed) {
683 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
684
685 /*
686 * If we got an error here there's no other magic we
687 * can do, so bail. All the looping above is only
688 * helpful to redo things if we got a low speed slot
689 * and then couldn't find a matching high speed slot.
690 */
691 if (err)
692 return err;
693 } else {
694 /* Must be missing the tt structure? Why? */
695 WARN_ON_ONCE(1);
696 }
697
698 /*
699 * This will give us a number 0 - 7 if
700 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
701 */
702 start_s_uframe = qh->ls_start_schedule_slice /
703 DWC2_SLICES_PER_UFRAME;
704
705 /* Get a number that's always 0 - 7 */
706 rel_uframe = (start_s_uframe % 8);
707
708 /*
709 * If we were going to start in uframe 7 then we would need to
710 * issue a start split in uframe 6, which spec says is not OK.
711 * Move on to the next full frame (assuming there is one).
712 *
713 * See 11.18.4 Host Split Transaction Scheduling Requirements
714 * bullet 1.
715 */
716 if (rel_uframe == 7) {
717 if (qh->schedule_low_speed)
718 dwc2_ls_pmap_unschedule(hsotg, qh);
719 ls_search_slice =
720 (qh->ls_start_schedule_slice /
721 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
722 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
723 continue;
724 }
725
726 /*
727 * For ISOC in:
728 * - start split (frame -1)
729 * - complete split w/ data (frame +1)
730 * - complete split w/ data (frame +2)
731 * - ...
732 * - complete split w/ data (frame +num_data_packets)
733 * - complete split w/ data (frame +num_data_packets+1)
734 * - complete split w/ data (frame +num_data_packets+2, max 8)
735 * ...though if frame was "0" then max is 7...
736 *
737 * For ISOC out we might need to do:
738 * - start split w/ data (frame -1)
739 * - start split w/ data (frame +0)
740 * - ...
741 * - start split w/ data (frame +num_data_packets-2)
742 *
743 * For INTERRUPT in we might need to do:
744 * - start split (frame -1)
745 * - complete split w/ data (frame +1)
746 * - complete split w/ data (frame +2)
747 * - complete split w/ data (frame +3, max 8)
748 *
749 * For INTERRUPT out we might need to do:
750 * - start split w/ data (frame -1)
751 * - complete split (frame +1)
752 * - complete split (frame +2)
753 * - complete split (frame +3, max 8)
754 *
755 * Start adjusting!
756 */
757 ssplit_s_uframe = (start_s_uframe +
758 host_interval_in_sched - 1) %
759 host_interval_in_sched;
760 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
761 second_s_uframe = start_s_uframe;
762 else
763 second_s_uframe = start_s_uframe + 1;
764
765 /* First data transfer might not be all 188 bytes. */
766 first_data_bytes = 188 -
767 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
768 DWC2_SLICES_PER_UFRAME),
769 DWC2_SLICES_PER_UFRAME);
770 if (first_data_bytes > bytecount)
771 first_data_bytes = bytecount;
772 other_data_bytes = bytecount - first_data_bytes;
773
774 /*
775 * For now, skip OUT xfers where first xfer is partial
776 *
777 * Main dwc2 code assumes:
778 * - INT transfers never get split in two.
779 * - ISOC transfers can always transfer 188 bytes the first
780 * time.
781 *
782 * Until that code is fixed, try again if the first transfer
783 * couldn't transfer everything.
784 *
785 * This code can be removed if/when the rest of dwc2 handles
786 * the above cases. Until it's fixed we just won't be able
787 * to schedule quite as tightly.
788 */
789 if (!qh->ep_is_in &&
790 (first_data_bytes != min_t(int, 188, bytecount))) {
791 dwc2_sch_dbg(hsotg,
792 "QH=%p avoiding broken 1st xfer (%d, %d)\n",
793 qh, first_data_bytes, bytecount);
794 if (qh->schedule_low_speed)
795 dwc2_ls_pmap_unschedule(hsotg, qh);
796 ls_search_slice = (start_s_uframe + 1) *
797 DWC2_SLICES_PER_UFRAME;
798 continue;
799 }
800
801 /* Start by assuming transfers for the bytes */
802 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
803
804 /*
805 * Everything except ISOC OUT has extra transfers. Rules are
806 * complicated. See 11.18.4 Host Split Transaction Scheduling
807 * Requirements bullet 3.
808 */
809 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
810 if (rel_uframe == 6)
811 qh->num_hs_transfers += 2;
812 else
813 qh->num_hs_transfers += 3;
814
815 if (qh->ep_is_in) {
816 /*
817 * First is start split, middle/end is data.
818 * Allocate full data bytes for all data.
819 */
820 first_count = 4;
821 middle_count = bytecount;
822 end_count = bytecount;
823 } else {
824 /*
825 * First is data, middle/end is complete.
826 * First transfer and second can have data.
827 * Rest should just have complete split.
828 */
829 first_count = first_data_bytes;
830 middle_count = max_t(int, 4, other_data_bytes);
831 end_count = 4;
832 }
833 } else {
834 if (qh->ep_is_in) {
835 int last;
836
837 /* Account for the start split */
838 qh->num_hs_transfers++;
839
840 /* Calculate "L" value from spec */
841 last = rel_uframe + qh->num_hs_transfers + 1;
842
843 /* Start with basic case */
844 if (last <= 6)
845 qh->num_hs_transfers += 2;
846 else
847 qh->num_hs_transfers += 1;
848
849 /* Adjust downwards */
850 if (last >= 6 && rel_uframe == 0)
851 qh->num_hs_transfers--;
852
853 /* 1st = start; rest can contain data */
854 first_count = 4;
855 middle_count = min_t(int, 188, bytecount);
856 end_count = middle_count;
857 } else {
858 /* All contain data, last might be smaller */
859 first_count = first_data_bytes;
860 middle_count = min_t(int, 188,
861 other_data_bytes);
862 end_count = other_data_bytes % 188;
863 }
864 }
865
866 /* Assign durations per uFrame */
867 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
868 for (i = 1; i < qh->num_hs_transfers - 1; i++)
869 qh->hs_transfers[i].duration_us =
870 HS_USECS_ISO(middle_count);
871 if (qh->num_hs_transfers > 1)
872 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
873 HS_USECS_ISO(end_count);
874
875 /*
876 * Assign start us. The call below to dwc2_hs_pmap_schedule()
877 * will start with these numbers but may adjust within the same
878 * microframe.
879 */
880 qh->hs_transfers[0].start_schedule_us =
881 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
882 for (i = 1; i < qh->num_hs_transfers; i++)
883 qh->hs_transfers[i].start_schedule_us =
884 ((second_s_uframe + i - 1) %
885 DWC2_HS_SCHEDULE_UFRAMES) *
886 DWC2_HS_PERIODIC_US_PER_UFRAME;
887
888 /* Try to schedule with filled in hs_transfers above */
889 for (i = 0; i < qh->num_hs_transfers; i++) {
890 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
891 if (err)
892 break;
893 }
894
895 /* If we scheduled all w/out breaking out then we're all good */
896 if (i == qh->num_hs_transfers)
897 break;
898
899 for (; i >= 0; i--)
900 dwc2_hs_pmap_unschedule(hsotg, qh, i);
901
902 if (qh->schedule_low_speed)
903 dwc2_ls_pmap_unschedule(hsotg, qh);
904
905 /* Try again starting in the next microframe */
906 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
907 }
908
909 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
910 return -ENOSPC;
911
912 return 0;
913}
914
915/**
916 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
917 *
918 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
919 * interface.
920 *
921 * @hsotg: The HCD state structure for the DWC OTG controller.
922 * @qh: QH for the periodic transfer.
923 */
924static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
925{
926 /* In non-split host and device time are the same */
927 WARN_ON(qh->host_us != qh->device_us);
928 WARN_ON(qh->host_interval != qh->device_interval);
929 WARN_ON(qh->num_hs_transfers != 1);
930
931 /* We'll have one transfer; init start to 0 before calling scheduler */
932 qh->hs_transfers[0].start_schedule_us = 0;
933 qh->hs_transfers[0].duration_us = qh->host_us;
934
935 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
936}
937
938/**
939 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
940 *
941 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
942 * interface.
943 *
944 * @hsotg: The HCD state structure for the DWC OTG controller.
945 * @qh: QH for the periodic transfer.
946 */
947static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
948{
949 /* In non-split host and device time are the same */
950 WARN_ON(qh->host_us != qh->device_us);
951 WARN_ON(qh->host_interval != qh->device_interval);
952 WARN_ON(!qh->schedule_low_speed);
953
954 /* Run on the main low speed schedule (no split = no hub = no TT) */
955 return dwc2_ls_pmap_schedule(hsotg, qh, 0);
956}
957
958/**
959 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
960 *
961 * Calls one of the 3 sub-function depending on what type of transfer this QH
962 * is for. Also adds some printing.
963 *
964 * @hsotg: The HCD state structure for the DWC OTG controller.
965 * @qh: QH for the periodic transfer.
966 */
967static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
968{
969 int ret;
970
971 if (qh->dev_speed == USB_SPEED_HIGH)
972 ret = dwc2_uframe_schedule_hs(hsotg, qh);
973 else if (!qh->do_split)
974 ret = dwc2_uframe_schedule_ls(hsotg, qh);
975 else
976 ret = dwc2_uframe_schedule_split(hsotg, qh);
977
978 if (ret)
979 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
980 else
981 dwc2_qh_schedule_print(hsotg, qh);
982
983 return ret;
984}
985
986/**
987 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
988 *
989 * @hsotg: The HCD state structure for the DWC OTG controller.
990 * @qh: QH for the periodic transfer.
991 */
992static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
993{
994 int i;
995
996 for (i = 0; i < qh->num_hs_transfers; i++)
997 dwc2_hs_pmap_unschedule(hsotg, qh, i);
998
999 if (qh->schedule_low_speed)
1000 dwc2_ls_pmap_unschedule(hsotg, qh);
1001
1002 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1003}
1004
1005/**
1006 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1007 *
1008 * Takes a qh that has already been scheduled (which means we know we have the
1009 * bandwdith reserved for us) and set the next_active_frame and the
1010 * start_active_frame.
1011 *
1012 * This is expected to be called on qh's that weren't previously actively
1013 * running. It just picks the next frame that we can fit into without any
1014 * thought about the past.
1015 *
1016 * @hsotg: The HCD state structure for the DWC OTG controller
1017 * @qh: QH for a periodic endpoint
1018 *
1019 */
1020static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1021{
1022 u16 frame_number;
1023 u16 earliest_frame;
1024 u16 next_active_frame;
1025 u16 relative_frame;
1026 u16 interval;
1027
1028 /*
1029 * Use the real frame number rather than the cached value as of the
1030 * last SOF to give us a little extra slop.
1031 */
1032 frame_number = dwc2_hcd_get_frame_number(hsotg);
1033
1034 /*
1035 * We wouldn't want to start any earlier than the next frame just in
1036 * case the frame number ticks as we're doing this calculation.
1037 *
1038 * NOTE: if we could quantify how long till we actually get scheduled
1039 * we might be able to avoid the "+ 1" by looking at the upper part of
1040 * HFNUM (the FRREM field). For now we'll just use the + 1 though.
1041 */
1042 earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1043 next_active_frame = earliest_frame;
1044
1045 /* Get the "no microframe scheduler" out of the way... */
1046 if (!hsotg->params.uframe_sched) {
1047 if (qh->do_split)
1048 /* Splits are active at microframe 0 minus 1 */
1049 next_active_frame |= 0x7;
1050 goto exit;
1051 }
1052
1053 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
1054 /*
1055 * We're either at high speed or we're doing a split (which
1056 * means we're talking high speed to a hub). In any case
1057 * the first frame should be based on when the first scheduled
1058 * event is.
1059 */
1060 WARN_ON(qh->num_hs_transfers < 1);
1061
1062 relative_frame = qh->hs_transfers[0].start_schedule_us /
1063 DWC2_HS_PERIODIC_US_PER_UFRAME;
1064
1065 /* Adjust interval as per high speed schedule */
1066 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1067
1068 } else {
1069 /*
1070 * Low or full speed directly on dwc2. Just about the same
1071 * as high speed but on a different schedule and with slightly
1072 * different adjustments. Note that this works because when
1073 * the host and device are both low speed then frames in the
1074 * controller tick at low speed.
1075 */
1076 relative_frame = qh->ls_start_schedule_slice /
1077 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1078 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1079 }
1080
1081 /* Scheduler messed up if frame is past interval */
1082 WARN_ON(relative_frame >= interval);
1083
1084 /*
1085 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1086 * done the gcd(), so it's safe to move to the beginning of the current
1087 * interval like this.
1088 *
1089 * After this we might be before earliest_frame, but don't worry,
1090 * we'll fix it...
1091 */
1092 next_active_frame = (next_active_frame / interval) * interval;
1093
1094 /*
1095 * Actually choose to start at the frame number we've been
1096 * scheduled for.
1097 */
1098 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1099 relative_frame);
1100
1101 /*
1102 * We actually need 1 frame before since the next_active_frame is
1103 * the frame number we'll be put on the ready list and we won't be on
1104 * the bus until 1 frame later.
1105 */
1106 next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1107
1108 /*
1109 * By now we might actually be before the earliest_frame. Let's move
1110 * up intervals until we're not.
1111 */
1112 while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1113 next_active_frame = dwc2_frame_num_inc(next_active_frame,
1114 interval);
1115
1116exit:
1117 qh->next_active_frame = next_active_frame;
1118 qh->start_active_frame = next_active_frame;
1119
1120 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1121 qh, frame_number, qh->next_active_frame);
1122}
1123
1124/**
1125 * dwc2_do_reserve() - Make a periodic reservation
1126 *
1127 * Try to allocate space in the periodic schedule. Depending on parameters
1128 * this might use the microframe scheduler or the dumb scheduler.
1129 *
1130 * @hsotg: The HCD state structure for the DWC OTG controller
1131 * @qh: QH for the periodic transfer.
1132 *
1133 * Returns: 0 upon success; error upon failure.
1134 */
1135static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1136{
1137 int status;
1138
1139 if (hsotg->params.uframe_sched) {
1140 status = dwc2_uframe_schedule(hsotg, qh);
1141 } else {
1142 status = dwc2_periodic_channel_available(hsotg);
1143 if (status) {
1144 dev_info(hsotg->dev,
1145 "%s: No host channel available for periodic transfer\n",
1146 __func__);
1147 return status;
1148 }
1149
1150 status = dwc2_check_periodic_bandwidth(hsotg, qh);
1151 }
1152
1153 if (status) {
1154 dev_dbg(hsotg->dev,
1155 "%s: Insufficient periodic bandwidth for periodic transfer\n",
1156 __func__);
1157 return status;
1158 }
1159
1160 if (!hsotg->params.uframe_sched)
1161 /* Reserve periodic channel */
1162 hsotg->periodic_channels++;
1163
1164 /* Update claimed usecs per (micro)frame */
1165 hsotg->periodic_usecs += qh->host_us;
1166
1167 dwc2_pick_first_frame(hsotg, qh);
1168
1169 return 0;
1170}
1171
1172/**
1173 * dwc2_do_unreserve() - Actually release the periodic reservation
1174 *
1175 * This function actually releases the periodic bandwidth that was reserved
1176 * by the given qh.
1177 *
1178 * @hsotg: The HCD state structure for the DWC OTG controller
1179 * @qh: QH for the periodic transfer.
1180 */
1181static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1182{
1183 assert_spin_locked(&hsotg->lock);
1184
1185 WARN_ON(!qh->unreserve_pending);
1186
1187 /* No more unreserve pending--we're doing it */
1188 qh->unreserve_pending = false;
1189
1190 if (WARN_ON(!list_empty(&qh->qh_list_entry)))
1191 list_del_init(&qh->qh_list_entry);
1192
1193 /* Update claimed usecs per (micro)frame */
1194 hsotg->periodic_usecs -= qh->host_us;
1195
1196 if (hsotg->params.uframe_sched) {
1197 dwc2_uframe_unschedule(hsotg, qh);
1198 } else {
1199 /* Release periodic channel reservation */
1200 hsotg->periodic_channels--;
1201 }
1202}
1203
1204/**
1205 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1206 *
1207 * According to the kernel doc for usb_submit_urb() (specifically the part about
1208 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1209 * long as a device driver keeps submitting. Since we're using HCD_BH to give
1210 * back the URB we need to give the driver a little bit of time before we
1211 * release the reservation. This worker is called after the appropriate
1212 * delay.
1213 *
1214 * @t: Address to a qh unreserve_work.
1215 */
1216static void dwc2_unreserve_timer_fn(struct timer_list *t)
1217{
1218 struct dwc2_qh *qh = timer_container_of(qh, t, unreserve_timer);
1219 struct dwc2_hsotg *hsotg = qh->hsotg;
1220 unsigned long flags;
1221
1222 /*
1223 * Wait for the lock, or for us to be scheduled again. We
1224 * could be scheduled again if:
1225 * - We started executing but didn't get the lock yet.
1226 * - A new reservation came in, but cancel didn't take effect
1227 * because we already started executing.
1228 * - The timer has been kicked again.
1229 * In that case cancel and wait for the next call.
1230 */
1231 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1232 if (timer_pending(&qh->unreserve_timer))
1233 return;
1234 }
1235
1236 /*
1237 * Might be no more unreserve pending if:
1238 * - We started executing but didn't get the lock yet.
1239 * - A new reservation came in, but cancel didn't take effect
1240 * because we already started executing.
1241 *
1242 * We can't put this in the loop above because unreserve_pending needs
1243 * to be accessed under lock, so we can only check it once we got the
1244 * lock.
1245 */
1246 if (qh->unreserve_pending)
1247 dwc2_do_unreserve(hsotg, qh);
1248
1249 spin_unlock_irqrestore(&hsotg->lock, flags);
1250}
1251
1252/**
1253 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1254 * host channel is large enough to handle the maximum data transfer in a single
1255 * (micro)frame for a periodic transfer
1256 *
1257 * @hsotg: The HCD state structure for the DWC OTG controller
1258 * @qh: QH for a periodic endpoint
1259 *
1260 * Return: 0 if successful, negative error code otherwise
1261 */
1262static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1263 struct dwc2_qh *qh)
1264{
1265 u32 max_xfer_size;
1266 u32 max_channel_xfer_size;
1267 int status = 0;
1268
1269 max_xfer_size = qh->maxp * qh->maxp_mult;
1270 max_channel_xfer_size = hsotg->params.max_transfer_size;
1271
1272 if (max_xfer_size > max_channel_xfer_size) {
1273 dev_err(hsotg->dev,
1274 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
1275 __func__, max_xfer_size, max_channel_xfer_size);
1276 status = -ENOSPC;
1277 }
1278
1279 return status;
1280}
1281
1282/**
1283 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1284 * the periodic schedule
1285 *
1286 * @hsotg: The HCD state structure for the DWC OTG controller
1287 * @qh: QH for the periodic transfer. The QH should already contain the
1288 * scheduling information.
1289 *
1290 * Return: 0 if successful, negative error code otherwise
1291 */
1292static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1293{
1294 int status;
1295
1296 status = dwc2_check_max_xfer_size(hsotg, qh);
1297 if (status) {
1298 dev_dbg(hsotg->dev,
1299 "%s: Channel max transfer size too small for periodic transfer\n",
1300 __func__);
1301 return status;
1302 }
1303
1304 /* Cancel pending unreserve; if canceled OK, unreserve was pending */
1305 if (timer_delete(&qh->unreserve_timer))
1306 WARN_ON(!qh->unreserve_pending);
1307
1308 /*
1309 * Only need to reserve if there's not an unreserve pending, since if an
1310 * unreserve is pending then by definition our old reservation is still
1311 * valid. Unreserve might still be pending even if we didn't cancel if
1312 * dwc2_unreserve_timer_fn() already started. Code in the timer handles
1313 * that case.
1314 */
1315 if (!qh->unreserve_pending) {
1316 status = dwc2_do_reserve(hsotg, qh);
1317 if (status)
1318 return status;
1319 } else {
1320 /*
1321 * It might have been a while, so make sure that frame_number
1322 * is still good. Note: we could also try to use the similar
1323 * dwc2_next_periodic_start() but that schedules much more
1324 * tightly and we might need to hurry and queue things up.
1325 */
1326 if (dwc2_frame_num_le(qh->next_active_frame,
1327 hsotg->frame_number))
1328 dwc2_pick_first_frame(hsotg, qh);
1329 }
1330
1331 qh->unreserve_pending = 0;
1332
1333 if (hsotg->params.dma_desc_enable)
1334 /* Don't rely on SOF and start in ready schedule */
1335 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1336 else
1337 /* Always start in inactive schedule */
1338 list_add_tail(&qh->qh_list_entry,
1339 &hsotg->periodic_sched_inactive);
1340
1341 return 0;
1342}
1343
1344/**
1345 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1346 * from the periodic schedule
1347 *
1348 * @hsotg: The HCD state structure for the DWC OTG controller
1349 * @qh: QH for the periodic transfer
1350 */
1351static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1352 struct dwc2_qh *qh)
1353{
1354 bool did_modify;
1355
1356 assert_spin_locked(&hsotg->lock);
1357
1358 /*
1359 * Schedule the unreserve to happen in a little bit. Cases here:
1360 * - Unreserve worker might be sitting there waiting to grab the lock.
1361 * In this case it will notice it's been schedule again and will
1362 * quit.
1363 * - Unreserve worker might not be scheduled.
1364 *
1365 * We should never already be scheduled since dwc2_schedule_periodic()
1366 * should have canceled the scheduled unreserve timer (hence the
1367 * warning on did_modify).
1368 *
1369 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1370 * passed (otherwise if the jiffy counter might tick right after we
1371 * read it and we'll get no delay).
1372 */
1373 did_modify = mod_timer(&qh->unreserve_timer,
1374 jiffies + DWC2_UNRESERVE_DELAY + 1);
1375 WARN_ON(did_modify);
1376 qh->unreserve_pending = 1;
1377
1378 list_del_init(&qh->qh_list_entry);
1379}
1380
1381/**
1382 * dwc2_wait_timer_fn() - Timer function to re-queue after waiting
1383 *
1384 * As per the spec, a NAK indicates that "a function is temporarily unable to
1385 * transmit or receive data, but will eventually be able to do so without need
1386 * of host intervention".
1387 *
1388 * That means that when we encounter a NAK we're supposed to retry.
1389 *
1390 * ...but if we retry right away (from the interrupt handler that saw the NAK)
1391 * then we can end up with an interrupt storm (if the other side keeps NAKing
1392 * us) because on slow enough CPUs it could take us longer to get out of the
1393 * interrupt routine than it takes for the device to send another NAK. That
1394 * leads to a constant stream of NAK interrupts and the CPU locks.
1395 *
1396 * ...so instead of retrying right away in the case of a NAK we'll set a timer
1397 * to retry some time later. This function handles that timer and moves the
1398 * qh back to the "inactive" list, then queues transactions.
1399 *
1400 * @t: Pointer to wait_timer in a qh.
1401 *
1402 * Return: HRTIMER_NORESTART to not automatically restart this timer.
1403 */
1404static enum hrtimer_restart dwc2_wait_timer_fn(struct hrtimer *t)
1405{
1406 struct dwc2_qh *qh = container_of(t, struct dwc2_qh, wait_timer);
1407 struct dwc2_hsotg *hsotg = qh->hsotg;
1408 unsigned long flags;
1409
1410 spin_lock_irqsave(&hsotg->lock, flags);
1411
1412 /*
1413 * We'll set wait_timer_cancel to true if we want to cancel this
1414 * operation in dwc2_hcd_qh_unlink().
1415 */
1416 if (!qh->wait_timer_cancel) {
1417 enum dwc2_transaction_type tr_type;
1418
1419 qh->want_wait = false;
1420
1421 list_move(&qh->qh_list_entry,
1422 &hsotg->non_periodic_sched_inactive);
1423
1424 tr_type = dwc2_hcd_select_transactions(hsotg);
1425 if (tr_type != DWC2_TRANSACTION_NONE)
1426 dwc2_hcd_queue_transactions(hsotg, tr_type);
1427 }
1428
1429 spin_unlock_irqrestore(&hsotg->lock, flags);
1430 return HRTIMER_NORESTART;
1431}
1432
1433/**
1434 * dwc2_qh_init() - Initializes a QH structure
1435 *
1436 * @hsotg: The HCD state structure for the DWC OTG controller
1437 * @qh: The QH to init
1438 * @urb: Holds the information about the device/endpoint needed to initialize
1439 * the QH
1440 * @mem_flags: Flags for allocating memory.
1441 */
1442static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1443 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1444{
1445 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1446 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1447 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1448 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1449 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1450 u32 hprt = dwc2_readl(hsotg, HPRT0);
1451 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1452 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1453 dev_speed != USB_SPEED_HIGH);
1454 int maxp = dwc2_hcd_get_maxp(&urb->pipe_info);
1455 int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info);
1456 int bytecount = maxp_mult * maxp;
1457 char *speed, *type;
1458
1459 /* Initialize QH */
1460 qh->hsotg = hsotg;
1461 timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0);
1462 hrtimer_setup(&qh->wait_timer, &dwc2_wait_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1463 qh->ep_type = ep_type;
1464 qh->ep_is_in = ep_is_in;
1465
1466 qh->data_toggle = DWC2_HC_PID_DATA0;
1467 qh->maxp = maxp;
1468 qh->maxp_mult = maxp_mult;
1469 INIT_LIST_HEAD(&qh->qtd_list);
1470 INIT_LIST_HEAD(&qh->qh_list_entry);
1471
1472 qh->do_split = do_split;
1473 qh->dev_speed = dev_speed;
1474
1475 if (ep_is_int || ep_is_isoc) {
1476 /* Compute scheduling parameters once and save them */
1477 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1478 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1479 mem_flags,
1480 &qh->ttport);
1481 int device_ns;
1482
1483 qh->dwc_tt = dwc_tt;
1484
1485 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
1486 ep_is_isoc, bytecount));
1487 device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
1488 ep_is_isoc, bytecount);
1489
1490 if (do_split && dwc_tt)
1491 device_ns += dwc_tt->usb_tt->think_time;
1492 qh->device_us = NS_TO_US(device_ns);
1493
1494 qh->device_interval = urb->interval;
1495 qh->host_interval = urb->interval * (do_split ? 8 : 1);
1496
1497 /*
1498 * Schedule low speed if we're running the host in low or
1499 * full speed OR if we've got a "TT" to deal with to access this
1500 * device.
1501 */
1502 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1503 dwc_tt;
1504
1505 if (do_split) {
1506 /* We won't know num transfers until we schedule */
1507 qh->num_hs_transfers = -1;
1508 } else if (dev_speed == USB_SPEED_HIGH) {
1509 qh->num_hs_transfers = 1;
1510 } else {
1511 qh->num_hs_transfers = 0;
1512 }
1513
1514 /* We'll schedule later when we have something to do */
1515 }
1516
1517 switch (dev_speed) {
1518 case USB_SPEED_LOW:
1519 speed = "low";
1520 break;
1521 case USB_SPEED_FULL:
1522 speed = "full";
1523 break;
1524 case USB_SPEED_HIGH:
1525 speed = "high";
1526 break;
1527 default:
1528 speed = "?";
1529 break;
1530 }
1531
1532 switch (qh->ep_type) {
1533 case USB_ENDPOINT_XFER_ISOC:
1534 type = "isochronous";
1535 break;
1536 case USB_ENDPOINT_XFER_INT:
1537 type = "interrupt";
1538 break;
1539 case USB_ENDPOINT_XFER_CONTROL:
1540 type = "control";
1541 break;
1542 case USB_ENDPOINT_XFER_BULK:
1543 type = "bulk";
1544 break;
1545 default:
1546 type = "?";
1547 break;
1548 }
1549
1550 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1551 speed, bytecount);
1552 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1553 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1554 dwc2_hcd_get_ep_num(&urb->pipe_info),
1555 ep_is_in ? "IN" : "OUT");
1556 if (ep_is_int || ep_is_isoc) {
1557 dwc2_sch_dbg(hsotg,
1558 "QH=%p ...duration: host=%d us, device=%d us\n",
1559 qh, qh->host_us, qh->device_us);
1560 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1561 qh, qh->host_interval, qh->device_interval);
1562 if (qh->schedule_low_speed)
1563 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1564 qh, dwc2_get_ls_map(hsotg, qh));
1565 }
1566}
1567
1568/**
1569 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1570 *
1571 * @hsotg: The HCD state structure for the DWC OTG controller
1572 * @urb: Holds the information about the device/endpoint needed
1573 * to initialize the QH
1574 * @mem_flags: Flags for allocating memory.
1575 *
1576 * Return: Pointer to the newly allocated QH, or NULL on error
1577 */
1578struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1579 struct dwc2_hcd_urb *urb,
1580 gfp_t mem_flags)
1581{
1582 struct dwc2_qh *qh;
1583
1584 if (!urb->priv)
1585 return NULL;
1586
1587 /* Allocate memory */
1588 qh = kzalloc_obj(*qh, mem_flags);
1589 if (!qh)
1590 return NULL;
1591
1592 dwc2_qh_init(hsotg, qh, urb, mem_flags);
1593
1594 if (hsotg->params.dma_desc_enable &&
1595 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1596 dwc2_hcd_qh_free(hsotg, qh);
1597 return NULL;
1598 }
1599
1600 return qh;
1601}
1602
1603/**
1604 * dwc2_hcd_qh_free() - Frees the QH
1605 *
1606 * @hsotg: HCD instance
1607 * @qh: The QH to free
1608 *
1609 * QH should already be removed from the list. QTD list should already be empty
1610 * if called from URB Dequeue.
1611 *
1612 * Must NOT be called with interrupt disabled or spinlock held
1613 */
1614void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1615{
1616 /* Make sure any unreserve work is finished. */
1617 if (timer_delete_sync(&qh->unreserve_timer)) {
1618 unsigned long flags;
1619
1620 spin_lock_irqsave(&hsotg->lock, flags);
1621 dwc2_do_unreserve(hsotg, qh);
1622 spin_unlock_irqrestore(&hsotg->lock, flags);
1623 }
1624
1625 /*
1626 * We don't have the lock so we can safely wait until the wait timer
1627 * finishes. Of course, at this point in time we'd better have set
1628 * wait_timer_active to false so if this timer was still pending it
1629 * won't do anything anyway, but we want it to finish before we free
1630 * memory.
1631 */
1632 hrtimer_cancel(&qh->wait_timer);
1633
1634 dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1635
1636 if (qh->desc_list)
1637 dwc2_hcd_qh_free_ddma(hsotg, qh);
1638 else if (hsotg->unaligned_cache && qh->dw_align_buf)
1639 kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf);
1640
1641 kfree(qh);
1642}
1643
1644/**
1645 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1646 * schedule if it is not already in the schedule. If the QH is already in
1647 * the schedule, no action is taken.
1648 *
1649 * @hsotg: The HCD state structure for the DWC OTG controller
1650 * @qh: The QH to add
1651 *
1652 * Return: 0 if successful, negative error code otherwise
1653 */
1654int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1655{
1656 int status;
1657 u32 intr_mask;
1658 ktime_t delay;
1659
1660 if (dbg_qh(qh))
1661 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1662
1663 if (!list_empty(&qh->qh_list_entry))
1664 /* QH already in a schedule */
1665 return 0;
1666
1667 /* Add the new QH to the appropriate schedule */
1668 if (dwc2_qh_is_non_per(qh)) {
1669 /* Schedule right away */
1670 qh->start_active_frame = hsotg->frame_number;
1671 qh->next_active_frame = qh->start_active_frame;
1672
1673 if (qh->want_wait) {
1674 list_add_tail(&qh->qh_list_entry,
1675 &hsotg->non_periodic_sched_waiting);
1676 qh->wait_timer_cancel = false;
1677 delay = ktime_set(0, DWC2_RETRY_WAIT_DELAY);
1678 hrtimer_start(&qh->wait_timer, delay, HRTIMER_MODE_REL);
1679 } else {
1680 list_add_tail(&qh->qh_list_entry,
1681 &hsotg->non_periodic_sched_inactive);
1682 }
1683 return 0;
1684 }
1685
1686 status = dwc2_schedule_periodic(hsotg, qh);
1687 if (status)
1688 return status;
1689 if (!hsotg->periodic_qh_count) {
1690 intr_mask = dwc2_readl(hsotg, GINTMSK);
1691 intr_mask |= GINTSTS_SOF;
1692 dwc2_writel(hsotg, intr_mask, GINTMSK);
1693 }
1694 hsotg->periodic_qh_count++;
1695
1696 return 0;
1697}
1698
1699/**
1700 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1701 * schedule. Memory is not freed.
1702 *
1703 * @hsotg: The HCD state structure
1704 * @qh: QH to remove from schedule
1705 */
1706void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1707{
1708 u32 intr_mask;
1709
1710 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1711
1712 /* If the wait_timer is pending, this will stop it from acting */
1713 qh->wait_timer_cancel = true;
1714
1715 if (list_empty(&qh->qh_list_entry))
1716 /* QH is not in a schedule */
1717 return;
1718
1719 if (dwc2_qh_is_non_per(qh)) {
1720 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1721 hsotg->non_periodic_qh_ptr =
1722 hsotg->non_periodic_qh_ptr->next;
1723 list_del_init(&qh->qh_list_entry);
1724 return;
1725 }
1726
1727 dwc2_deschedule_periodic(hsotg, qh);
1728 hsotg->periodic_qh_count--;
1729 if (!hsotg->periodic_qh_count &&
1730 !hsotg->params.dma_desc_enable) {
1731 intr_mask = dwc2_readl(hsotg, GINTMSK);
1732 intr_mask &= ~GINTSTS_SOF;
1733 dwc2_writel(hsotg, intr_mask, GINTMSK);
1734 }
1735}
1736
1737/**
1738 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1739 *
1740 * This is called for setting next_active_frame for periodic splits for all but
1741 * the first packet of the split. Confusing? I thought so...
1742 *
1743 * Periodic splits are single low/full speed transfers that we end up splitting
1744 * up into several high speed transfers. They always fit into one full (1 ms)
1745 * frame but might be split over several microframes (125 us each). We to put
1746 * each of the parts on a very specific high speed frame.
1747 *
1748 * This function figures out where the next active uFrame needs to be.
1749 *
1750 * @hsotg: The HCD state structure
1751 * @qh: QH for the periodic transfer.
1752 * @frame_number: The current frame number.
1753 *
1754 * Return: number missed by (or 0 if we didn't miss).
1755 */
1756static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1757 struct dwc2_qh *qh, u16 frame_number)
1758{
1759 u16 old_frame = qh->next_active_frame;
1760 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1761 int missed = 0;
1762 u16 incr;
1763
1764 /*
1765 * See dwc2_uframe_schedule_split() for split scheduling.
1766 *
1767 * Basically: increment 1 normally, but 2 right after the start split
1768 * (except for ISOC out).
1769 */
1770 if (old_frame == qh->start_active_frame &&
1771 !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1772 incr = 2;
1773 else
1774 incr = 1;
1775
1776 qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1777
1778 /*
1779 * Note that it's OK for frame_number to be 1 frame past
1780 * next_active_frame. Remember that next_active_frame is supposed to
1781 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
1782 * past it just means schedule ASAP.
1783 *
1784 * It's _not_ OK, however, if we're more than one frame past.
1785 */
1786 if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1787 /*
1788 * OOPS, we missed. That's actually pretty bad since
1789 * the hub will be unhappy; try ASAP I guess.
1790 */
1791 missed = dwc2_frame_num_dec(prev_frame_number,
1792 qh->next_active_frame);
1793 qh->next_active_frame = frame_number;
1794 }
1795
1796 return missed;
1797}
1798
1799/**
1800 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1801 *
1802 * This is called for setting next_active_frame for a periodic transfer for
1803 * all cases other than midway through a periodic split. This will also update
1804 * start_active_frame.
1805 *
1806 * Since we _always_ keep start_active_frame as the start of the previous
1807 * transfer this is normally pretty easy: we just add our interval to
1808 * start_active_frame and we've got our answer.
1809 *
1810 * The tricks come into play if we miss. In that case we'll look for the next
1811 * slot we can fit into.
1812 *
1813 * @hsotg: The HCD state structure
1814 * @qh: QH for the periodic transfer.
1815 * @frame_number: The current frame number.
1816 *
1817 * Return: number missed by (or 0 if we didn't miss).
1818 */
1819static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1820 struct dwc2_qh *qh, u16 frame_number)
1821{
1822 int missed = 0;
1823 u16 interval = qh->host_interval;
1824 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1825
1826 qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1827 interval);
1828
1829 /*
1830 * The dwc2_frame_num_gt() function used below won't work terribly well
1831 * with if we just incremented by a really large intervals since the
1832 * frame counter only goes to 0x3fff. It's terribly unlikely that we
1833 * will have missed in this case anyway. Just go to exit. If we want
1834 * to try to do better we'll need to keep track of a bigger counter
1835 * somewhere in the driver and handle overflows.
1836 */
1837 if (interval >= 0x1000)
1838 goto exit;
1839
1840 /*
1841 * Test for misses, which is when it's too late to schedule.
1842 *
1843 * A few things to note:
1844 * - We compare against prev_frame_number since start_active_frame
1845 * and next_active_frame are always 1 frame before we want things
1846 * to be active and we assume we can still get scheduled in the
1847 * current frame number.
1848 * - It's possible for start_active_frame (now incremented) to be
1849 * next_active_frame if we got an EO MISS (even_odd miss) which
1850 * basically means that we detected there wasn't enough time for
1851 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1852 * at the last second. We want to make sure we don't schedule
1853 * another transfer for the same frame. My test webcam doesn't seem
1854 * terribly upset by missing a transfer but really doesn't like when
1855 * we do two transfers in the same frame.
1856 * - Some misses are expected. Specifically, in order to work
1857 * perfectly dwc2 really needs quite spectacular interrupt latency
1858 * requirements. It needs to be able to handle its interrupts
1859 * completely within 125 us of them being asserted. That not only
1860 * means that the dwc2 interrupt handler needs to be fast but it
1861 * means that nothing else in the system has to block dwc2 for a long
1862 * time. We can help with the dwc2 parts of this, but it's hard to
1863 * guarantee that a system will have interrupt latency < 125 us, so
1864 * we have to be robust to some misses.
1865 */
1866 if (qh->start_active_frame == qh->next_active_frame ||
1867 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1868 u16 ideal_start = qh->start_active_frame;
1869 int periods_in_map;
1870
1871 /*
1872 * Adjust interval as per gcd with map size.
1873 * See pmap_schedule() for more details here.
1874 */
1875 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1876 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1877 else
1878 periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1879 interval = gcd(interval, periods_in_map);
1880
1881 do {
1882 qh->start_active_frame = dwc2_frame_num_inc(
1883 qh->start_active_frame, interval);
1884 } while (dwc2_frame_num_gt(prev_frame_number,
1885 qh->start_active_frame));
1886
1887 missed = dwc2_frame_num_dec(qh->start_active_frame,
1888 ideal_start);
1889 }
1890
1891exit:
1892 qh->next_active_frame = qh->start_active_frame;
1893
1894 return missed;
1895}
1896
1897/*
1898 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1899 * non-periodic schedule. The QH is added to the inactive non-periodic
1900 * schedule if any QTDs are still attached to the QH.
1901 *
1902 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1903 * there are any QTDs still attached to the QH, the QH is added to either the
1904 * periodic inactive schedule or the periodic ready schedule and its next
1905 * scheduled frame is calculated. The QH is placed in the ready schedule if
1906 * the scheduled frame has been reached already. Otherwise it's placed in the
1907 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1908 * completely removed from the periodic schedule.
1909 */
1910void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1911 int sched_next_periodic_split)
1912{
1913 u16 old_frame = qh->next_active_frame;
1914 u16 frame_number;
1915 int missed;
1916
1917 if (dbg_qh(qh))
1918 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1919
1920 if (dwc2_qh_is_non_per(qh)) {
1921 dwc2_hcd_qh_unlink(hsotg, qh);
1922 if (!list_empty(&qh->qtd_list))
1923 /* Add back to inactive/waiting non-periodic schedule */
1924 dwc2_hcd_qh_add(hsotg, qh);
1925 return;
1926 }
1927
1928 /*
1929 * Use the real frame number rather than the cached value as of the
1930 * last SOF just to get us a little closer to reality. Note that
1931 * means we don't actually know if we've already handled the SOF
1932 * interrupt for this frame.
1933 */
1934 frame_number = dwc2_hcd_get_frame_number(hsotg);
1935
1936 if (sched_next_periodic_split)
1937 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1938 else
1939 missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1940
1941 dwc2_sch_vdbg(hsotg,
1942 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1943 qh, sched_next_periodic_split, frame_number, old_frame,
1944 qh->next_active_frame,
1945 dwc2_frame_num_dec(qh->next_active_frame, old_frame),
1946 missed, missed ? "MISS" : "");
1947
1948 if (list_empty(&qh->qtd_list)) {
1949 dwc2_hcd_qh_unlink(hsotg, qh);
1950 return;
1951 }
1952
1953 /*
1954 * Remove from periodic_sched_queued and move to
1955 * appropriate queue
1956 *
1957 * Note: we purposely use the frame_number from the "hsotg" structure
1958 * since we know SOF interrupt will handle future frames.
1959 */
1960 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
1961 list_move_tail(&qh->qh_list_entry,
1962 &hsotg->periodic_sched_ready);
1963 else
1964 list_move_tail(&qh->qh_list_entry,
1965 &hsotg->periodic_sched_inactive);
1966}
1967
1968/**
1969 * dwc2_hcd_qtd_init() - Initializes a QTD structure
1970 *
1971 * @qtd: The QTD to initialize
1972 * @urb: The associated URB
1973 */
1974void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
1975{
1976 qtd->urb = urb;
1977 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
1978 USB_ENDPOINT_XFER_CONTROL) {
1979 /*
1980 * The only time the QTD data toggle is used is on the data
1981 * phase of control transfers. This phase always starts with
1982 * DATA1.
1983 */
1984 qtd->data_toggle = DWC2_HC_PID_DATA1;
1985 qtd->control_phase = DWC2_CONTROL_SETUP;
1986 }
1987
1988 /* Start split */
1989 qtd->complete_split = 0;
1990 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1991 qtd->isoc_split_offset = 0;
1992 qtd->in_process = 0;
1993
1994 /* Store the qtd ptr in the urb to reference the QTD */
1995 urb->qtd = qtd;
1996}
1997
1998/**
1999 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
2000 * Caller must hold driver lock.
2001 *
2002 * @hsotg: The DWC HCD structure
2003 * @qtd: The QTD to add
2004 * @qh: Queue head to add qtd to
2005 *
2006 * Return: 0 if successful, negative error code otherwise
2007 *
2008 * If the QH to which the QTD is added is not currently scheduled, it is placed
2009 * into the proper schedule based on its EP type.
2010 */
2011int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2012 struct dwc2_qh *qh)
2013{
2014 int retval;
2015
2016 if (unlikely(!qh)) {
2017 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2018 retval = -EINVAL;
2019 goto fail;
2020 }
2021
2022 retval = dwc2_hcd_qh_add(hsotg, qh);
2023 if (retval)
2024 goto fail;
2025
2026 qtd->qh = qh;
2027 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2028
2029 return 0;
2030fail:
2031 return retval;
2032}