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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
5 *
6 * (c) 1998-2002 Petr Vandrovec <[email protected]>
7 *
8 * Portions Copyright (c) 2001 Matrox Graphics Inc.
9 *
10 * Version: 1.65 2002/08/14
11 *
12 * MTRR stuff: 1998 Tom Rini <[email protected]>
13 *
14 * Contributors: "menion?" <[email protected]>
15 * Betatesting, fixes, ideas
16 *
17 * "Kurt Garloff" <[email protected]>
18 * Betatesting, fixes, ideas, videomodes, videomodes timmings
19 *
20 * "Tom Rini" <[email protected]>
21 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
22 *
23 * "Bibek Sahu" <[email protected]>
24 * Access device through readb|w|l and write b|w|l
25 * Extensive debugging stuff
26 *
27 * "Daniel Haun" <[email protected]>
28 * Testing, hardware cursor fixes
29 *
30 * "Scott Wood" <[email protected]>
31 * Fixes
32 *
33 * "Gerd Knorr" <[email protected]>
34 * Betatesting
35 *
36 * "Kelly French" <[email protected]>
37 * "Fernando Herrera" <[email protected]>
38 * Betatesting, bug reporting
39 *
40 * "Pablo Bianucci" <[email protected]>
41 * Fixes, ideas, betatesting
42 *
43 * "Inaky Perez Gonzalez" <[email protected]>
44 * Fixes, enhandcements, ideas, betatesting
45 *
46 * "Ryuichi Oikawa" <[email protected]>
47 * PPC betatesting, PPC support, backward compatibility
48 *
49 * "Paul Womar" <[email protected]>
50 * "Owen Waller" <[email protected]>
51 * PPC betatesting
52 *
53 * "Thomas Pornin" <[email protected]>
54 * Alpha betatesting
55 *
56 * "Pieter van Leuven" <[email protected]>
57 * "Ulf Jaenicke-Roessler" <[email protected]>
58 * G100 testing
59 *
60 * "H. Peter Arvin" <[email protected]>
61 * Ideas
62 *
63 * "Cort Dougan" <[email protected]>
64 * CHRP fixes and PReP cleanup
65 *
66 * "Mark Vojkovich" <[email protected]>
67 * G400 support
68 *
69 * "David C. Hansen" <[email protected]>
70 * Fixes
71 *
72 * "Ian Romanick" <[email protected]>
73 * Find PInS data in BIOS on PowerPC systems.
74 *
75 * (following author is not in any relation with this code, but his code
76 * is included in this driver)
77 *
78 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
79 * (c) 1998 Gerd Knorr <[email protected]>
80 *
81 * (following author is not in any relation with this code, but his ideas
82 * were used when writing this driver)
83 *
84 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <[email protected]>
85 *
86 */
87
88#include <linux/export.h>
89
90#include "matroxfb_misc.h"
91#include <linux/interrupt.h>
92#include <linux/matroxfb.h>
93
94void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
95{
96 DBG_REG(__func__)
97 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
98 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
99}
100
101int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
102{
103 DBG_REG(__func__)
104 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
105 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
106}
107
108void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
109 unsigned int pixclock = var->pixclock;
110
111 DBG(__func__)
112
113 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
114 mt->pixclock = 1000000000 / pixclock;
115 if (mt->pixclock < 1) mt->pixclock = 1;
116 mt->mnp = -1;
117 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
118 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
119 mt->HDisplay = var->xres;
120 mt->HSyncStart = mt->HDisplay + var->right_margin;
121 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
122 mt->HTotal = mt->HSyncEnd + var->left_margin;
123 mt->VDisplay = var->yres;
124 mt->VSyncStart = mt->VDisplay + var->lower_margin;
125 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
126 mt->VTotal = mt->VSyncEnd + var->upper_margin;
127 mt->sync = var->sync;
128}
129
130int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
131 unsigned int* in, unsigned int* feed, unsigned int* post) {
132 unsigned int bestdiff = ~0;
133 unsigned int bestvco = 0;
134 unsigned int fxtal = pll->ref_freq;
135 unsigned int fwant;
136 unsigned int p;
137
138 DBG(__func__)
139
140 fwant = freq;
141
142#ifdef DEBUG
143 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
144 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
145 printk(KERN_ERR "freq: %d\n", freq);
146 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
147 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
148 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
149 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
150 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
151 printk(KERN_ERR "fmax: %d\n", fmax);
152#endif
153 for (p = 1; p <= pll->post_shift_max; p++) {
154 if (fwant * 2 > fmax)
155 break;
156 fwant *= 2;
157 }
158 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
159 if (fwant > fmax) fwant = fmax;
160 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
161 unsigned int m;
162
163 if (fwant < pll->vco_freq_min) break;
164 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
165 unsigned int diff, fvco;
166 unsigned int n;
167
168 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
169 if (n > pll->feed_div_max)
170 break;
171 if (n < pll->feed_div_min)
172 n = pll->feed_div_min;
173 fvco = (fxtal * (n + 1)) / (m + 1);
174 if (fvco < fwant)
175 diff = fwant - fvco;
176 else
177 diff = fvco - fwant;
178 if (diff < bestdiff) {
179 bestdiff = diff;
180 *post = p;
181 *in = m;
182 *feed = n;
183 bestvco = fvco;
184 }
185 }
186 }
187 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
188 return bestvco;
189}
190
191int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
192{
193 unsigned int hd, hs, he, hbe, ht;
194 unsigned int vd, vs, ve, vt, lc;
195 unsigned int wd;
196 unsigned int divider;
197 int i;
198 struct matrox_hw_state * const hw = &minfo->hw;
199
200 DBG(__func__)
201
202 hw->SEQ[0] = 0x00;
203 hw->SEQ[1] = 0x01; /* or 0x09 */
204 hw->SEQ[2] = 0x0F; /* bitplanes */
205 hw->SEQ[3] = 0x00;
206 hw->SEQ[4] = 0x0E;
207 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
208 if (m->dblscan) {
209 m->VTotal <<= 1;
210 m->VDisplay <<= 1;
211 m->VSyncStart <<= 1;
212 m->VSyncEnd <<= 1;
213 }
214 if (m->interlaced) {
215 m->VTotal >>= 1;
216 m->VDisplay >>= 1;
217 m->VSyncStart >>= 1;
218 m->VSyncEnd >>= 1;
219 }
220
221 /* GCTL is ignored when not using 0xA0000 aperture */
222 hw->GCTL[0] = 0x00;
223 hw->GCTL[1] = 0x00;
224 hw->GCTL[2] = 0x00;
225 hw->GCTL[3] = 0x00;
226 hw->GCTL[4] = 0x00;
227 hw->GCTL[5] = 0x40;
228 hw->GCTL[6] = 0x05;
229 hw->GCTL[7] = 0x0F;
230 hw->GCTL[8] = 0xFF;
231
232 /* Whole ATTR is ignored in PowerGraphics mode */
233 for (i = 0; i < 16; i++)
234 hw->ATTR[i] = i;
235 hw->ATTR[16] = 0x41;
236 hw->ATTR[17] = 0xFF;
237 hw->ATTR[18] = 0x0F;
238 hw->ATTR[19] = 0x00;
239 hw->ATTR[20] = 0x00;
240
241 hd = m->HDisplay >> 3;
242 hs = m->HSyncStart >> 3;
243 he = m->HSyncEnd >> 3;
244 ht = m->HTotal >> 3;
245 /* standard timmings are in 8pixels, but for interleaved we cannot */
246 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
247 /* using 16 or more pixels per unit can save us */
248 divider = minfo->curr.final_bppShift;
249 while (divider & 3) {
250 hd >>= 1;
251 hs >>= 1;
252 he >>= 1;
253 ht >>= 1;
254 divider <<= 1;
255 }
256 divider = divider / 4;
257 /* divider can be from 1 to 8 */
258 while (divider > 8) {
259 hd <<= 1;
260 hs <<= 1;
261 he <<= 1;
262 ht <<= 1;
263 divider >>= 1;
264 }
265 hd = hd - 1;
266 hs = hs - 1;
267 he = he - 1;
268 ht = ht - 1;
269 vd = m->VDisplay - 1;
270 vs = m->VSyncStart - 1;
271 ve = m->VSyncEnd - 1;
272 vt = m->VTotal - 2;
273 lc = vd;
274 /* G200 cannot work with (ht & 7) == 6 */
275 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
276 ht++;
277 hbe = ht;
278 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
279
280 hw->CRTCEXT[0] = 0;
281 hw->CRTCEXT[5] = 0;
282 if (m->interlaced) {
283 hw->CRTCEXT[0] = 0x80;
284 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
285 if (!m->dblscan)
286 wd <<= 1;
287 vt &= ~1;
288 }
289 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
290 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
291 ((hd & 0x100) >> 7) | /* blanking */
292 ((hs & 0x100) >> 6) | /* sync start */
293 (hbe & 0x040); /* end hor. blanking */
294 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
295 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
296 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
297 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
298 ((vd & 0x400) >> 8) | /* disp end */
299 ((vd & 0xC00) >> 7) | /* vblanking start */
300 ((vs & 0xC00) >> 5) |
301 ((lc & 0x400) >> 3);
302 hw->CRTCEXT[3] = (divider - 1) | 0x80;
303 hw->CRTCEXT[4] = 0;
304
305 hw->CRTC[0] = ht-4;
306 hw->CRTC[1] = hd;
307 hw->CRTC[2] = hd;
308 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
309 hw->CRTC[4] = hs;
310 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
311 hw->CRTC[6] = vt & 0xFF;
312 hw->CRTC[7] = ((vt & 0x100) >> 8) |
313 ((vd & 0x100) >> 7) |
314 ((vs & 0x100) >> 6) |
315 ((vd & 0x100) >> 5) |
316 ((lc & 0x100) >> 4) |
317 ((vt & 0x200) >> 4) |
318 ((vd & 0x200) >> 3) |
319 ((vs & 0x200) >> 2);
320 hw->CRTC[8] = 0x00;
321 hw->CRTC[9] = ((vd & 0x200) >> 4) |
322 ((lc & 0x200) >> 3);
323 if (m->dblscan && !m->interlaced)
324 hw->CRTC[9] |= 0x80;
325 for (i = 10; i < 16; i++)
326 hw->CRTC[i] = 0x00;
327 hw->CRTC[16] = vs /* & 0xFF */;
328 hw->CRTC[17] = (ve & 0x0F) | 0x20;
329 hw->CRTC[18] = vd /* & 0xFF */;
330 hw->CRTC[19] = wd /* & 0xFF */;
331 hw->CRTC[20] = 0x00;
332 hw->CRTC[21] = vd /* & 0xFF */;
333 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
334 hw->CRTC[23] = 0xC3;
335 hw->CRTC[24] = lc;
336 return 0;
337};
338
339void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
340{
341 int i;
342 struct matrox_hw_state * const hw = &minfo->hw;
343 CRITFLAGS
344
345 DBG(__func__)
346
347 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
348 dprintk(KERN_INFO "SEQ regs: ");
349 for (i = 0; i < 5; i++)
350 dprintk("%02X:", hw->SEQ[i]);
351 dprintk("\n");
352 dprintk(KERN_INFO "GDC regs: ");
353 for (i = 0; i < 9; i++)
354 dprintk("%02X:", hw->GCTL[i]);
355 dprintk("\n");
356 dprintk(KERN_INFO "CRTC regs: ");
357 for (i = 0; i < 25; i++)
358 dprintk("%02X:", hw->CRTC[i]);
359 dprintk("\n");
360 dprintk(KERN_INFO "ATTR regs: ");
361 for (i = 0; i < 21; i++)
362 dprintk("%02X:", hw->ATTR[i]);
363 dprintk("\n");
364
365 CRITBEGIN
366
367 mga_inb(M_ATTR_RESET);
368 mga_outb(M_ATTR_INDEX, 0);
369 mga_outb(M_MISC_REG, hw->MiscOutReg);
370 for (i = 1; i < 5; i++)
371 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
372 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
373 for (i = 0; i < 25; i++)
374 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
375 for (i = 0; i < 9; i++)
376 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
377 for (i = 0; i < 21; i++) {
378 mga_inb(M_ATTR_RESET);
379 mga_outb(M_ATTR_INDEX, i);
380 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
381 }
382 mga_outb(M_PALETTE_MASK, 0xFF);
383 mga_outb(M_DAC_REG, 0x00);
384 for (i = 0; i < 768; i++)
385 mga_outb(M_DAC_VAL, hw->DACpal[i]);
386 mga_inb(M_ATTR_RESET);
387 mga_outb(M_ATTR_INDEX, 0x20);
388
389 CRITEND
390}
391
392static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
393 unsigned int b0 = readb(pins);
394
395 if (b0 == 0x2E && readb(pins+1) == 0x41) {
396 unsigned int pins_len = readb(pins+2);
397 unsigned int i;
398 unsigned char cksum;
399 unsigned char* dst = bd->pins;
400
401 if (pins_len < 3 || pins_len > 128) {
402 return;
403 }
404 *dst++ = 0x2E;
405 *dst++ = 0x41;
406 *dst++ = pins_len;
407 cksum = 0x2E + 0x41 + pins_len;
408 for (i = 3; i < pins_len; i++) {
409 cksum += *dst++ = readb(pins+i);
410 }
411 if (cksum) {
412 return;
413 }
414 bd->pins_len = pins_len;
415 } else if (b0 == 0x40 && readb(pins+1) == 0x00) {
416 unsigned int i;
417 unsigned char* dst = bd->pins;
418
419 *dst++ = 0x40;
420 *dst++ = 0;
421 for (i = 2; i < 0x40; i++) {
422 *dst++ = readb(pins+i);
423 }
424 bd->pins_len = 0x40;
425 }
426}
427
428static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
429 unsigned int pcir_offset;
430
431 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
432 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
433 readb(vbios + pcir_offset ) == 'P' &&
434 readb(vbios + pcir_offset + 1) == 'C' &&
435 readb(vbios + pcir_offset + 2) == 'I' &&
436 readb(vbios + pcir_offset + 3) == 'R') {
437 unsigned char h;
438
439 h = readb(vbios + pcir_offset + 0x12);
440 bd->version.vMaj = (h >> 4) & 0xF;
441 bd->version.vMin = h & 0xF;
442 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
443 } else {
444 unsigned char h;
445
446 h = readb(vbios + 5);
447 bd->version.vMaj = (h >> 4) & 0xF;
448 bd->version.vMin = h & 0xF;
449 bd->version.vRev = 0;
450 }
451}
452
453static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
454 unsigned char b;
455
456 b = readb(vbios + 0x7FF1);
457 if (b == 0xFF) {
458 b = 0;
459 }
460 bd->output.state = b;
461}
462
463static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
464 unsigned int i;
465
466 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
467 bd->output.tvout = 0;
468 if (readb(vbios + 0x1D) != 'I' ||
469 readb(vbios + 0x1E) != 'B' ||
470 readb(vbios + 0x1F) != 'M' ||
471 readb(vbios + 0x20) != ' ') {
472 return;
473 }
474 for (i = 0x2D; i < 0x2D + 128; i++) {
475 unsigned char b = readb(vbios + i);
476
477 if (b == '(' && readb(vbios + i + 1) == 'V') {
478 if (readb(vbios + i + 6) == 'T' &&
479 readb(vbios + i + 7) == 'V' &&
480 readb(vbios + i + 8) == 'O') {
481 bd->output.tvout = 1;
482 }
483 return;
484 }
485 if (b == 0)
486 break;
487 }
488}
489
490static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
491 unsigned int pins_offset;
492
493 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
494 return;
495 }
496 bd->bios_valid = 1;
497 get_bios_version(vbios, bd);
498 get_bios_output(vbios, bd);
499 get_bios_tvout(vbios, bd);
500#if defined(__powerpc__)
501 /* On PowerPC cards, the PInS offset isn't stored at the end of the
502 * BIOS image. Instead, you must search the entire BIOS image for
503 * the magic PInS signature.
504 *
505 * This actually applies to all OpenFirmware base cards. Since these
506 * cards could be put in a MIPS or SPARC system, should the condition
507 * be something different?
508 */
509 for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
510 unsigned char header[3];
511
512 header[0] = readb(vbios + pins_offset);
513 header[1] = readb(vbios + pins_offset + 1);
514 header[2] = readb(vbios + pins_offset + 2);
515 if ( (header[0] == 0x2E) && (header[1] == 0x41)
516 && ((header[2] == 0x40) || (header[2] == 0x80)) ) {
517 printk(KERN_INFO "PInS data found at offset %u\n",
518 pins_offset);
519 get_pins(vbios + pins_offset, bd);
520 break;
521 }
522 }
523#else
524 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
525 if (pins_offset <= 0xFF80) {
526 get_pins(vbios + pins_offset, bd);
527 }
528#endif
529}
530
531static int parse_pins1(struct matrox_fb_info *minfo,
532 const struct matrox_bios *bd)
533{
534 unsigned int maxdac;
535
536 switch (bd->pins[22]) {
537 case 0: maxdac = 175000; break;
538 case 1: maxdac = 220000; break;
539 default: maxdac = 240000; break;
540 }
541 if (get_unaligned_le16(bd->pins + 24)) {
542 maxdac = get_unaligned_le16(bd->pins + 24) * 10;
543 }
544 minfo->limits.pixel.vcomax = maxdac;
545 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
546 get_unaligned_le16(bd->pins + 28) * 10 : 50000;
547 /* ignore 4MB, 8MB, module clocks */
548 minfo->features.pll.ref_freq = 14318;
549 minfo->values.reg.mctlwtst = 0x00030101;
550 return 0;
551}
552
553static void default_pins1(struct matrox_fb_info *minfo)
554{
555 /* Millennium */
556 minfo->limits.pixel.vcomax = 220000;
557 minfo->values.pll.system = 50000;
558 minfo->features.pll.ref_freq = 14318;
559 minfo->values.reg.mctlwtst = 0x00030101;
560}
561
562static int parse_pins2(struct matrox_fb_info *minfo,
563 const struct matrox_bios *bd)
564{
565 minfo->limits.pixel.vcomax =
566 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
567 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
568 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
569 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
570 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
571 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
572 minfo->features.pll.ref_freq = 14318;
573 return 0;
574}
575
576static void default_pins2(struct matrox_fb_info *minfo)
577{
578 /* Millennium II, Mystique */
579 minfo->limits.pixel.vcomax =
580 minfo->limits.system.vcomax = 230000;
581 minfo->values.reg.mctlwtst = 0x00030101;
582 minfo->values.pll.system = 50000;
583 minfo->features.pll.ref_freq = 14318;
584}
585
586static int parse_pins3(struct matrox_fb_info *minfo,
587 const struct matrox_bios *bd)
588{
589 minfo->limits.pixel.vcomax =
590 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
591 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
592 0x01250A21 : get_unaligned_le32(bd->pins + 48);
593 /* memory config */
594 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
595 ((bd->pins[57] << 22) & 0x00C00000) |
596 ((bd->pins[56] << 1) & 0x000001E0) |
597 ( bd->pins[56] & 0x0000000F);
598 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
599 minfo->values.reg.opt2 = bd->pins[58] << 12;
600 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
601 return 0;
602}
603
604static void default_pins3(struct matrox_fb_info *minfo)
605{
606 /* G100, G200 */
607 minfo->limits.pixel.vcomax =
608 minfo->limits.system.vcomax = 230000;
609 minfo->values.reg.mctlwtst = 0x01250A21;
610 minfo->values.reg.memrdbk = 0x00000000;
611 minfo->values.reg.opt = 0x00000C00;
612 minfo->values.reg.opt2 = 0x00000000;
613 minfo->features.pll.ref_freq = 27000;
614}
615
616static int parse_pins4(struct matrox_fb_info *minfo,
617 const struct matrox_bios *bd)
618{
619 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
620 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
621 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
622 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
623 ((bd->pins[87] << 22) & 0x00C00000) |
624 ((bd->pins[86] << 1) & 0x000001E0) |
625 ( bd->pins[86] & 0x0000000F);
626 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
627 ((bd->pins[53] << 22) & 0x10000000) |
628 ((bd->pins[53] << 7) & 0x00001C00);
629 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
630 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
631 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
632 return 0;
633}
634
635static void default_pins4(struct matrox_fb_info *minfo)
636{
637 /* G400 */
638 minfo->limits.pixel.vcomax =
639 minfo->limits.system.vcomax = 252000;
640 minfo->values.reg.mctlwtst = 0x04A450A1;
641 minfo->values.reg.memrdbk = 0x000000E7;
642 minfo->values.reg.opt = 0x10000400;
643 minfo->values.reg.opt3 = 0x0190A419;
644 minfo->values.pll.system = 200000;
645 minfo->features.pll.ref_freq = 27000;
646}
647
648static int parse_pins5(struct matrox_fb_info *minfo,
649 const struct matrox_bios *bd)
650{
651 unsigned int mult;
652
653 mult = bd->pins[4]?8000:6000;
654
655 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
656 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
657 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
658 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
659 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
660 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
661 minfo->values.pll.system =
662 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
663 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
664 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
665 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
666 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
667 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
668 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
669 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
670 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
671 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
672 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
673 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
674 if (bd->pins[115] & 4) {
675 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
676 } else {
677 static const u8 wtst_xlat[] = {
678 0, 1, 5, 6, 7, 5, 2, 3
679 };
680
681 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
682 wtst_xlat[minfo->values.reg.mctlwtst & 7];
683 }
684 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
685 return 0;
686}
687
688static void default_pins5(struct matrox_fb_info *minfo)
689{
690 /* Mine 16MB G450 with SDRAM DDR */
691 minfo->limits.pixel.vcomax =
692 minfo->limits.system.vcomax =
693 minfo->limits.video.vcomax = 600000;
694 minfo->limits.pixel.vcomin =
695 minfo->limits.system.vcomin =
696 minfo->limits.video.vcomin = 256000;
697 minfo->values.pll.system =
698 minfo->values.pll.video = 284000;
699 minfo->values.reg.opt = 0x404A1160;
700 minfo->values.reg.opt2 = 0x0000AC00;
701 minfo->values.reg.opt3 = 0x0090A409;
702 minfo->values.reg.mctlwtst_core =
703 minfo->values.reg.mctlwtst = 0x0C81462B;
704 minfo->values.reg.memmisc = 0x80000004;
705 minfo->values.reg.memrdbk = 0x01001103;
706 minfo->features.pll.ref_freq = 27000;
707 minfo->values.memory.ddr = 1;
708 minfo->values.memory.dll = 1;
709 minfo->values.memory.emrswen = 1;
710 minfo->values.reg.maccess = 0x00004000;
711}
712
713static int matroxfb_set_limits(struct matrox_fb_info *minfo,
714 const struct matrox_bios *bd)
715{
716 unsigned int pins_version;
717 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
718
719 switch (minfo->chip) {
720 case MGA_2064: default_pins1(minfo); break;
721 case MGA_2164:
722 case MGA_1064:
723 case MGA_1164: default_pins2(minfo); break;
724 case MGA_G100:
725 case MGA_G200: default_pins3(minfo); break;
726 case MGA_G400: default_pins4(minfo); break;
727 case MGA_G450:
728 case MGA_G550: default_pins5(minfo); break;
729 }
730 if (!bd->bios_valid) {
731 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
732 return -1;
733 }
734 if (bd->pins_len < 64) {
735 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
736 return -1;
737 }
738 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
739 pins_version = bd->pins[5];
740 if (pins_version < 2 || pins_version > 5) {
741 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
742 return -1;
743 }
744 } else {
745 pins_version = 1;
746 }
747 if (bd->pins_len != pinslen[pins_version - 1]) {
748 printk(KERN_INFO "matroxfb: Invalid powerup info\n");
749 return -1;
750 }
751 switch (pins_version) {
752 case 1:
753 return parse_pins1(minfo, bd);
754 case 2:
755 return parse_pins2(minfo, bd);
756 case 3:
757 return parse_pins3(minfo, bd);
758 case 4:
759 return parse_pins4(minfo, bd);
760 case 5:
761 return parse_pins5(minfo, bd);
762 default:
763 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
764 return -1;
765 }
766}
767
768void matroxfb_read_pins(struct matrox_fb_info *minfo)
769{
770 u32 opt;
771 u32 biosbase;
772 u32 fbbase;
773 struct pci_dev *pdev = minfo->pcidev;
774
775 memset(&minfo->bios, 0, sizeof(minfo->bios));
776 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
777 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
778 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
779 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
780 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
781 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
782 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
783 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
784#ifdef CONFIG_X86
785 if (!minfo->bios.bios_valid) {
786 unsigned char __iomem* b;
787
788 b = ioremap(0x000C0000, 65536);
789 if (!b) {
790 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
791 } else {
792 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
793 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
794
795 if (ven != pdev->vendor || dev != pdev->device) {
796 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
797 ven, dev, pdev->vendor, pdev->device);
798 } else {
799 parse_bios(b, &minfo->bios);
800 }
801 iounmap(b);
802 }
803 }
804#endif
805 matroxfb_set_limits(minfo, &minfo->bios);
806 printk(KERN_INFO "PInS memtype = %u\n",
807 (minfo->values.reg.opt & 0x1C00) >> 10);
808}
809
810EXPORT_SYMBOL(matroxfb_DAC_in);
811EXPORT_SYMBOL(matroxfb_DAC_out);
812EXPORT_SYMBOL(matroxfb_var2my);
813EXPORT_SYMBOL(matroxfb_PLL_calcclock);
814EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
815EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
816EXPORT_SYMBOL(matroxfb_read_pins);
817
818MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <[email protected]>");
819MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
820MODULE_LICENSE("GPL");