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1/*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague ([email protected])
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi ([email protected])
9 * Copyright (c) 1999 Jakub Jelinek ([email protected])
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30#include <linux/aperture.h>
31#include <linux/module.h>
32#include <linux/moduleparam.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <video/permedia2.h>
43#include <video/cvisionppc.h>
44
45#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46#error "The endianness of the target host has not been defined."
47#endif
48
49#if !defined(CONFIG_PCI)
50#error "Only generic PCI cards supported."
51#endif
52
53#undef PM2FB_MASTER_DEBUG
54#ifdef PM2FB_MASTER_DEBUG
55#define DPRINTK(a, b...) \
56 printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b)
57#else
58#define DPRINTK(a, b...) no_printk(a, ##b)
59#endif
60
61#define PM2_PIXMAP_SIZE (1600 * 4)
62
63/*
64 * Driver data
65 */
66static int hwcursor = 1;
67static char *mode_option;
68
69/*
70 * The XFree GLINT driver will (I think to implement hardware cursor
71 * support on TVP4010 and similar where there is no RAMDAC - see
72 * comment in set_video) always request +ve sync regardless of what
73 * the mode requires. This screws me because I have a Sun
74 * fixed-frequency monitor which absolutely has to have -ve sync. So
75 * these flags allow the user to specify that requests for +ve sync
76 * should be silently turned in -ve sync.
77 */
78static bool lowhsync;
79static bool lowvsync;
80static bool noaccel;
81static bool nomtrr;
82
83/*
84 * The hardware state of the graphics card that isn't part of the
85 * screeninfo.
86 */
87struct pm2fb_par
88{
89 pm2type_t type; /* Board type */
90 unsigned char __iomem *v_regs;/* virtual address of p_regs */
91 u32 memclock; /* memclock */
92 u32 video; /* video flags before blanking */
93 u32 mem_config; /* MemConfig reg at probe */
94 u32 mem_control; /* MemControl reg at probe */
95 u32 boot_address; /* BootAddress reg at probe */
96 u32 palette[16];
97 int wc_cookie;
98};
99
100/*
101 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
102 * if we don't use modedb.
103 */
104static struct fb_fix_screeninfo pm2fb_fix = {
105 .id = "",
106 .type = FB_TYPE_PACKED_PIXELS,
107 .visual = FB_VISUAL_PSEUDOCOLOR,
108 .xpanstep = 1,
109 .ypanstep = 1,
110 .ywrapstep = 0,
111 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
112};
113
114/*
115 * Default video mode. In case the modedb doesn't work.
116 */
117static const struct fb_var_screeninfo pm2fb_var = {
118 /* "640x480, 8 bpp @ 60 Hz */
119 .xres = 640,
120 .yres = 480,
121 .xres_virtual = 640,
122 .yres_virtual = 480,
123 .bits_per_pixel = 8,
124 .red = {0, 8, 0},
125 .blue = {0, 8, 0},
126 .green = {0, 8, 0},
127 .activate = FB_ACTIVATE_NOW,
128 .height = -1,
129 .width = -1,
130 .accel_flags = 0,
131 .pixclock = 39721,
132 .left_margin = 40,
133 .right_margin = 24,
134 .upper_margin = 32,
135 .lower_margin = 11,
136 .hsync_len = 96,
137 .vsync_len = 2,
138 .vmode = FB_VMODE_NONINTERLACED
139};
140
141/*
142 * Utility functions
143 */
144
145static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
146{
147 return fb_readl(p->v_regs + off);
148}
149
150static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
151{
152 fb_writel(v, p->v_regs + off);
153}
154
155static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
156{
157 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
158 mb();
159 return pm2_RD(p, PM2R_RD_INDEXED_DATA);
160}
161
162static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
163{
164 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
165 mb();
166 return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
167}
168
169static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
170{
171 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
172 wmb();
173 pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
174 wmb();
175}
176
177static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
178{
179 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
180 wmb();
181 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
182 wmb();
183}
184
185#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
186#define WAIT_FIFO(p, a)
187#else
188static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
189{
190 while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)
191 cpu_relax();
192}
193#endif
194
195/*
196 * partial products for the supported horizontal resolutions.
197 */
198#define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
199static const struct {
200 u16 width;
201 u16 pp;
202} pp_table[] = {
203 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
204 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
205 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
206 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
207 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
208 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
209 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
210 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
211 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
212 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
213 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
214 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
215 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
216 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
217 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
218 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
219 { 0, 0 } };
220
221static u32 partprod(u32 xres)
222{
223 int i;
224
225 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
226 ;
227 if (pp_table[i].width == 0)
228 DPRINTK("invalid width %u\n", xres);
229 return pp_table[i].pp;
230}
231
232static u32 to3264(u32 timing, int bpp, int is64)
233{
234 switch (bpp) {
235 case 24:
236 timing *= 3;
237 fallthrough;
238 case 8:
239 timing >>= 1;
240 fallthrough;
241 case 16:
242 timing >>= 1;
243 fallthrough;
244 case 32:
245 break;
246 }
247 if (is64)
248 timing >>= 1;
249 return timing;
250}
251
252static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
253 unsigned char *pp)
254{
255 unsigned char m;
256 unsigned char n;
257 unsigned char p;
258 u32 f;
259 s32 curr;
260 s32 delta = 100000;
261
262 *mm = *nn = *pp = 0;
263 for (n = 2; n < 15; n++) {
264 for (m = 2; m; m++) {
265 f = PM2_REFERENCE_CLOCK * m / n;
266 if (f >= 150000 && f <= 300000) {
267 for (p = 0; p < 5; p++, f >>= 1) {
268 curr = (clk > f) ? clk - f : f - clk;
269 if (curr < delta) {
270 delta = curr;
271 *mm = m;
272 *nn = n;
273 *pp = p;
274 }
275 }
276 }
277 }
278 }
279}
280
281static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
282 unsigned char *pp)
283{
284 unsigned char m;
285 unsigned char n;
286 unsigned char p;
287 u32 f;
288 s32 delta = 1000;
289
290 *mm = *nn = *pp = 0;
291 for (m = 1; m < 128; m++) {
292 for (n = 2 * m + 1; n; n++) {
293 for (p = 0; p < 2; p++) {
294 f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
295 if (clk > f - delta && clk < f + delta) {
296 delta = (clk > f) ? clk - f : f - clk;
297 *mm = m;
298 *nn = n;
299 *pp = p;
300 }
301 }
302 }
303 }
304}
305
306static void clear_palette(struct pm2fb_par *p)
307{
308 int i = 256;
309
310 WAIT_FIFO(p, 1);
311 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
312 wmb();
313 while (i--) {
314 WAIT_FIFO(p, 3);
315 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
316 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
317 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
318 }
319}
320
321static void reset_card(struct pm2fb_par *p)
322{
323 if (p->type == PM2_TYPE_PERMEDIA2V)
324 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
325 pm2_WR(p, PM2R_RESET_STATUS, 0);
326 mb();
327 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
328 cpu_relax();
329 mb();
330#ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
331 DPRINTK("FIFO disconnect enabled\n");
332 pm2_WR(p, PM2R_FIFO_DISCON, 1);
333 mb();
334#endif
335
336 /* Restore stashed memory config information from probe */
337 WAIT_FIFO(p, 3);
338 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
339 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
340 wmb();
341 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
342}
343
344static void reset_config(struct pm2fb_par *p)
345{
346 WAIT_FIFO(p, 53);
347 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
348 ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
349 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
350 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
351 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
352 pm2_WR(p, PM2R_APERTURE_ONE, 0);
353 pm2_WR(p, PM2R_APERTURE_TWO, 0);
354 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
355 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
356 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
357 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
358 pm2_WR(p, PM2R_LB_READ_MODE, 0);
359 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
360 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
361 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
362 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
363 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
364 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
365 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
366 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
367 pm2_WR(p, PM2R_DITHER_MODE, 0);
368 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
369 pm2_WR(p, PM2R_DEPTH_MODE, 0);
370 pm2_WR(p, PM2R_STENCIL_MODE, 0);
371 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
372 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
373 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
374 pm2_WR(p, PM2R_YUV_MODE, 0);
375 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
376 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
377 pm2_WR(p, PM2R_FOG_MODE, 0);
378 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
379 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
380 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
381 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
382 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
383 pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
384 switch (p->type) {
385 case PM2_TYPE_PERMEDIA2:
386 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
387 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
388 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
389 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
390 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
391 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
392 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
393 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
394 break;
395 case PM2_TYPE_PERMEDIA2V:
396 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
397 break;
398 }
399}
400
401static void set_aperture(struct pm2fb_par *p, u32 depth)
402{
403 /*
404 * The hardware is little-endian. When used in big-endian
405 * hosts, the on-chip aperture settings are used where
406 * possible to translate from host to card byte order.
407 */
408 WAIT_FIFO(p, 2);
409#ifdef __LITTLE_ENDIAN
410 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
411#else
412 switch (depth) {
413 case 24: /* RGB->BGR */
414 /*
415 * We can't use the aperture to translate host to
416 * card byte order here, so we switch to BGR mode
417 * in pm2fb_set_par().
418 */
419 case 8: /* B->B */
420 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
421 break;
422 case 16: /* HL->LH */
423 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
424 break;
425 case 32: /* RGBA->ABGR */
426 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
427 break;
428 }
429#endif
430
431 /* We don't use aperture two, so this may be superflous */
432 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
433}
434
435static void set_color(struct pm2fb_par *p, unsigned char regno,
436 unsigned char r, unsigned char g, unsigned char b)
437{
438 WAIT_FIFO(p, 4);
439 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
440 wmb();
441 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
442 wmb();
443 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
444 wmb();
445 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
446}
447
448static void set_memclock(struct pm2fb_par *par, u32 clk)
449{
450 int i;
451 unsigned char m, n, p;
452
453 switch (par->type) {
454 case PM2_TYPE_PERMEDIA2V:
455 pm2v_mnp(clk/2, &m, &n, &p);
456 WAIT_FIFO(par, 12);
457 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
458 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
459 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
460 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
461 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
462 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
463 rmb();
464 for (i = 256; i; i--)
465 if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
466 break;
467 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
468 break;
469 case PM2_TYPE_PERMEDIA2:
470 pm2_mnp(clk, &m, &n, &p);
471 WAIT_FIFO(par, 10);
472 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
473 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
474 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
475 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
476 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
477 rmb();
478 for (i = 256; i; i--)
479 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
480 break;
481 break;
482 }
483}
484
485static void set_pixclock(struct pm2fb_par *par, u32 clk)
486{
487 int i;
488 unsigned char m, n, p;
489
490 switch (par->type) {
491 case PM2_TYPE_PERMEDIA2:
492 pm2_mnp(clk, &m, &n, &p);
493 WAIT_FIFO(par, 10);
494 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
495 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
496 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
497 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
498 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
499 rmb();
500 for (i = 256; i; i--)
501 if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
502 break;
503 break;
504 case PM2_TYPE_PERMEDIA2V:
505 pm2v_mnp(clk/2, &m, &n, &p);
506 WAIT_FIFO(par, 8);
507 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
508 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
509 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
510 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
511 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
512 break;
513 }
514}
515
516static void set_video(struct pm2fb_par *p, u32 video)
517{
518 u32 tmp;
519 u32 vsync = video;
520
521 DPRINTK("video = 0x%x\n", video);
522
523 /*
524 * The hardware cursor needs +vsync to recognise vert retrace.
525 * We may not be using the hardware cursor, but the X Glint
526 * driver may well. So always set +hsync/+vsync and then set
527 * the RAMDAC to invert the sync if necessary.
528 */
529 vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
530 vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
531
532 WAIT_FIFO(p, 3);
533 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
534
535 switch (p->type) {
536 case PM2_TYPE_PERMEDIA2:
537 tmp = PM2F_RD_PALETTE_WIDTH_8;
538 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
539 tmp |= 4; /* invert hsync */
540 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
541 tmp |= 8; /* invert vsync */
542 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
543 break;
544 case PM2_TYPE_PERMEDIA2V:
545 tmp = 0;
546 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
547 tmp |= 1; /* invert hsync */
548 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
549 tmp |= 4; /* invert vsync */
550 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
551 break;
552 }
553}
554
555/*
556 * pm2fb_check_var - Optional function. Validates a var passed in.
557 * @var: frame buffer variable screen structure
558 * @info: frame buffer structure that represents a single frame buffer
559 *
560 * Checks to see if the hardware supports the state requested by
561 * var passed in.
562 *
563 * Returns negative errno on error, or zero on success.
564 */
565static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
566{
567 u32 lpitch;
568
569 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
570 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
571 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
572 return -EINVAL;
573 }
574
575 if (var->xres != var->xres_virtual) {
576 DPRINTK("virtual x resolution != "
577 "physical x resolution not supported\n");
578 return -EINVAL;
579 }
580
581 if (var->yres > var->yres_virtual) {
582 DPRINTK("virtual y resolution < "
583 "physical y resolution not possible\n");
584 return -EINVAL;
585 }
586
587 /* permedia cannot blit over 2048 */
588 if (var->yres_virtual > 2047) {
589 var->yres_virtual = 2047;
590 }
591
592 if (var->xoffset) {
593 DPRINTK("xoffset not supported\n");
594 return -EINVAL;
595 }
596
597 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
598 DPRINTK("interlace not supported\n");
599 return -EINVAL;
600 }
601
602 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
603 lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
604
605 if (var->xres < 320 || var->xres > 1600) {
606 DPRINTK("width not supported: %u\n", var->xres);
607 return -EINVAL;
608 }
609
610 if (var->yres < 200 || var->yres > 1200) {
611 DPRINTK("height not supported: %u\n", var->yres);
612 return -EINVAL;
613 }
614
615 if (lpitch * var->yres_virtual > info->fix.smem_len) {
616 DPRINTK("no memory for screen (%ux%ux%u)\n",
617 var->xres, var->yres_virtual, var->bits_per_pixel);
618 return -EINVAL;
619 }
620
621 if (!var->pixclock) {
622 DPRINTK("pixclock is zero\n");
623 return -EINVAL;
624 }
625
626 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
627 DPRINTK("pixclock too high (%ldKHz)\n",
628 PICOS2KHZ(var->pixclock));
629 return -EINVAL;
630 }
631
632 var->transp.offset = 0;
633 var->transp.length = 0;
634 switch (var->bits_per_pixel) {
635 case 8:
636 var->red.length = 8;
637 var->green.length = 8;
638 var->blue.length = 8;
639 break;
640 case 16:
641 var->red.offset = 11;
642 var->red.length = 5;
643 var->green.offset = 5;
644 var->green.length = 6;
645 var->blue.offset = 0;
646 var->blue.length = 5;
647 break;
648 case 32:
649 var->transp.offset = 24;
650 var->transp.length = 8;
651 var->red.offset = 16;
652 var->green.offset = 8;
653 var->blue.offset = 0;
654 var->red.length = 8;
655 var->green.length = 8;
656 var->blue.length = 8;
657 break;
658 case 24:
659#ifdef __BIG_ENDIAN
660 var->red.offset = 0;
661 var->blue.offset = 16;
662#else
663 var->red.offset = 16;
664 var->blue.offset = 0;
665#endif
666 var->green.offset = 8;
667 var->red.length = 8;
668 var->green.length = 8;
669 var->blue.length = 8;
670 break;
671 }
672 var->height = -1;
673 var->width = -1;
674
675 var->accel_flags = 0; /* Can't mmap if this is on */
676
677 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
678 var->xres, var->yres, var->bits_per_pixel);
679 return 0;
680}
681
682/**
683 * pm2fb_set_par - Alters the hardware state.
684 * @info: frame buffer structure that represents a single frame buffer
685 *
686 * Using the fb_var_screeninfo in fb_info we set the resolution of the
687 * this particular framebuffer.
688 */
689static int pm2fb_set_par(struct fb_info *info)
690{
691 struct pm2fb_par *par = info->par;
692 u32 pixclock;
693 u32 width = (info->var.xres_virtual + 7) & ~7;
694 u32 height = info->var.yres_virtual;
695 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
696 u32 hsstart, hsend, hbend, htotal;
697 u32 vsstart, vsend, vbend, vtotal;
698 u32 stride;
699 u32 base;
700 u32 video = 0;
701 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
702 u32 txtmap = 0;
703 u32 pixsize = 0;
704 u32 clrformat = 0;
705 u32 misc = 1; /* 8-bit DAC */
706 u32 xres = (info->var.xres + 31) & ~31;
707 int data64;
708
709 reset_card(par);
710 reset_config(par);
711 clear_palette(par);
712 if (par->memclock)
713 set_memclock(par, par->memclock);
714
715 depth = (depth > 32) ? 32 : depth;
716 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
717
718 pixclock = PICOS2KHZ(info->var.pixclock);
719 if (pixclock > PM2_MAX_PIXCLOCK) {
720 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
721 return -EINVAL;
722 }
723
724 hsstart = to3264(info->var.right_margin, depth, data64);
725 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
726 hbend = hsend + to3264(info->var.left_margin, depth, data64);
727 htotal = to3264(xres, depth, data64) + hbend - 1;
728 vsstart = (info->var.lower_margin)
729 ? info->var.lower_margin - 1
730 : 0; /* FIXME! */
731 vsend = info->var.lower_margin + info->var.vsync_len - 1;
732 vbend = info->var.lower_margin + info->var.vsync_len +
733 info->var.upper_margin;
734 vtotal = info->var.yres + vbend - 1;
735 stride = to3264(width, depth, 1);
736 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
737 if (data64)
738 video |= PM2F_DATA_64_ENABLE;
739
740 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
741 if (lowhsync) {
742 DPRINTK("ignoring +hsync, using -hsync.\n");
743 video |= PM2F_HSYNC_ACT_LOW;
744 } else
745 video |= PM2F_HSYNC_ACT_HIGH;
746 } else
747 video |= PM2F_HSYNC_ACT_LOW;
748
749 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
750 if (lowvsync) {
751 DPRINTK("ignoring +vsync, using -vsync.\n");
752 video |= PM2F_VSYNC_ACT_LOW;
753 } else
754 video |= PM2F_VSYNC_ACT_HIGH;
755 } else
756 video |= PM2F_VSYNC_ACT_LOW;
757
758 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
759 DPRINTK("interlaced not supported\n");
760 return -EINVAL;
761 }
762 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
763 video |= PM2F_LINE_DOUBLE;
764 if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
765 video |= PM2F_VIDEO_ENABLE;
766 par->video = video;
767
768 info->fix.visual =
769 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
770 info->fix.line_length = info->var.xres * depth / 8;
771 info->cmap.len = 256;
772
773 /*
774 * Settings calculated. Now write them out.
775 */
776 if (par->type == PM2_TYPE_PERMEDIA2V) {
777 WAIT_FIFO(par, 1);
778 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
779 }
780
781 set_aperture(par, depth);
782
783 mb();
784 WAIT_FIFO(par, 19);
785 switch (depth) {
786 case 8:
787 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
788 clrformat = 0x2e;
789 break;
790 case 16:
791 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
792 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
793 txtmap = PM2F_TEXTEL_SIZE_16;
794 pixsize = 1;
795 clrformat = 0x70;
796 misc |= 8;
797 break;
798 case 32:
799 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
800 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
801 txtmap = PM2F_TEXTEL_SIZE_32;
802 pixsize = 2;
803 clrformat = 0x20;
804 misc |= 8;
805 break;
806 case 24:
807 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
808 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
809 txtmap = PM2F_TEXTEL_SIZE_24;
810 pixsize = 4;
811 clrformat = 0x20;
812 misc |= 8;
813 break;
814 }
815 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
816 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
817 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
818 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
819 pm2_WR(par, PM2R_H_TOTAL, htotal);
820 pm2_WR(par, PM2R_HS_START, hsstart);
821 pm2_WR(par, PM2R_HS_END, hsend);
822 pm2_WR(par, PM2R_HG_END, hbend);
823 pm2_WR(par, PM2R_HB_END, hbend);
824 pm2_WR(par, PM2R_V_TOTAL, vtotal);
825 pm2_WR(par, PM2R_VS_START, vsstart);
826 pm2_WR(par, PM2R_VS_END, vsend);
827 pm2_WR(par, PM2R_VB_END, vbend);
828 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
829 wmb();
830 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
831 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
832 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
833 wmb();
834 pm2_WR(par, PM2R_SCREEN_BASE, base);
835 wmb();
836 set_video(par, video);
837 WAIT_FIFO(par, 10);
838 switch (par->type) {
839 case PM2_TYPE_PERMEDIA2:
840 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
841 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
842 (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
843 break;
844 case PM2_TYPE_PERMEDIA2V:
845 pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
846 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
847 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
848 pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
849 pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
850 break;
851 }
852 set_pixclock(par, pixclock);
853 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
854 info->var.xres, info->var.yres, info->var.bits_per_pixel);
855 return 0;
856}
857
858/**
859 * pm2fb_setcolreg - Sets a color register.
860 * @regno: boolean, 0 copy local, 1 get_user() function
861 * @red: frame buffer colormap structure
862 * @green: The green value which can be up to 16 bits wide
863 * @blue: The blue value which can be up to 16 bits wide.
864 * @transp: If supported the alpha value which can be up to 16 bits wide.
865 * @info: frame buffer info structure
866 *
867 * Set a single color register. The values supplied have a 16 bit
868 * magnitude which needs to be scaled in this function for the hardware.
869 * Pretty much a direct lift from tdfxfb.c.
870 *
871 * Returns negative errno on error, or zero on success.
872 */
873static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
874 unsigned blue, unsigned transp,
875 struct fb_info *info)
876{
877 struct pm2fb_par *par = info->par;
878
879 if (regno >= info->cmap.len) /* no. of hw registers */
880 return -EINVAL;
881 /*
882 * Program hardware... do anything you want with transp
883 */
884
885 /* grayscale works only partially under directcolor */
886 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
887 if (info->var.grayscale)
888 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
889
890 /* Directcolor:
891 * var->{color}.offset contains start of bitfield
892 * var->{color}.length contains length of bitfield
893 * {hardwarespecific} contains width of DAC
894 * cmap[X] is programmed to
895 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
896 * RAMDAC[X] is programmed to (red, green, blue)
897 *
898 * Pseudocolor:
899 * uses offset = 0 && length = DAC register width.
900 * var->{color}.offset is 0
901 * var->{color}.length contains width of DAC
902 * cmap is not used
903 * DAC[X] is programmed to (red, green, blue)
904 * Truecolor:
905 * does not use RAMDAC (usually has 3 of them).
906 * var->{color}.offset contains start of bitfield
907 * var->{color}.length contains length of bitfield
908 * cmap is programmed to
909 * (red << red.offset) | (green << green.offset) |
910 * (blue << blue.offset) | (transp << transp.offset)
911 * RAMDAC does not exist
912 */
913#define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
914 switch (info->fix.visual) {
915 case FB_VISUAL_TRUECOLOR:
916 case FB_VISUAL_PSEUDOCOLOR:
917 red = CNVT_TOHW(red, info->var.red.length);
918 green = CNVT_TOHW(green, info->var.green.length);
919 blue = CNVT_TOHW(blue, info->var.blue.length);
920 transp = CNVT_TOHW(transp, info->var.transp.length);
921 break;
922 case FB_VISUAL_DIRECTCOLOR:
923 /* example here assumes 8 bit DAC. Might be different
924 * for your hardware */
925 red = CNVT_TOHW(red, 8);
926 green = CNVT_TOHW(green, 8);
927 blue = CNVT_TOHW(blue, 8);
928 /* hey, there is bug in transp handling... */
929 transp = CNVT_TOHW(transp, 8);
930 break;
931 }
932#undef CNVT_TOHW
933 /* Truecolor has hardware independent palette */
934 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
935 u32 v;
936
937 if (regno >= 16)
938 return -EINVAL;
939
940 v = (red << info->var.red.offset) |
941 (green << info->var.green.offset) |
942 (blue << info->var.blue.offset) |
943 (transp << info->var.transp.offset);
944
945 switch (info->var.bits_per_pixel) {
946 case 8:
947 break;
948 case 16:
949 case 24:
950 case 32:
951 par->palette[regno] = v;
952 break;
953 }
954 return 0;
955 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
956 set_color(par, regno, red, green, blue);
957
958 return 0;
959}
960
961/**
962 * pm2fb_pan_display - Pans the display.
963 * @var: frame buffer variable screen structure
964 * @info: frame buffer structure that represents a single frame buffer
965 *
966 * Pan (or wrap, depending on the `vmode' field) the display using the
967 * `xoffset' and `yoffset' fields of the `var' structure.
968 * If the values don't fit, return -EINVAL.
969 *
970 * Returns negative errno on error, or zero on success.
971 *
972 */
973static int pm2fb_pan_display(struct fb_var_screeninfo *var,
974 struct fb_info *info)
975{
976 struct pm2fb_par *p = info->par;
977 u32 base;
978 u32 depth = (info->var.bits_per_pixel + 7) & ~7;
979 u32 xres = (info->var.xres + 31) & ~31;
980
981 depth = (depth > 32) ? 32 : depth;
982 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
983 WAIT_FIFO(p, 1);
984 pm2_WR(p, PM2R_SCREEN_BASE, base);
985 return 0;
986}
987
988/**
989 * pm2fb_blank - Blanks the display.
990 * @blank_mode: the blank mode we want.
991 * @info: frame buffer structure that represents a single frame buffer
992 *
993 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
994 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
995 * video mode which doesn't support it. Implements VESA suspend
996 * and powerdown modes on hardware that supports disabling hsync/vsync:
997 * blank_mode == 2: suspend vsync
998 * blank_mode == 3: suspend hsync
999 * blank_mode == 4: powerdown
1000 *
1001 * Returns negative errno on error, or zero on success.
1002 *
1003 */
1004static int pm2fb_blank(int blank_mode, struct fb_info *info)
1005{
1006 struct pm2fb_par *par = info->par;
1007 u32 video = par->video;
1008
1009 DPRINTK("blank_mode %d\n", blank_mode);
1010
1011 switch (blank_mode) {
1012 case FB_BLANK_UNBLANK:
1013 /* Screen: On */
1014 video |= PM2F_VIDEO_ENABLE;
1015 break;
1016 case FB_BLANK_NORMAL:
1017 /* Screen: Off */
1018 video &= ~PM2F_VIDEO_ENABLE;
1019 break;
1020 case FB_BLANK_VSYNC_SUSPEND:
1021 /* VSync: Off */
1022 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
1023 break;
1024 case FB_BLANK_HSYNC_SUSPEND:
1025 /* HSync: Off */
1026 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1027 break;
1028 case FB_BLANK_POWERDOWN:
1029 /* HSync: Off, VSync: Off */
1030 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
1031 break;
1032 }
1033 set_video(par, video);
1034 return 0;
1035}
1036
1037static int pm2fb_sync(struct fb_info *info)
1038{
1039 struct pm2fb_par *par = info->par;
1040
1041 WAIT_FIFO(par, 1);
1042 pm2_WR(par, PM2R_SYNC, 0);
1043 mb();
1044 do {
1045 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1046 cpu_relax();
1047 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1048
1049 return 0;
1050}
1051
1052static void pm2fb_fillrect(struct fb_info *info,
1053 const struct fb_fillrect *region)
1054{
1055 struct pm2fb_par *par = info->par;
1056 struct fb_fillrect modded;
1057 int vxres, vyres;
1058 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1059 ((u32 *)info->pseudo_palette)[region->color] : region->color;
1060
1061 if (info->state != FBINFO_STATE_RUNNING)
1062 return;
1063 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1064 region->rop != ROP_COPY ) {
1065 cfb_fillrect(info, region);
1066 return;
1067 }
1068
1069 vxres = info->var.xres_virtual;
1070 vyres = info->var.yres_virtual;
1071
1072 memcpy(&modded, region, sizeof(struct fb_fillrect));
1073
1074 if (!modded.width || !modded.height ||
1075 modded.dx >= vxres || modded.dy >= vyres)
1076 return;
1077
1078 if (modded.dx + modded.width > vxres)
1079 modded.width = vxres - modded.dx;
1080 if (modded.dy + modded.height > vyres)
1081 modded.height = vyres - modded.dy;
1082
1083 if (info->var.bits_per_pixel == 8)
1084 color |= color << 8;
1085 if (info->var.bits_per_pixel <= 16)
1086 color |= color << 16;
1087
1088 WAIT_FIFO(par, 3);
1089 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
1090 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1091 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1092 if (info->var.bits_per_pixel != 24) {
1093 WAIT_FIFO(par, 2);
1094 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1095 wmb();
1096 pm2_WR(par, PM2R_RENDER,
1097 PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
1098 } else {
1099 WAIT_FIFO(par, 4);
1100 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1101 pm2_WR(par, PM2R_CONSTANT_COLOR, color);
1102 wmb();
1103 pm2_WR(par, PM2R_RENDER,
1104 PM2F_RENDER_RECTANGLE |
1105 PM2F_INCREASE_X | PM2F_INCREASE_Y );
1106 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1107 }
1108}
1109
1110static void pm2fb_copyarea(struct fb_info *info,
1111 const struct fb_copyarea *area)
1112{
1113 struct pm2fb_par *par = info->par;
1114 struct fb_copyarea modded;
1115 u32 vxres, vyres;
1116
1117 if (info->state != FBINFO_STATE_RUNNING)
1118 return;
1119 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1120 cfb_copyarea(info, area);
1121 return;
1122 }
1123
1124 memcpy(&modded, area, sizeof(struct fb_copyarea));
1125
1126 vxres = info->var.xres_virtual;
1127 vyres = info->var.yres_virtual;
1128
1129 if (!modded.width || !modded.height ||
1130 modded.sx >= vxres || modded.sy >= vyres ||
1131 modded.dx >= vxres || modded.dy >= vyres)
1132 return;
1133
1134 if (modded.sx + modded.width > vxres)
1135 modded.width = vxres - modded.sx;
1136 if (modded.dx + modded.width > vxres)
1137 modded.width = vxres - modded.dx;
1138 if (modded.sy + modded.height > vyres)
1139 modded.height = vyres - modded.sy;
1140 if (modded.dy + modded.height > vyres)
1141 modded.height = vyres - modded.dy;
1142
1143 WAIT_FIFO(par, 5);
1144 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1145 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1146 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1147 ((modded.sy - modded.dy) & 0xfff) << 16 |
1148 ((modded.sx - modded.dx) & 0xfff));
1149 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
1150 pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
1151 wmb();
1152 pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
1153 (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
1154 (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
1155}
1156
1157static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
1158{
1159 struct pm2fb_par *par = info->par;
1160 u32 height = image->height;
1161 u32 fgx, bgx;
1162 const u32 *src = (const u32 *)image->data;
1163 u32 xres = (info->var.xres + 31) & ~31;
1164 int raster_mode = 1; /* invert bits */
1165
1166#ifdef __LITTLE_ENDIAN
1167 raster_mode |= 3 << 7; /* reverse byte order */
1168#endif
1169
1170 if (info->state != FBINFO_STATE_RUNNING)
1171 return;
1172 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
1173 cfb_imageblit(info, image);
1174 return;
1175 }
1176 switch (info->fix.visual) {
1177 case FB_VISUAL_PSEUDOCOLOR:
1178 fgx = image->fg_color;
1179 bgx = image->bg_color;
1180 break;
1181 case FB_VISUAL_TRUECOLOR:
1182 default:
1183 fgx = par->palette[image->fg_color];
1184 bgx = par->palette[image->bg_color];
1185 break;
1186 }
1187 if (info->var.bits_per_pixel == 8) {
1188 fgx |= fgx << 8;
1189 bgx |= bgx << 8;
1190 }
1191 if (info->var.bits_per_pixel <= 16) {
1192 fgx |= fgx << 16;
1193 bgx |= bgx << 16;
1194 }
1195
1196 WAIT_FIFO(par, 13);
1197 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
1198 pm2_WR(par, PM2R_SCISSOR_MIN_XY,
1199 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1200 pm2_WR(par, PM2R_SCISSOR_MAX_XY,
1201 (((image->dy + image->height) & 0x0fff) << 16) |
1202 ((image->dx + image->width) & 0x0fff));
1203 pm2_WR(par, PM2R_SCISSOR_MODE, 1);
1204 /* GXcopy & UNIT_ENABLE */
1205 pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
1206 pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
1207 ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
1208 pm2_WR(par, PM2R_RECTANGLE_SIZE,
1209 ((image->height & 0x0fff) << 16) |
1210 ((image->width) & 0x0fff));
1211 if (info->var.bits_per_pixel == 24) {
1212 pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
1213 /* clear area */
1214 pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
1215 pm2_WR(par, PM2R_RENDER,
1216 PM2F_RENDER_RECTANGLE |
1217 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1218 /* BitMapPackEachScanline */
1219 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9));
1220 pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
1221 pm2_WR(par, PM2R_RENDER,
1222 PM2F_RENDER_RECTANGLE |
1223 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1224 PM2F_RENDER_SYNC_ON_BIT_MASK);
1225 } else {
1226 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1227 /* clear area */
1228 pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
1229 pm2_WR(par, PM2R_RENDER,
1230 PM2F_RENDER_RECTANGLE |
1231 PM2F_RENDER_FASTFILL |
1232 PM2F_INCREASE_X | PM2F_INCREASE_Y);
1233 pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode);
1234 pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
1235 pm2_WR(par, PM2R_RENDER,
1236 PM2F_RENDER_RECTANGLE |
1237 PM2F_INCREASE_X | PM2F_INCREASE_Y |
1238 PM2F_RENDER_FASTFILL |
1239 PM2F_RENDER_SYNC_ON_BIT_MASK);
1240 }
1241
1242 while (height--) {
1243 int width = ((image->width + 7) >> 3)
1244 + info->pixmap.scan_align - 1;
1245 width >>= 2;
1246 WAIT_FIFO(par, width);
1247 while (width--) {
1248 pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
1249 src++;
1250 }
1251 }
1252 WAIT_FIFO(par, 3);
1253 pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
1254 pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
1255 pm2_WR(par, PM2R_SCISSOR_MODE, 0);
1256}
1257
1258/*
1259 * Hardware cursor support.
1260 */
1261static const u8 cursor_bits_lookup[16] = {
1262 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
1263 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
1264};
1265
1266static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1267{
1268 struct pm2fb_par *par = info->par;
1269 u8 mode = PM2F_CURSORMODE_TYPE_X;
1270 int x = cursor->image.dx - info->var.xoffset;
1271 int y = cursor->image.dy - info->var.yoffset;
1272
1273 if (cursor->enable)
1274 mode |= PM2F_CURSORMODE_CURSOR_ENABLE;
1275
1276 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode);
1277
1278 if (!cursor->enable)
1279 x = 2047; /* push it outside display */
1280 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff);
1281 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf);
1282 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff);
1283 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf);
1284
1285 /*
1286 * If the cursor is not be changed this means either we want the
1287 * current cursor state (if enable is set) or we want to query what
1288 * we can do with the cursor (if enable is not set)
1289 */
1290 if (!cursor->set)
1291 return 0;
1292
1293 if (cursor->set & FB_CUR_SETHOT) {
1294 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT,
1295 cursor->hot.x & 0x3f);
1296 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT,
1297 cursor->hot.y & 0x3f);
1298 }
1299
1300 if (cursor->set & FB_CUR_SETCMAP) {
1301 u32 fg_idx = cursor->image.fg_color;
1302 u32 bg_idx = cursor->image.bg_color;
1303 struct fb_cmap cmap = info->cmap;
1304
1305 /* the X11 driver says one should use these color registers */
1306 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8);
1307 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0,
1308 cmap.red[bg_idx] >> 8 );
1309 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1,
1310 cmap.green[bg_idx] >> 8 );
1311 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2,
1312 cmap.blue[bg_idx] >> 8 );
1313
1314 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3,
1315 cmap.red[fg_idx] >> 8 );
1316 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4,
1317 cmap.green[fg_idx] >> 8 );
1318 pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5,
1319 cmap.blue[fg_idx] >> 8 );
1320 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1321 }
1322
1323 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1324 u8 *bitmap = (u8 *)cursor->image.data;
1325 u8 *mask = (u8 *)cursor->mask;
1326 int i;
1327 int pos = PM2VI_RD_CURSOR_PATTERN;
1328
1329 for (i = 0; i < cursor->image.height; i++) {
1330 int j = (cursor->image.width + 7) >> 3;
1331 int k = 8 - j;
1332
1333 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1334
1335 for (; j > 0; j--) {
1336 u8 data = *bitmap ^ *mask;
1337
1338 if (cursor->rop == ROP_COPY)
1339 data = *mask & *bitmap;
1340 /* Upper 4 bits of bitmap data */
1341 pm2v_RDAC_WR(par, pos++,
1342 cursor_bits_lookup[data >> 4] |
1343 (cursor_bits_lookup[*mask >> 4] << 1));
1344 /* Lower 4 bits of bitmap */
1345 pm2v_RDAC_WR(par, pos++,
1346 cursor_bits_lookup[data & 0xf] |
1347 (cursor_bits_lookup[*mask & 0xf] << 1));
1348 bitmap++;
1349 mask++;
1350 }
1351 for (; k > 0; k--) {
1352 pm2v_RDAC_WR(par, pos++, 0);
1353 pm2v_RDAC_WR(par, pos++, 0);
1354 }
1355 }
1356
1357 while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) {
1358 pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
1359 pm2v_RDAC_WR(par, pos++, 0);
1360 }
1361
1362 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
1363 }
1364 return 0;
1365}
1366
1367static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1368{
1369 struct pm2fb_par *par = info->par;
1370 u8 mode;
1371
1372 if (!hwcursor)
1373 return -EINVAL; /* just to force soft_cursor() call */
1374
1375 /* Too large of a cursor or wrong bpp :-( */
1376 if (cursor->image.width > 64 ||
1377 cursor->image.height > 64 ||
1378 cursor->image.depth > 1)
1379 return -EINVAL;
1380
1381 if (par->type == PM2_TYPE_PERMEDIA2V)
1382 return pm2vfb_cursor(info, cursor);
1383
1384 mode = 0x40;
1385 if (cursor->enable)
1386 mode = 0x43;
1387
1388 pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode);
1389
1390 /*
1391 * If the cursor is not be changed this means either we want the
1392 * current cursor state (if enable is set) or we want to query what
1393 * we can do with the cursor (if enable is not set)
1394 */
1395 if (!cursor->set)
1396 return 0;
1397
1398 if (cursor->set & FB_CUR_SETPOS) {
1399 int x = cursor->image.dx - info->var.xoffset + 63;
1400 int y = cursor->image.dy - info->var.yoffset + 63;
1401
1402 WAIT_FIFO(par, 4);
1403 pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff);
1404 pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7);
1405 pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff);
1406 pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7);
1407 }
1408
1409 if (cursor->set & FB_CUR_SETCMAP) {
1410 u32 fg_idx = cursor->image.fg_color;
1411 u32 bg_idx = cursor->image.bg_color;
1412
1413 WAIT_FIFO(par, 7);
1414 pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1);
1415 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1416 info->cmap.red[bg_idx] >> 8);
1417 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1418 info->cmap.green[bg_idx] >> 8);
1419 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1420 info->cmap.blue[bg_idx] >> 8);
1421
1422 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1423 info->cmap.red[fg_idx] >> 8);
1424 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1425 info->cmap.green[fg_idx] >> 8);
1426 pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
1427 info->cmap.blue[fg_idx] >> 8);
1428 }
1429
1430 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1431 u8 *bitmap = (u8 *)cursor->image.data;
1432 u8 *mask = (u8 *)cursor->mask;
1433 int i;
1434
1435 WAIT_FIFO(par, 1);
1436 pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
1437
1438 for (i = 0; i < cursor->image.height; i++) {
1439 int j = (cursor->image.width + 7) >> 3;
1440 int k = 8 - j;
1441
1442 WAIT_FIFO(par, 8);
1443 for (; j > 0; j--) {
1444 u8 data = *bitmap ^ *mask;
1445
1446 if (cursor->rop == ROP_COPY)
1447 data = *mask & *bitmap;
1448 /* bitmap data */
1449 pm2_WR(par, PM2R_RD_CURSOR_DATA, data);
1450 bitmap++;
1451 mask++;
1452 }
1453 for (; k > 0; k--)
1454 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1455 }
1456 for (; i < 64; i++) {
1457 int j = 8;
1458 WAIT_FIFO(par, 8);
1459 while (j-- > 0)
1460 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1461 }
1462
1463 mask = (u8 *)cursor->mask;
1464 for (i = 0; i < cursor->image.height; i++) {
1465 int j = (cursor->image.width + 7) >> 3;
1466 int k = 8 - j;
1467
1468 WAIT_FIFO(par, 8);
1469 for (; j > 0; j--) {
1470 /* mask */
1471 pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask);
1472 mask++;
1473 }
1474 for (; k > 0; k--)
1475 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1476 }
1477 for (; i < 64; i++) {
1478 int j = 8;
1479 WAIT_FIFO(par, 8);
1480 while (j-- > 0)
1481 pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
1482 }
1483 }
1484 return 0;
1485}
1486
1487/* ------------ Hardware Independent Functions ------------ */
1488
1489/*
1490 * Frame buffer operations
1491 */
1492
1493static const struct fb_ops pm2fb_ops = {
1494 .owner = THIS_MODULE,
1495 __FB_DEFAULT_IOMEM_OPS_RDWR,
1496 .fb_check_var = pm2fb_check_var,
1497 .fb_set_par = pm2fb_set_par,
1498 .fb_setcolreg = pm2fb_setcolreg,
1499 .fb_blank = pm2fb_blank,
1500 .fb_pan_display = pm2fb_pan_display,
1501 .fb_fillrect = pm2fb_fillrect,
1502 .fb_copyarea = pm2fb_copyarea,
1503 .fb_imageblit = pm2fb_imageblit,
1504 .fb_sync = pm2fb_sync,
1505 .fb_cursor = pm2fb_cursor,
1506 __FB_DEFAULT_IOMEM_OPS_MMAP,
1507};
1508
1509/*
1510 * PCI stuff
1511 */
1512
1513
1514/**
1515 * pm2fb_probe - Initialise and allocate resource for PCI device.
1516 *
1517 * @pdev: PCI device.
1518 * @id: PCI device ID.
1519 */
1520static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1521{
1522 struct pm2fb_par *default_par;
1523 struct fb_info *info;
1524 int err;
1525 int retval = -ENXIO;
1526
1527 err = aperture_remove_conflicting_pci_devices(pdev, "pm2fb");
1528 if (err)
1529 return err;
1530
1531 err = pci_enable_device(pdev);
1532 if (err) {
1533 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1534 return err;
1535 }
1536
1537 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1538 if (!info) {
1539 err = -ENOMEM;
1540 goto err_exit_disable;
1541 }
1542 default_par = info->par;
1543
1544 switch (pdev->device) {
1545 case PCI_DEVICE_ID_TI_TVP4020:
1546 strcpy(pm2fb_fix.id, "TVP4020");
1547 default_par->type = PM2_TYPE_PERMEDIA2;
1548 break;
1549 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1550 strcpy(pm2fb_fix.id, "Permedia2");
1551 default_par->type = PM2_TYPE_PERMEDIA2;
1552 break;
1553 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1554 strcpy(pm2fb_fix.id, "Permedia2v");
1555 default_par->type = PM2_TYPE_PERMEDIA2V;
1556 break;
1557 }
1558
1559 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1560 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1561
1562#if defined(__BIG_ENDIAN)
1563 /*
1564 * PM2 has a 64k register file, mapped twice in 128k. Lower
1565 * map is little-endian, upper map is big-endian.
1566 */
1567 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1568 DPRINTK("Adjusting register base for big-endian.\n");
1569#endif
1570 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1571
1572 /* Registers - request region and map it. */
1573 if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1574 "pm2fb regbase")) {
1575 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1576 goto err_exit_neither;
1577 }
1578 default_par->v_regs =
1579 ioremap(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1580 if (!default_par->v_regs) {
1581 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1582 pm2fb_fix.id);
1583 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1584 goto err_exit_neither;
1585 }
1586
1587 /* Stash away memory register info for use when we reset the board */
1588 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1589 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1590 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1591 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1592 default_par->mem_control, default_par->boot_address,
1593 default_par->mem_config);
1594
1595 if (default_par->mem_control == 0 &&
1596 default_par->boot_address == 0x31 &&
1597 default_par->mem_config == 0x259fffff) {
1598 default_par->memclock = CVPPC_MEMCLOCK;
1599 default_par->mem_control = 0;
1600 default_par->boot_address = 0x20;
1601 default_par->mem_config = 0xe6002021;
1602 if (pdev->subsystem_vendor == 0x1048 &&
1603 pdev->subsystem_device == 0x0a31) {
1604 DPRINTK("subsystem_vendor: %04x, "
1605 "subsystem_device: %04x\n",
1606 pdev->subsystem_vendor, pdev->subsystem_device);
1607 DPRINTK("We have not been initialized by VGA BIOS and "
1608 "are running on an Elsa Winner 2000 Office\n");
1609 DPRINTK("Initializing card timings manually...\n");
1610 default_par->memclock = 100000;
1611 }
1612 if (pdev->subsystem_vendor == 0x3d3d &&
1613 pdev->subsystem_device == 0x0100) {
1614 DPRINTK("subsystem_vendor: %04x, "
1615 "subsystem_device: %04x\n",
1616 pdev->subsystem_vendor, pdev->subsystem_device);
1617 DPRINTK("We have not been initialized by VGA BIOS and "
1618 "are running on an 3dlabs reference board\n");
1619 DPRINTK("Initializing card timings manually...\n");
1620 default_par->memclock = 74894;
1621 }
1622 }
1623
1624 /* Now work out how big lfb is going to be. */
1625 switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1626 case PM2F_MEM_BANKS_1:
1627 pm2fb_fix.smem_len = 0x200000;
1628 break;
1629 case PM2F_MEM_BANKS_2:
1630 pm2fb_fix.smem_len = 0x400000;
1631 break;
1632 case PM2F_MEM_BANKS_3:
1633 pm2fb_fix.smem_len = 0x600000;
1634 break;
1635 case PM2F_MEM_BANKS_4:
1636 pm2fb_fix.smem_len = 0x800000;
1637 break;
1638 }
1639 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1640
1641 /* Linear frame buffer - request region and map it. */
1642 if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1643 "pm2fb smem")) {
1644 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1645 goto err_exit_mmio;
1646 }
1647 info->screen_base =
1648 ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1649 if (!info->screen_base) {
1650 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1651 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1652 goto err_exit_mmio;
1653 }
1654
1655 if (!nomtrr)
1656 default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start,
1657 pm2fb_fix.smem_len);
1658
1659 info->fbops = &pm2fb_ops;
1660 info->fix = pm2fb_fix;
1661 info->pseudo_palette = default_par->palette;
1662 info->flags = FBINFO_HWACCEL_YPAN |
1663 FBINFO_HWACCEL_COPYAREA |
1664 FBINFO_HWACCEL_IMAGEBLIT |
1665 FBINFO_HWACCEL_FILLRECT;
1666
1667 info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
1668 if (!info->pixmap.addr) {
1669 retval = -ENOMEM;
1670 goto err_exit_pixmap;
1671 }
1672 info->pixmap.size = PM2_PIXMAP_SIZE;
1673 info->pixmap.buf_align = 4;
1674 info->pixmap.scan_align = 4;
1675 info->pixmap.access_align = 32;
1676 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1677
1678 if (noaccel) {
1679 printk(KERN_DEBUG "disabling acceleration\n");
1680 info->flags |= FBINFO_HWACCEL_DISABLED;
1681 info->pixmap.scan_align = 1;
1682 }
1683
1684 if (!mode_option)
1685 mode_option = "640x480@60";
1686
1687 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1688 if (!err || err == 4)
1689 info->var = pm2fb_var;
1690
1691 retval = fb_alloc_cmap(&info->cmap, 256, 0);
1692 if (retval < 0)
1693 goto err_exit_both;
1694
1695 retval = register_framebuffer(info);
1696 if (retval < 0)
1697 goto err_exit_all;
1698
1699 fb_info(info, "%s frame buffer device, memory = %dK\n",
1700 info->fix.id, pm2fb_fix.smem_len / 1024);
1701
1702 /*
1703 * Our driver data
1704 */
1705 pci_set_drvdata(pdev, info);
1706
1707 return 0;
1708
1709 err_exit_all:
1710 fb_dealloc_cmap(&info->cmap);
1711 err_exit_both:
1712 kfree(info->pixmap.addr);
1713 err_exit_pixmap:
1714 arch_phys_wc_del(default_par->wc_cookie);
1715 iounmap(info->screen_base);
1716 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1717 err_exit_mmio:
1718 iounmap(default_par->v_regs);
1719 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1720 err_exit_neither:
1721 framebuffer_release(info);
1722 err_exit_disable:
1723 pci_disable_device(pdev);
1724 return retval;
1725}
1726
1727/**
1728 * pm2fb_remove - Release all device resources.
1729 *
1730 * @pdev: PCI device to clean up.
1731 */
1732static void pm2fb_remove(struct pci_dev *pdev)
1733{
1734 struct fb_info *info = pci_get_drvdata(pdev);
1735 struct fb_fix_screeninfo *fix = &info->fix;
1736 struct pm2fb_par *par = info->par;
1737
1738 unregister_framebuffer(info);
1739 arch_phys_wc_del(par->wc_cookie);
1740 iounmap(info->screen_base);
1741 release_mem_region(fix->smem_start, fix->smem_len);
1742 iounmap(par->v_regs);
1743 release_mem_region(fix->mmio_start, fix->mmio_len);
1744
1745 fb_dealloc_cmap(&info->cmap);
1746 kfree(info->pixmap.addr);
1747 framebuffer_release(info);
1748 pci_disable_device(pdev);
1749}
1750
1751static const struct pci_device_id pm2fb_id_table[] = {
1752 { PCI_VDEVICE(TI, PCI_DEVICE_ID_TI_TVP4020) },
1753 { PCI_VDEVICE(3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2) },
1754 { PCI_VDEVICE(3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V) },
1755 { }
1756};
1757
1758static struct pci_driver pm2fb_driver = {
1759 .name = "pm2fb",
1760 .id_table = pm2fb_id_table,
1761 .probe = pm2fb_probe,
1762 .remove = pm2fb_remove,
1763};
1764
1765MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1766
1767
1768#ifndef MODULE
1769/*
1770 * Parse user specified options.
1771 *
1772 * This is, comma-separated options following `video=pm2fb:'.
1773 */
1774static int __init pm2fb_setup(char *options)
1775{
1776 char *this_opt;
1777
1778 if (!options || !*options)
1779 return 0;
1780
1781 while ((this_opt = strsep(&options, ",")) != NULL) {
1782 if (!*this_opt)
1783 continue;
1784 if (!strcmp(this_opt, "lowhsync"))
1785 lowhsync = 1;
1786 else if (!strcmp(this_opt, "lowvsync"))
1787 lowvsync = 1;
1788 else if (!strncmp(this_opt, "hwcursor=", 9))
1789 hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
1790 else if (!strncmp(this_opt, "nomtrr", 6))
1791 nomtrr = 1;
1792 else if (!strncmp(this_opt, "noaccel", 7))
1793 noaccel = 1;
1794 else
1795 mode_option = this_opt;
1796 }
1797 return 0;
1798}
1799#endif
1800
1801
1802static int __init pm2fb_init(void)
1803{
1804#ifndef MODULE
1805 char *option = NULL;
1806#endif
1807
1808 if (fb_modesetting_disabled("pm2fb"))
1809 return -ENODEV;
1810
1811#ifndef MODULE
1812 if (fb_get_options("pm2fb", &option))
1813 return -ENODEV;
1814 pm2fb_setup(option);
1815#endif
1816
1817 return pci_register_driver(&pm2fb_driver);
1818}
1819
1820module_init(pm2fb_init);
1821
1822#ifdef MODULE
1823/*
1824 * Cleanup
1825 */
1826
1827static void __exit pm2fb_exit(void)
1828{
1829 pci_unregister_driver(&pm2fb_driver);
1830}
1831#endif
1832
1833#ifdef MODULE
1834module_exit(pm2fb_exit);
1835
1836module_param(mode_option, charp, 0);
1837MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
1838module_param_named(mode, mode_option, charp, 0);
1839MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
1840module_param(lowhsync, bool, 0);
1841MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1842module_param(lowvsync, bool, 0);
1843MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1844module_param(noaccel, bool, 0);
1845MODULE_PARM_DESC(noaccel, "Disable acceleration");
1846module_param(hwcursor, int, 0644);
1847MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
1848 "(1=enable, 0=disable, default=1)");
1849module_param(nomtrr, bool, 0);
1850MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
1851
1852MODULE_AUTHOR("Jim Hague <[email protected]>");
1853MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1854MODULE_LICENSE("GPL");
1855#endif