| 1 | |
| 2 | * Silicon Motion SM712 frame buffer device
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| 3 | *
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| 4 | * Copyright (C) 2006 Silicon Motion Technology Corp.
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| 5 | * Authors: Ge Wang, [email protected]
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| 6 | * Boyod [email protected]
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| 7 | *
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| 8 | * Copyright (C) 2009 Lemote, Inc.
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| 9 | * Author: Wu Zhangjin, [email protected]
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| 10 | *
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| 11 | * This file is subject to the terms and conditions of the GNU General Public
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| 12 | * License. See the file COPYING in the main directory of this archive for
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| 13 | * more details.
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| 14 |
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| 15 |
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| 16 | #define FB_ACCEL_SMI_LYNX 88
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| 17 |
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| 18 | #define SCREEN_X_RES 1024
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| 19 | #define SCREEN_Y_RES_PC 768
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| 20 | #define SCREEN_Y_RES_NETBOOK 600
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| 21 | #define SCREEN_BPP 16
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| 22 |
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| 23 | #define dac_reg (0x3c8)
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| 24 | #define dac_val (0x3c9)
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| 25 |
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| 26 | extern void __iomem *smtc_regbaseaddress;
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| 27 | #define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
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| 28 |
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| 29 | #define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
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| 30 |
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| 31 | #define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
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| 32 | #define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
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| 33 | #define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
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| 34 | #define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
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| 35 | #define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
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| 36 | #define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
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| 37 | #define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
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| 38 | #define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
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| 39 | #define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
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| 40 | #define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
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| 41 |
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| 42 | static inline void smtc_crtcw(int reg, int val)
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| 43 | {
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| 44 | smtc_mmiowb(reg, 0x3d4);
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| 45 | smtc_mmiowb(val, 0x3d5);
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| 46 | }
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| 47 |
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| 48 | static inline void smtc_grphw(int reg, int val)
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| 49 | {
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| 50 | smtc_mmiowb(reg, 0x3ce);
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| 51 | smtc_mmiowb(val, 0x3cf);
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| 52 | }
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| 53 |
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| 54 | static inline void smtc_attrw(int reg, int val)
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| 55 | {
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| 56 | smtc_mmiorb(0x3da);
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| 57 | smtc_mmiowb(reg, 0x3c0);
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| 58 | smtc_mmiorb(0x3c1);
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| 59 | smtc_mmiowb(val, 0x3c0);
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| 60 | }
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| 61 |
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| 62 | static inline void smtc_seqw(int reg, int val)
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| 63 | {
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| 64 | smtc_mmiowb(reg, 0x3c4);
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| 65 | smtc_mmiowb(val, 0x3c5);
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| 66 | }
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| 67 |
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| 68 | static inline unsigned int smtc_seqr(int reg)
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| 69 | {
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| 70 | smtc_mmiowb(reg, 0x3c4);
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| 71 | return smtc_mmiorb(0x3c5);
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| 72 | }
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| 73 |
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| 74 | |
| 75 |
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| 76 |
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| 77 | struct modeinit {
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| 78 | int mmsizex;
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| 79 | int mmsizey;
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| 80 | int bpp;
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| 81 | int hz;
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| 82 | unsigned char init_misc;
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| 83 | unsigned char init_sr00_sr04[SIZE_SR00_SR04];
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| 84 | unsigned char init_sr10_sr24[SIZE_SR10_SR24];
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| 85 | unsigned char init_sr30_sr75[SIZE_SR30_SR75];
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| 86 | unsigned char init_sr80_sr93[SIZE_SR80_SR93];
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| 87 | unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
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| 88 | unsigned char init_gr00_gr08[SIZE_GR00_GR08];
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| 89 | unsigned char init_ar00_ar14[SIZE_AR00_AR14];
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| 90 | unsigned char init_cr00_cr18[SIZE_CR00_CR18];
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| 91 | unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
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| 92 | unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
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| 93 | };
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| 94 |
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| 95 | #ifdef __BIG_ENDIAN
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| 96 | #define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
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| 97 | ((g & 0xe000) >> 13) | \
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| 98 | ((g & 0x1c00) << 3) | \
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| 99 | ((b & 0xf800) >> 3))
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| 100 | #define big_addr 0x800000
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| 101 | #define mmio_addr 0x00800000
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| 102 | #define seqw17() smtc_seqw(0x17, 0x30)
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| 103 | #define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
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| 104 | #define big_swap(p) (((p & 0xff00ff00) >> 8) | ((p & 0x00ff00ff) << 8))
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| 105 | #else
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| 106 | #define pal_rgb(r, g, b, val) val
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| 107 | #define big_addr 0
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| 108 | #define mmio_addr 0x00c00000
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| 109 | #define seqw17() do { } while (0)
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| 110 | #define big_pixel_depth(p, d) do { } while (0)
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| 111 | #define big_swap(p) p
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| 112 | #endif
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