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| 2 | |
| 3 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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| 4 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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| 5 |
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| 6 |
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| 7 |
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| 8 | #include "global.h"
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| 9 |
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| 10 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = {
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| 11 | |
| 12 | DVP1Driving, DFPHigh, DFPLow
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| 13 | |
| 14 | SR65, CR97, CR99
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| 15 |
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| 16 | {DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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| 17 | 0x00},
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| 18 |
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| 19 | {DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,
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| 20 | 0x00},
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| 21 |
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| 22 | {DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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| 23 | 0x00},
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| 24 |
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| 25 | {DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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| 26 | 0x00},
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| 27 |
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| 28 | {DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00,
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| 29 | 0x00},
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| 30 |
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| 31 | {DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00,
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| 32 | 0x00},
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| 33 | };
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| 34 |
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| 35 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = {
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| 36 | |
| 37 | DVP1Driving, DFPHigh, DFPLow
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| 38 | |
| 39 | SR65, CR97, CR99
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| 40 |
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| 41 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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| 42 |
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| 43 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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| 44 |
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| 45 | {DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01},
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| 46 |
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| 47 | {DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03},
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| 48 |
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| 49 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02},
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| 50 |
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| 51 | {DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03},
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| 52 | };
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| 53 |
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| 54 |
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| 55 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = {
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| 56 | |
| 57 | DVP1Driving, DFPHigh, DFPLow
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| 58 | |
| 59 | SR65, CR97, CR99
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| 60 |
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| 61 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 62 |
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| 63 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 64 |
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| 65 | {DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 66 |
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| 67 | {DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 68 |
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| 69 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 70 |
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| 71 | {DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08},
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| 72 | };
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