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| 2 | |
| 3 | * Copyright (C) 2021 Sean Anderson <[email protected]>
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| 4 |
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| 5 |
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| 6 | #ifndef XILINX_TIMER_H
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| 7 | #define XILINX_TIMER_H
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| 8 |
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| 9 | #include <linux/compiler.h>
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| 10 |
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| 11 | #define TCSR0 0x00
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| 12 | #define TLR0 0x04
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| 13 | #define TCR0 0x08
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| 14 | #define TCSR1 0x10
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| 15 | #define TLR1 0x14
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| 16 | #define TCR1 0x18
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| 17 |
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| 18 | #define TCSR_MDT BIT(0)
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| 19 | #define TCSR_UDT BIT(1)
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| 20 | #define TCSR_GENT BIT(2)
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| 21 | #define TCSR_CAPT BIT(3)
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| 22 | #define TCSR_ARHT BIT(4)
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| 23 | #define TCSR_LOAD BIT(5)
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| 24 | #define TCSR_ENIT BIT(6)
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| 25 | #define TCSR_ENT BIT(7)
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| 26 | #define TCSR_TINT BIT(8)
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| 27 | #define TCSR_PWMA BIT(9)
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| 28 | #define TCSR_ENALL BIT(10)
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| 29 | #define TCSR_CASC BIT(11)
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| 30 |
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| 31 | struct clk;
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| 32 | struct device_node;
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| 33 | struct regmap;
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| 34 |
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| 35 | |
| 36 | * struct xilinx_timer_priv - Private data for Xilinx AXI timer drivers
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| 37 | * @map: Regmap of the device, possibly with an offset
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| 38 | * @clk: Parent clock
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| 39 | * @max: Maximum value of the counters
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| 40 |
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| 41 | struct xilinx_timer_priv {
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| 42 | struct regmap *map;
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| 43 | struct clk *clk;
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| 44 | u64 max;
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| 45 | };
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| 46 |
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| 47 | |
| 48 | * xilinx_timer_tlr_cycles() - Calculate the TLR for a period specified
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| 49 | * in clock cycles
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| 50 | * @priv: The timer's private data
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| 51 | * @tcsr: The value of the TCSR register for this counter
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| 52 | * @cycles: The number of cycles in this period
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| 53 | *
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| 54 | * Callers of this function MUST ensure that @cycles is representable as
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| 55 | * a TLR.
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| 56 | *
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| 57 | * Return: The calculated value for TLR
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| 58 |
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| 59 | u32 xilinx_timer_tlr_cycles(struct xilinx_timer_priv *priv, u32 tcsr,
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| 60 | u64 cycles);
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| 61 |
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| 62 | |
| 63 | * xilinx_timer_get_period() - Get the current period of a counter
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| 64 | * @priv: The timer's private data
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| 65 | * @tlr: The value of TLR for this counter
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| 66 | * @tcsr: The value of TCSR for this counter
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| 67 | *
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| 68 | * Return: The period, in ns
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| 69 |
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| 70 | unsigned int xilinx_timer_get_period(struct xilinx_timer_priv *priv,
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| 71 | u32 tlr, u32 tcsr);
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| 72 |
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| 73 | #endif
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