| 1 | |
| 2 | * Copyright © 2008 Keith Packard
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| 3 | *
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| 4 | * Permission to use, copy, modify, distribute, and sell this software and its
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| 5 | * documentation for any purpose is hereby granted without fee, provided that
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| 6 | * the above copyright notice appear in all copies and that both that copyright
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| 7 | * notice and this permission notice appear in supporting documentation, and
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| 8 | * that the name of the copyright holders not be used in advertising or
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| 9 | * publicity pertaining to distribution of the software without specific,
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| 10 | * written prior permission. The copyright holders make no representations
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| 11 | * about the suitability of this software for any purpose. It is provided "as
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| 12 | * is" without express or implied warranty.
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| 13 | *
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| 14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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| 15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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| 16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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| 17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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| 18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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| 19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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| 20 | * OF THIS SOFTWARE.
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| 21 |
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| 22 |
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| 23 | #ifndef _DRM_DP_H_
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| 24 | #define _DRM_DP_H_
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| 25 |
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| 26 | #include <linux/types.h>
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| 27 |
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| 28 | |
| 29 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
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| 30 | * DP and DPCD versions are independent. Differences from 1.0 are not noted,
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| 31 | * 1.0 devices basically don't exist in the wild.
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| 32 | *
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| 33 | * Abbreviations, in chronological order:
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| 34 | *
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| 35 | * eDP: Embedded DisplayPort version 1
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| 36 | * DPI: DisplayPort Interoperability Guideline v1.1a
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| 37 | * 1.2: DisplayPort 1.2
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| 38 | * MST: Multistream Transport - part of DP 1.2a
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| 39 | *
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| 40 | * 1.2 formally includes both eDP and DPI definitions.
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| 41 |
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| 42 |
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| 43 |
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| 44 | #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
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| 45 | #define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
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| 46 | #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
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| 47 | #define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
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| 48 | #define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
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| 49 |
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| 50 | #define DP_MSA_MISC_6_BPC (0 << 5)
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| 51 | #define DP_MSA_MISC_8_BPC (1 << 5)
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| 52 | #define DP_MSA_MISC_10_BPC (2 << 5)
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| 53 | #define DP_MSA_MISC_12_BPC (3 << 5)
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| 54 | #define DP_MSA_MISC_16_BPC (4 << 5)
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| 55 |
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| 56 | #define DP_MSA_MISC_RAW_6_BPC (1 << 5)
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| 57 | #define DP_MSA_MISC_RAW_7_BPC (2 << 5)
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| 58 | #define DP_MSA_MISC_RAW_8_BPC (3 << 5)
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| 59 | #define DP_MSA_MISC_RAW_10_BPC (4 << 5)
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| 60 | #define DP_MSA_MISC_RAW_12_BPC (5 << 5)
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| 61 | #define DP_MSA_MISC_RAW_14_BPC (6 << 5)
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| 62 | #define DP_MSA_MISC_RAW_16_BPC (7 << 5)
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| 63 |
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| 64 | #define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
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| 65 | ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
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| 66 | #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
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| 67 | #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
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| 68 | #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
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| 69 | #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
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| 70 | #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
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| 71 | #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
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| 72 | #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
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| 73 | #define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
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| 74 | #define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
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| 75 | #define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
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| 76 | #define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
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| 77 | #define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
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| 78 | #define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
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| 79 | #define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
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| 80 | #define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
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| 81 | #define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
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| 82 | #define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
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| 83 | #define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
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| 84 |
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| 85 | #define DP_AUX_MAX_PAYLOAD_BYTES 16
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| 86 |
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| 87 | #define DP_AUX_I2C_WRITE 0x0
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| 88 | #define DP_AUX_I2C_READ 0x1
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| 89 | #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
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| 90 | #define DP_AUX_I2C_MOT 0x4
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| 91 | #define DP_AUX_NATIVE_WRITE 0x8
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| 92 | #define DP_AUX_NATIVE_READ 0x9
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| 93 |
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| 94 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
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| 95 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
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| 96 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
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| 97 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
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| 98 |
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| 99 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
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| 100 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
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| 101 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
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| 102 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
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| 103 |
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| 104 |
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| 105 |
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| 106 |
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| 107 | #define DP_DPCD_REV 0x000
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| 108 | # define DP_DPCD_REV_10 0x10
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| 109 | # define DP_DPCD_REV_11 0x11
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| 110 | # define DP_DPCD_REV_12 0x12
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| 111 | # define DP_DPCD_REV_13 0x13
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| 112 | # define DP_DPCD_REV_14 0x14
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| 113 |
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| 114 | #define DP_MAX_LINK_RATE 0x001
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| 115 |
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| 116 | #define DP_MAX_LANE_COUNT 0x002
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| 117 | # define DP_MAX_LANE_COUNT_MASK 0x1f
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| 118 | # define DP_POST_LT_ADJ_REQ_SUPPORTED (1 << 5)
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| 119 | # define DP_TPS3_SUPPORTED (1 << 6)
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| 120 | # define DP_ENHANCED_FRAME_CAP (1 << 7)
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| 121 |
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| 122 | #define DP_MAX_DOWNSPREAD 0x003
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| 123 | # define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
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| 124 | # define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1)
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| 125 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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| 126 | # define DP_TPS4_SUPPORTED (1 << 7)
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| 127 |
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| 128 | #define DP_NORP 0x004
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| 129 |
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| 130 | #define DP_DOWNSTREAMPORT_PRESENT 0x005
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| 131 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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| 132 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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| 133 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
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| 134 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
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| 135 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
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| 136 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
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| 137 | # define DP_FORMAT_CONVERSION (1 << 3)
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| 138 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
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| 139 |
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| 140 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006
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| 141 | # define DP_CAP_ANSI_8B10B (1 << 0)
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| 142 | # define DP_CAP_ANSI_128B132B (1 << 1)
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| 143 |
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| 144 | #define DP_DOWN_STREAM_PORT_COUNT 0x007
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| 145 | # define DP_PORT_COUNT_MASK 0x0f
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| 146 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
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| 147 | # define DP_OUI_SUPPORT (1 << 7)
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| 148 |
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| 149 | #define DP_RECEIVE_PORT_0_CAP_0 0x008
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| 150 | # define DP_LOCAL_EDID_PRESENT (1 << 1)
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| 151 | # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
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| 152 | # define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
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| 153 |
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| 154 | #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
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| 155 |
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| 156 | #define DP_RECEIVE_PORT_1_CAP_0 0x00a
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| 157 | #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
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| 158 |
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| 159 | #define DP_I2C_SPEED_CAP 0x00c
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| 160 | # define DP_I2C_SPEED_1K 0x01
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| 161 | # define DP_I2C_SPEED_5K 0x02
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| 162 | # define DP_I2C_SPEED_10K 0x04
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| 163 | # define DP_I2C_SPEED_100K 0x08
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| 164 | # define DP_I2C_SPEED_400K 0x10
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| 165 | # define DP_I2C_SPEED_1M 0x20
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| 166 |
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| 167 | #define DP_EDP_CONFIGURATION_CAP 0x00d
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| 168 | # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
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| 169 | # define DP_FRAMING_CHANGE_CAP (1 << 1)
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| 170 | # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3)
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| 171 |
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| 172 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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| 173 | # define DP_TRAINING_AUX_RD_MASK 0x7F
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| 174 | # define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)
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| 175 |
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| 176 | #define DP_ADAPTER_CAP 0x00f
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| 177 | # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
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| 178 | # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
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| 179 |
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| 180 | #define DP_SUPPORTED_LINK_RATES 0x010
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| 181 | # define DP_MAX_SUPPORTED_RATES 8
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| 182 |
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| 183 |
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| 184 | #define DP_FAUX_CAP 0x020
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| 185 | # define DP_FAUX_CAP_1 (1 << 0)
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| 186 |
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| 187 | #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020
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| 188 | # define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
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| 189 | # define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
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| 190 | # define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
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| 191 |
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| 192 | #define DP_MSTM_CAP 0x021
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| 193 | # define DP_MST_CAP (1 << 0)
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| 194 | # define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1)
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| 195 |
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| 196 | #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022
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| 197 |
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| 198 |
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| 199 | #define DP_AV_GRANULARITY 0x023
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| 200 | # define DP_AG_FACTOR_MASK (0xf << 0)
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| 201 | # define DP_AG_FACTOR_3MS (0 << 0)
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| 202 | # define DP_AG_FACTOR_2MS (1 << 0)
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| 203 | # define DP_AG_FACTOR_1MS (2 << 0)
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| 204 | # define DP_AG_FACTOR_500US (3 << 0)
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| 205 | # define DP_AG_FACTOR_200US (4 << 0)
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| 206 | # define DP_AG_FACTOR_100US (5 << 0)
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| 207 | # define DP_AG_FACTOR_10US (6 << 0)
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| 208 | # define DP_AG_FACTOR_1US (7 << 0)
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| 209 | # define DP_VG_FACTOR_MASK (0xf << 4)
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| 210 | # define DP_VG_FACTOR_3MS (0 << 4)
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| 211 | # define DP_VG_FACTOR_2MS (1 << 4)
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| 212 | # define DP_VG_FACTOR_1MS (2 << 4)
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| 213 | # define DP_VG_FACTOR_500US (3 << 4)
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| 214 | # define DP_VG_FACTOR_200US (4 << 4)
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| 215 | # define DP_VG_FACTOR_100US (5 << 4)
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| 216 |
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| 217 | #define DP_AUD_DEC_LAT0 0x024
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| 218 | #define DP_AUD_DEC_LAT1 0x025
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| 219 |
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| 220 | #define DP_AUD_PP_LAT0 0x026
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| 221 | #define DP_AUD_PP_LAT1 0x027
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| 222 |
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| 223 | #define DP_VID_INTER_LAT 0x028
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| 224 |
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| 225 | #define DP_VID_PROG_LAT 0x029
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| 226 |
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| 227 | #define DP_REP_LAT 0x02a
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| 228 |
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| 229 | #define DP_AUD_DEL_INS0 0x02b
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| 230 | #define DP_AUD_DEL_INS1 0x02c
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| 231 | #define DP_AUD_DEL_INS2 0x02d
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| 232 |
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| 233 |
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| 234 | #define DP_RECEIVER_ALPM_CAP 0x02e
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| 235 | # define DP_ALPM_CAP (1 << 0)
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| 236 | # define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1)
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| 237 | # define DP_ALPM_AUX_LESS_CAP (1 << 2)
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| 238 |
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| 239 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f
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| 240 | # define DP_AUX_FRAME_SYNC_CAP (1 << 0)
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| 241 |
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| 242 | #define DP_GUID 0x030
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| 243 |
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| 244 | #define DP_DSC_SUPPORT 0x060
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| 245 | # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
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| 246 | # define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1)
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| 247 | # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2)
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| 248 | # define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3)
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| 249 |
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| 250 | #define DP_DSC_REV 0x061
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| 251 | # define DP_DSC_MAJOR_MASK (0xf << 0)
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| 252 | # define DP_DSC_MINOR_MASK (0xf << 4)
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| 253 | # define DP_DSC_MAJOR_SHIFT 0
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| 254 | # define DP_DSC_MINOR_SHIFT 4
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| 255 |
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| 256 | #define DP_DSC_RC_BUF_BLK_SIZE 0x062
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| 257 | # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
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| 258 | # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
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| 259 | # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
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| 260 | # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
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| 261 | # define DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT 3
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| 262 | # define DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK (0x1f << DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT)
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| 263 |
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| 264 | #define DP_DSC_RC_BUF_SIZE 0x063
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| 265 |
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| 266 | #define DP_DSC_SLICE_CAP_1 0x064
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| 267 | # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
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| 268 | # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
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| 269 | # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
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| 270 | # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
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| 271 | # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
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| 272 | # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
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| 273 | # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
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| 274 |
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| 275 | #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
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| 276 | # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
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| 277 | # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
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| 278 | # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
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| 279 | # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
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| 280 | # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
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| 281 | # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
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| 282 | # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
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| 283 | # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
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| 284 | # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
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| 285 | # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
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| 286 |
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| 287 | #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
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| 288 | # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
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| 289 | # define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)
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| 290 |
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| 291 | #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067
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| 292 |
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| 293 | #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068
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| 294 | # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
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| 295 | # define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5)
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| 296 | # define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7)
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| 297 |
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| 298 | #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
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| 299 | # define DP_DSC_RGB (1 << 0)
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| 300 | # define DP_DSC_YCbCr444 (1 << 1)
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| 301 | # define DP_DSC_YCbCr422_Simple (1 << 2)
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| 302 | # define DP_DSC_YCbCr422_Native (1 << 3)
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| 303 | # define DP_DSC_YCbCr420_Native (1 << 4)
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| 304 |
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| 305 | #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
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| 306 | # define DP_DSC_8_BPC (1 << 1)
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| 307 | # define DP_DSC_10_BPC (1 << 2)
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| 308 | # define DP_DSC_12_BPC (1 << 3)
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| 309 |
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| 310 | #define DP_DSC_PEAK_THROUGHPUT 0x06B
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| 311 | # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
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| 312 | # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
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| 313 | # define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
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| 314 | # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
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| 315 | # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
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| 316 | # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
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| 317 | # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
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| 318 | # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
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| 319 | # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
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| 320 | # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
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| 321 | # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
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| 322 | # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
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| 323 | # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
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| 324 | # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
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| 325 | # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
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| 326 | # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
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| 327 | # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
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| 328 | # define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0)
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| 329 | # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
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| 330 | # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
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| 331 | # define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
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| 332 | # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
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| 333 | # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
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| 334 | # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
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| 335 | # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
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| 336 | # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
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| 337 | # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
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| 338 | # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
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| 339 | # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
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| 340 | # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
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| 341 | # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
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| 342 | # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
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| 343 | # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
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| 344 | # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
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| 345 | # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
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| 346 | # define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
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| 347 |
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| 348 | #define DP_DSC_MAX_SLICE_WIDTH 0x06C
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| 349 | #define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
|
| 350 | #define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
|
| 351 |
|
| 352 | #define DP_DSC_SLICE_CAP_2 0x06D
|
| 353 | # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
|
| 354 | # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
|
| 355 | # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
|
| 356 |
|
| 357 | #define DP_DSC_MAX_BPP_DELTA_VERSION_1 0x06E
|
| 358 | # define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
|
| 359 | # define DP_DSC_NATIVE_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
|
| 360 |
|
| 361 | # define DP_DSC_BPP_DELTA_444 16
|
| 362 | # define DP_DSC_BPP_DELTA_420 12
|
| 363 | # define DP_DSC_BPP_DELTA_SHIFT_420 5
|
| 364 |
|
| 365 | #define DP_DSC_BITS_PER_PIXEL_INC 0x06F
|
| 366 | # define DP_DSC_BITS_PER_PIXEL_1_16 0x0
|
| 367 | # define DP_DSC_BITS_PER_PIXEL_1_8 0x1
|
| 368 | # define DP_DSC_BITS_PER_PIXEL_1_4 0x2
|
| 369 | # define DP_DSC_BITS_PER_PIXEL_1_2 0x3
|
| 370 | # define DP_DSC_BITS_PER_PIXEL_1_1 0x4
|
| 371 | # define DP_DSC_BITS_PER_PIXEL_MASK 0x7
|
| 372 | # define DP_DSC_NATIVE_YCbCr422_MAX_BPP_DELTA_MASK 0x78
|
| 373 | # define DP_DSC_BPP_DELTA_NATIVE_SHIFT_422 3
|
| 374 | # define DP_DSC_BPP_DELTA_NATIVE_422 16
|
| 375 |
|
| 376 | #define DP_PSR_SUPPORT 0x070
|
| 377 | # define DP_PSR_IS_SUPPORTED 1
|
| 378 | # define DP_PSR2_IS_SUPPORTED 2
|
| 379 | # define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3
|
| 380 | # define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4
|
| 381 |
|
| 382 | #define DP_PSR_CAPS 0x071
|
| 383 | # define DP_PSR_NO_TRAIN_ON_EXIT 1
|
| 384 | # define DP_PSR_SETUP_TIME_330 (0 << 1)
|
| 385 | # define DP_PSR_SETUP_TIME_275 (1 << 1)
|
| 386 | # define DP_PSR_SETUP_TIME_220 (2 << 1)
|
| 387 | # define DP_PSR_SETUP_TIME_165 (3 << 1)
|
| 388 | # define DP_PSR_SETUP_TIME_110 (4 << 1)
|
| 389 | # define DP_PSR_SETUP_TIME_55 (5 << 1)
|
| 390 | # define DP_PSR_SETUP_TIME_0 (6 << 1)
|
| 391 | # define DP_PSR_SETUP_TIME_MASK (7 << 1)
|
| 392 | # define DP_PSR_SETUP_TIME_SHIFT 1
|
| 393 | # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4)
|
| 394 | # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5)
|
| 395 | # define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)
|
| 396 |
|
| 397 | #define DP_PSR2_SU_X_GRANULARITY 0x072
|
| 398 | #define DP_PSR2_SU_Y_GRANULARITY 0x074
|
| 399 |
|
| 400 | |
| 401 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts
|
| 402 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
|
| 403 | * each port's descriptor is one byte wide. If it was set, each port's is
|
| 404 | * four bytes wide, starting with the one byte from the base info. As of
|
| 405 | * DP interop v1.1a only VGA defines additional detail.
|
| 406 |
|
| 407 |
|
| 408 |
|
| 409 | #define DP_DOWNSTREAM_PORT_0 0x80
|
| 410 | # define DP_DS_PORT_TYPE_MASK (7 << 0)
|
| 411 | # define DP_DS_PORT_TYPE_DP 0
|
| 412 | # define DP_DS_PORT_TYPE_VGA 1
|
| 413 | # define DP_DS_PORT_TYPE_DVI 2
|
| 414 | # define DP_DS_PORT_TYPE_HDMI 3
|
| 415 | # define DP_DS_PORT_TYPE_NON_EDID 4
|
| 416 | # define DP_DS_PORT_TYPE_DP_DUALMODE 5
|
| 417 | # define DP_DS_PORT_TYPE_WIRELESS 6
|
| 418 | # define DP_DS_PORT_HPD (1 << 3)
|
| 419 | # define DP_DS_NON_EDID_MASK (0xf << 4)
|
| 420 | # define DP_DS_NON_EDID_720x480i_60 (1 << 4)
|
| 421 | # define DP_DS_NON_EDID_720x480i_50 (2 << 4)
|
| 422 | # define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
|
| 423 | # define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
|
| 424 | # define DP_DS_NON_EDID_1280x720_60 (5 << 4)
|
| 425 | # define DP_DS_NON_EDID_1280x720_50 (7 << 4)
|
| 426 |
|
| 427 |
|
| 428 |
|
| 429 | # define DP_DS_MAX_BPC_MASK (3 << 0)
|
| 430 | # define DP_DS_8BPC 0
|
| 431 | # define DP_DS_10BPC 1
|
| 432 | # define DP_DS_12BPC 2
|
| 433 | # define DP_DS_16BPC 3
|
| 434 |
|
| 435 | # define DP_PCON_MAX_FRL_BW (7 << 2)
|
| 436 | # define DP_PCON_MAX_0GBPS (0 << 2)
|
| 437 | # define DP_PCON_MAX_9GBPS (1 << 2)
|
| 438 | # define DP_PCON_MAX_18GBPS (2 << 2)
|
| 439 | # define DP_PCON_MAX_24GBPS (3 << 2)
|
| 440 | # define DP_PCON_MAX_32GBPS (4 << 2)
|
| 441 | # define DP_PCON_MAX_40GBPS (5 << 2)
|
| 442 | # define DP_PCON_MAX_48GBPS (6 << 2)
|
| 443 | # define DP_PCON_SOURCE_CTL_MODE (1 << 5)
|
| 444 |
|
| 445 |
|
| 446 | # define DP_DS_DVI_DUAL_LINK (1 << 1)
|
| 447 | # define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
|
| 448 |
|
| 449 | # define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
|
| 450 | # define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
|
| 451 | # define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
|
| 452 | # define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
|
| 453 | # define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
|
| 454 |
|
| 455 | |
| 456 | * VESA DP-to-HDMI PCON Specification adds caps for colorspace
|
| 457 | * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
|
| 458 | * Based on the available support the source can enable
|
| 459 | * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
|
| 460 | * DPCD 3052h.
|
| 461 |
|
| 462 | # define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
|
| 463 | # define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
|
| 464 | # define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
|
| 465 |
|
| 466 | #define DP_MAX_DOWNSTREAM_PORTS 0x10
|
| 467 |
|
| 468 |
|
| 469 | #define DP_FEC_CAPABILITY 0x090
|
| 470 | # define DP_FEC_CAPABLE (1 << 0)
|
| 471 | # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
|
| 472 | # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
|
| 473 | # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
|
| 474 | #define DP_FEC_CAPABILITY_1 0x091
|
| 475 |
|
| 476 |
|
| 477 | #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD
|
| 478 | #define DP_PCON_DSC_ENCODER 0x092
|
| 479 | # define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
|
| 480 | # define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
|
| 481 |
|
| 482 |
|
| 483 | #define DP_PCON_DSC_VERSION 0x093
|
| 484 | # define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
|
| 485 | # define DP_PCON_DSC_MINOR_MASK (0xF << 4)
|
| 486 | # define DP_PCON_DSC_MAJOR_SHIFT 0
|
| 487 | # define DP_PCON_DSC_MINOR_SHIFT 4
|
| 488 |
|
| 489 |
|
| 490 | #define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
|
| 491 | # define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
|
| 492 | # define DP_PCON_DSC_RC_BUF_BLK_1KB 0
|
| 493 | # define DP_PCON_DSC_RC_BUF_BLK_4KB 1
|
| 494 | # define DP_PCON_DSC_RC_BUF_BLK_16KB 2
|
| 495 | # define DP_PCON_DSC_RC_BUF_BLK_64KB 3
|
| 496 |
|
| 497 |
|
| 498 | #define DP_PCON_DSC_RC_BUF_SIZE 0x095
|
| 499 |
|
| 500 |
|
| 501 | #define DP_PCON_DSC_SLICE_CAP_1 0x096
|
| 502 | # define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
|
| 503 | # define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
|
| 504 | # define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
|
| 505 | # define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
|
| 506 | # define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
|
| 507 | # define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
|
| 508 | # define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
|
| 509 |
|
| 510 | #define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
|
| 511 | # define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
|
| 512 | # define DP_PCON_DSC_DEPTH_9_BITS 0
|
| 513 | # define DP_PCON_DSC_DEPTH_10_BITS 1
|
| 514 | # define DP_PCON_DSC_DEPTH_11_BITS 2
|
| 515 | # define DP_PCON_DSC_DEPTH_12_BITS 3
|
| 516 | # define DP_PCON_DSC_DEPTH_13_BITS 4
|
| 517 | # define DP_PCON_DSC_DEPTH_14_BITS 5
|
| 518 | # define DP_PCON_DSC_DEPTH_15_BITS 6
|
| 519 | # define DP_PCON_DSC_DEPTH_16_BITS 7
|
| 520 | # define DP_PCON_DSC_DEPTH_8_BITS 8
|
| 521 |
|
| 522 | #define DP_PCON_DSC_BLOCK_PREDICTION 0x098
|
| 523 | # define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
|
| 524 |
|
| 525 | #define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
|
| 526 | # define DP_PCON_DSC_ENC_RGB (0x1 << 0)
|
| 527 | # define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
|
| 528 | # define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
|
| 529 | # define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
|
| 530 | # define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
|
| 531 |
|
| 532 | #define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
|
| 533 | # define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
|
| 534 | # define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
|
| 535 | # define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
|
| 536 |
|
| 537 | #define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
|
| 538 |
|
| 539 |
|
| 540 | #define DP_PCON_DSC_SLICE_CAP_2 0x09C
|
| 541 | # define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
|
| 542 | # define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
|
| 543 | # define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
|
| 544 |
|
| 545 |
|
| 546 | #define DP_PCON_DSC_BPP_INCR 0x09E
|
| 547 | # define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
|
| 548 | # define DP_PCON_DSC_ONE_16TH_BPP 0
|
| 549 | # define DP_PCON_DSC_ONE_8TH_BPP 1
|
| 550 | # define DP_PCON_DSC_ONE_4TH_BPP 2
|
| 551 | # define DP_PCON_DSC_ONE_HALF_BPP 3
|
| 552 | # define DP_PCON_DSC_ONE_BPP 4
|
| 553 |
|
| 554 |
|
| 555 | #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0
|
| 556 | #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
|
| 557 | #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
|
| 558 |
|
| 559 |
|
| 560 | #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3
|
| 561 |
|
| 562 | #define DP_PANEL_REPLAY_CAP_SUPPORT 0x0b0
|
| 563 | # define DP_PANEL_REPLAY_SUPPORT (1 << 0)
|
| 564 | # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
|
| 565 | # define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2)
|
| 566 |
|
| 567 | #define DP_PANEL_REPLAY_CAP_SIZE 7
|
| 568 |
|
| 569 | #define DP_PANEL_REPLAY_CAP_CAPABILITY 0xb1
|
| 570 | # define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT 1
|
| 571 | # define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK (3 << DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT)
|
| 572 | # define DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED 0x00
|
| 573 | # define DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY 0x01
|
| 574 | # define DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED 0x02
|
| 575 | # define DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED 0x03
|
| 576 | # define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR (1 << 3)
|
| 577 | # define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED (1 << 4)
|
| 578 | # define DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5)
|
| 579 | # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED (1 << 6)
|
| 580 | # define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP (1 << 7)
|
| 581 |
|
| 582 | #define DP_PANEL_REPLAY_CAP_X_GRANULARITY 0xb2
|
| 583 | # define DP_PANEL_REPLAY_FULL_LINE_GRANULARITY 0xffff
|
| 584 |
|
| 585 | #define DP_PANEL_REPLAY_CAP_Y_GRANULARITY 0xb4
|
| 586 |
|
| 587 |
|
| 588 | #define DP_LINK_BW_SET 0x100
|
| 589 | # define DP_LINK_RATE_TABLE 0x00
|
| 590 | # define DP_LINK_BW_1_62 0x06
|
| 591 | # define DP_LINK_BW_2_7 0x0a
|
| 592 | # define DP_LINK_BW_5_4 0x14
|
| 593 | # define DP_LINK_BW_8_1 0x1e
|
| 594 | # define DP_LINK_BW_10 0x01
|
| 595 | # define DP_LINK_BW_13_5 0x04
|
| 596 | # define DP_LINK_BW_20 0x02
|
| 597 |
|
| 598 | #define DP_LANE_COUNT_SET 0x101
|
| 599 | # define DP_LANE_COUNT_MASK 0x0f
|
| 600 | # define DP_POST_LT_ADJ_REQ_GRANTED (1 << 5)
|
| 601 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
|
| 602 |
|
| 603 | #define DP_TRAINING_PATTERN_SET 0x102
|
| 604 | # define DP_TRAINING_PATTERN_DISABLE 0
|
| 605 | # define DP_TRAINING_PATTERN_1 1
|
| 606 | # define DP_TRAINING_PATTERN_2 2
|
| 607 | # define DP_TRAINING_PATTERN_2_CDS 3
|
| 608 | # define DP_TRAINING_PATTERN_3 3
|
| 609 | # define DP_TRAINING_PATTERN_4 7
|
| 610 | # define DP_TRAINING_PATTERN_MASK 0x3
|
| 611 | # define DP_TRAINING_PATTERN_MASK_1_4 0xf
|
| 612 |
|
| 613 |
|
| 614 | # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
|
| 615 | # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
|
| 616 | # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
|
| 617 | # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
|
| 618 | # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
|
| 619 |
|
| 620 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
|
| 621 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
|
| 622 |
|
| 623 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
|
| 624 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
|
| 625 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
|
| 626 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
|
| 627 |
|
| 628 | #define DP_TRAINING_LANE0_SET 0x103
|
| 629 | #define DP_TRAINING_LANE1_SET 0x104
|
| 630 | #define DP_TRAINING_LANE2_SET 0x105
|
| 631 | #define DP_TRAINING_LANE3_SET 0x106
|
| 632 |
|
| 633 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
|
| 634 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
|
| 635 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
|
| 636 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
|
| 637 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
|
| 638 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
|
| 639 | # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
|
| 640 |
|
| 641 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
|
| 642 | # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
|
| 643 | # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
|
| 644 | # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
|
| 645 | # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
|
| 646 |
|
| 647 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
|
| 648 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
|
| 649 |
|
| 650 | # define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0)
|
| 651 |
|
| 652 | #define DP_DOWNSPREAD_CTRL 0x107
|
| 653 | # define DP_SPREAD_AMP_0_5 (1 << 4)
|
| 654 | # define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (1 << 6)
|
| 655 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
|
| 656 |
|
| 657 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
|
| 658 | # define DP_SET_ANSI_8B10B (1 << 0)
|
| 659 | # define DP_SET_ANSI_128B132B (1 << 1)
|
| 660 |
|
| 661 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109
|
| 662 |
|
| 663 |
|
| 664 | #define DP_EDP_CONFIGURATION_SET 0x10a
|
| 665 | # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
|
| 666 | # define DP_FRAMING_CHANGE_ENABLE (1 << 1)
|
| 667 | # define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
|
| 668 |
|
| 669 | #define DP_LINK_QUAL_LANE0_SET 0x10b
|
| 670 | #define DP_LINK_QUAL_LANE1_SET 0x10c
|
| 671 | #define DP_LINK_QUAL_LANE2_SET 0x10d
|
| 672 | #define DP_LINK_QUAL_LANE3_SET 0x10e
|
| 673 | # define DP_LINK_QUAL_PATTERN_DISABLE 0
|
| 674 | # define DP_LINK_QUAL_PATTERN_D10_2 1
|
| 675 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
|
| 676 | # define DP_LINK_QUAL_PATTERN_PRBS7 3
|
| 677 | # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
|
| 678 | # define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
|
| 679 | # define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
|
| 680 | # define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
|
| 681 |
|
| 682 | # define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
|
| 683 | # define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
|
| 684 | # define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
|
| 685 | # define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
|
| 686 | # define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
|
| 687 | # define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
|
| 688 | # define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
|
| 689 | # define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
|
| 690 | # define DP_LINK_QUAL_PATTERN_SQUARE 0x48
|
| 691 | # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49
|
| 692 | # define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a
|
| 693 | # define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b
|
| 694 |
|
| 695 | #define DP_TRAINING_LANE0_1_SET2 0x10f
|
| 696 | #define DP_TRAINING_LANE2_3_SET2 0x110
|
| 697 | # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
|
| 698 | # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
|
| 699 | # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
|
| 700 | # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
|
| 701 |
|
| 702 | #define DP_MSTM_CTRL 0x111
|
| 703 | # define DP_MST_EN (1 << 0)
|
| 704 | # define DP_UP_REQ_EN (1 << 1)
|
| 705 | # define DP_UPSTREAM_IS_SRC (1 << 2)
|
| 706 |
|
| 707 | #define DP_AUDIO_DELAY0 0x112
|
| 708 | #define DP_AUDIO_DELAY1 0x113
|
| 709 | #define DP_AUDIO_DELAY2 0x114
|
| 710 |
|
| 711 | #define DP_LINK_RATE_SET 0x115
|
| 712 | # define DP_LINK_RATE_SET_SHIFT 0
|
| 713 | # define DP_LINK_RATE_SET_MASK (7 << 0)
|
| 714 |
|
| 715 | #define DP_RECEIVER_ALPM_CONFIG 0x116
|
| 716 | # define DP_ALPM_ENABLE (1 << 0)
|
| 717 | # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1)
|
| 718 | # define DP_ALPM_MODE_AUX_LESS (1 << 2)
|
| 719 |
|
| 720 | #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117
|
| 721 | # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
|
| 722 | # define DP_IRQ_HPD_ENABLE (1 << 1)
|
| 723 |
|
| 724 | #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118
|
| 725 | # define DP_PWR_NOT_NEEDED (1 << 0)
|
| 726 |
|
| 727 | #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT 0x119
|
| 728 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED (1 << 0)
|
| 729 |
|
| 730 | #define PANEL_REPLAY_CONFIG3 0x11a
|
| 731 | # define DP_PR_AS_SDP_SETUP_TIME_MASK (3 << 6)
|
| 732 | # define DP_PR_AS_SDP_SETUP_TIME_T1 (0 << 6)
|
| 733 | # define DP_PR_AS_SDP_SETUP_TIME_DYNAMIC (1 << 6)
|
| 734 | # define DP_PR_AS_SDP_SETUP_TIME_T2 (2 << 6)
|
| 735 |
|
| 736 | #define DP_FEC_CONFIGURATION 0x120
|
| 737 | # define DP_FEC_READY (1 << 0)
|
| 738 | # define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
|
| 739 | # define DP_FEC_ERR_COUNT_DIS (0 << 1)
|
| 740 | # define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
|
| 741 | # define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
|
| 742 | # define DP_FEC_BIT_ERROR_COUNT (3 << 1)
|
| 743 | # define DP_FEC_LANE_SELECT_MASK (3 << 4)
|
| 744 | # define DP_FEC_LANE_0_SELECT (0 << 4)
|
| 745 | # define DP_FEC_LANE_1_SELECT (1 << 4)
|
| 746 | # define DP_FEC_LANE_2_SELECT (2 << 4)
|
| 747 | # define DP_FEC_LANE_3_SELECT (3 << 4)
|
| 748 |
|
| 749 | #define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121
|
| 750 | #define DP_SDP_CRC16_128B132B_EN BIT(0)
|
| 751 |
|
| 752 | #define DP_AUX_FRAME_SYNC_VALUE 0x15c
|
| 753 | # define DP_AUX_FRAME_SYNC_VALID (1 << 0)
|
| 754 |
|
| 755 | #define DP_DSC_ENABLE 0x160
|
| 756 | # define DP_DECOMPRESSION_EN (1 << 0)
|
| 757 | # define DP_DSC_PASSTHROUGH_EN (1 << 1)
|
| 758 | #define DP_DSC_CONFIGURATION 0x161
|
| 759 |
|
| 760 | #define DP_PSR_EN_CFG 0x170
|
| 761 | # define DP_PSR_ENABLE BIT(0)
|
| 762 | # define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
|
| 763 | # define DP_PSR_CRC_VERIFICATION BIT(2)
|
| 764 | # define DP_PSR_FRAME_CAPTURE BIT(3)
|
| 765 | # define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4)
|
| 766 | # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5)
|
| 767 | # define DP_PSR_ENABLE_PSR2 BIT(6)
|
| 768 | # define DP_PSR_ENABLE_SU_REGION_ET BIT(7)
|
| 769 |
|
| 770 | #define DP_ADAPTER_CTRL 0x1a0
|
| 771 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
|
| 772 |
|
| 773 | #define DP_BRANCH_DEVICE_CTRL 0x1a1
|
| 774 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
|
| 775 |
|
| 776 | #define PANEL_REPLAY_CONFIG 0x1b0
|
| 777 | # define DP_PANEL_REPLAY_ENABLE (1 << 0)
|
| 778 | # define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1)
|
| 779 | # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3)
|
| 780 | # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4)
|
| 781 | # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5)
|
| 782 | # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6)
|
| 783 | # define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1 << 7)
|
| 784 |
|
| 785 | #define PANEL_REPLAY_CONFIG2 0x1b1
|
| 786 | # define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0)
|
| 787 | # define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1)
|
| 788 | # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2)
|
| 789 | # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3
|
| 790 | # define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3)
|
| 791 | # define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7)
|
| 792 |
|
| 793 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
|
| 794 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
|
| 795 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
|
| 796 |
|
| 797 |
|
| 798 | #define DP_SINK_COUNT 0x200
|
| 799 |
|
| 800 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
|
| 801 | # define DP_SINK_CP_READY (1 << 6)
|
| 802 |
|
| 803 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
|
| 804 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
|
| 805 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1)
|
| 806 | # define DP_CP_IRQ (1 << 2)
|
| 807 | # define DP_MCCS_IRQ (1 << 3)
|
| 808 | # define DP_DOWN_REP_MSG_RDY (1 << 4)
|
| 809 | # define DP_UP_REQ_MSG_RDY (1 << 5)
|
| 810 | # define DP_SINK_SPECIFIC_IRQ (1 << 6)
|
| 811 |
|
| 812 | #define DP_LANE0_1_STATUS 0x202
|
| 813 | #define DP_LANE2_3_STATUS 0x203
|
| 814 | # define DP_LANE_CR_DONE (1 << 0)
|
| 815 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
|
| 816 | # define DP_LANE_SYMBOL_LOCKED (1 << 2)
|
| 817 |
|
| 818 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
|
| 819 | DP_LANE_CHANNEL_EQ_DONE | \
|
| 820 | DP_LANE_SYMBOL_LOCKED)
|
| 821 |
|
| 822 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204
|
| 823 | #define DP_INTERLANE_ALIGN_DONE (1 << 0)
|
| 824 | #define DP_POST_LT_ADJ_REQ_IN_PROGRESS (1 << 1)
|
| 825 | #define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2)
|
| 826 | #define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3)
|
| 827 | #define DP_128B132B_LT_FAILED (1 << 4)
|
| 828 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
|
| 829 | #define DP_LINK_STATUS_UPDATED (1 << 7)
|
| 830 |
|
| 831 | #define DP_SINK_STATUS 0x205
|
| 832 | # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
|
| 833 | # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
|
| 834 | # define DP_STREAM_REGENERATION_STATUS (1 << 2)
|
| 835 | # define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3)
|
| 836 |
|
| 837 | #define DP_ADJUST_REQUEST_LANE0_1 0x206
|
| 838 | #define DP_ADJUST_REQUEST_LANE2_3 0x207
|
| 839 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
|
| 840 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
|
| 841 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
|
| 842 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
|
| 843 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
|
| 844 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
|
| 845 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
|
| 846 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
|
| 847 |
|
| 848 |
|
| 849 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
|
| 850 | # define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
|
| 851 | # define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
|
| 852 | # define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
|
| 853 |
|
| 854 | #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
|
| 855 | # define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
|
| 856 | # define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
|
| 857 | # define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
|
| 858 | # define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
|
| 859 | # define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
|
| 860 | # define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
|
| 861 | # define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
|
| 862 | # define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
|
| 863 |
|
| 864 | #define DP_TEST_REQUEST 0x218
|
| 865 | # define DP_TEST_LINK_TRAINING (1 << 0)
|
| 866 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
|
| 867 | # define DP_TEST_LINK_EDID_READ (1 << 2)
|
| 868 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3)
|
| 869 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4)
|
| 870 | # define DP_TEST_LINK_AUDIO_PATTERN (1 << 5)
|
| 871 | # define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6)
|
| 872 |
|
| 873 | #define DP_TEST_LINK_RATE 0x219
|
| 874 | # define DP_LINK_RATE_162 (0x6)
|
| 875 | # define DP_LINK_RATE_27 (0xa)
|
| 876 |
|
| 877 | #define DP_TEST_LANE_COUNT 0x220
|
| 878 |
|
| 879 | #define DP_TEST_PATTERN 0x221
|
| 880 | # define DP_NO_TEST_PATTERN 0x0
|
| 881 | # define DP_COLOR_RAMP 0x1
|
| 882 | # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
|
| 883 | # define DP_COLOR_SQUARE 0x3
|
| 884 |
|
| 885 | #define DP_TEST_H_TOTAL_HI 0x222
|
| 886 | #define DP_TEST_H_TOTAL_LO 0x223
|
| 887 |
|
| 888 | #define DP_TEST_V_TOTAL_HI 0x224
|
| 889 | #define DP_TEST_V_TOTAL_LO 0x225
|
| 890 |
|
| 891 | #define DP_TEST_H_START_HI 0x226
|
| 892 | #define DP_TEST_H_START_LO 0x227
|
| 893 |
|
| 894 | #define DP_TEST_V_START_HI 0x228
|
| 895 | #define DP_TEST_V_START_LO 0x229
|
| 896 |
|
| 897 | #define DP_TEST_HSYNC_HI 0x22A
|
| 898 | # define DP_TEST_HSYNC_POLARITY (1 << 7)
|
| 899 | # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
|
| 900 | #define DP_TEST_HSYNC_WIDTH_LO 0x22B
|
| 901 |
|
| 902 | #define DP_TEST_VSYNC_HI 0x22C
|
| 903 | # define DP_TEST_VSYNC_POLARITY (1 << 7)
|
| 904 | # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
|
| 905 | #define DP_TEST_VSYNC_WIDTH_LO 0x22D
|
| 906 |
|
| 907 | #define DP_TEST_H_WIDTH_HI 0x22E
|
| 908 | #define DP_TEST_H_WIDTH_LO 0x22F
|
| 909 |
|
| 910 | #define DP_TEST_V_HEIGHT_HI 0x230
|
| 911 | #define DP_TEST_V_HEIGHT_LO 0x231
|
| 912 |
|
| 913 | #define DP_TEST_MISC0 0x232
|
| 914 | # define DP_TEST_SYNC_CLOCK (1 << 0)
|
| 915 | # define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
|
| 916 | # define DP_TEST_COLOR_FORMAT_SHIFT 1
|
| 917 | # define DP_COLOR_FORMAT_RGB (0 << 1)
|
| 918 | # define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
|
| 919 | # define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
|
| 920 | # define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
|
| 921 | # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
|
| 922 | # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
|
| 923 | # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
|
| 924 | # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
|
| 925 | # define DP_TEST_BIT_DEPTH_MASK (7 << 5)
|
| 926 | # define DP_TEST_BIT_DEPTH_SHIFT 5
|
| 927 | # define DP_TEST_BIT_DEPTH_6 (0 << 5)
|
| 928 | # define DP_TEST_BIT_DEPTH_8 (1 << 5)
|
| 929 | # define DP_TEST_BIT_DEPTH_10 (2 << 5)
|
| 930 | # define DP_TEST_BIT_DEPTH_12 (3 << 5)
|
| 931 | # define DP_TEST_BIT_DEPTH_16 (4 << 5)
|
| 932 |
|
| 933 | #define DP_TEST_MISC1 0x233
|
| 934 | # define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
|
| 935 | # define DP_TEST_INTERLACED (1 << 1)
|
| 936 |
|
| 937 | #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
|
| 938 |
|
| 939 | #define DP_TEST_MISC0 0x232
|
| 940 |
|
| 941 | #define DP_TEST_CRC_R_CR 0x240
|
| 942 | #define DP_TEST_CRC_G_Y 0x242
|
| 943 | #define DP_TEST_CRC_B_CB 0x244
|
| 944 |
|
| 945 | #define DP_TEST_SINK_MISC 0x246
|
| 946 | # define DP_TEST_CRC_SUPPORTED (1 << 5)
|
| 947 | # define DP_TEST_COUNT_MASK 0xf
|
| 948 |
|
| 949 | #define DP_PHY_TEST_PATTERN 0x248
|
| 950 | # define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
|
| 951 | # define DP_PHY_TEST_PATTERN_NONE 0x0
|
| 952 | # define DP_PHY_TEST_PATTERN_D10_2 0x1
|
| 953 | # define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
|
| 954 | # define DP_PHY_TEST_PATTERN_PRBS7 0x3
|
| 955 | # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
|
| 956 | # define DP_PHY_TEST_PATTERN_CP2520 0x5
|
| 957 |
|
| 958 | #define DP_PHY_SQUARE_PATTERN 0x249
|
| 959 |
|
| 960 | #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
|
| 961 | #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
|
| 962 | #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
|
| 963 | #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
|
| 964 | #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
|
| 965 | #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
|
| 966 | #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
|
| 967 | #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
|
| 968 | #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
|
| 969 | #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
|
| 970 | #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
|
| 971 |
|
| 972 | #define DP_TEST_RESPONSE 0x260
|
| 973 | # define DP_TEST_ACK (1 << 0)
|
| 974 | # define DP_TEST_NAK (1 << 1)
|
| 975 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
|
| 976 |
|
| 977 | #define DP_TEST_EDID_CHECKSUM 0x261
|
| 978 |
|
| 979 | #define DP_TEST_SINK 0x270
|
| 980 | # define DP_TEST_SINK_START (1 << 0)
|
| 981 | #define DP_TEST_AUDIO_MODE 0x271
|
| 982 | #define DP_TEST_AUDIO_PATTERN_TYPE 0x272
|
| 983 | #define DP_TEST_AUDIO_PERIOD_CH1 0x273
|
| 984 | #define DP_TEST_AUDIO_PERIOD_CH2 0x274
|
| 985 | #define DP_TEST_AUDIO_PERIOD_CH3 0x275
|
| 986 | #define DP_TEST_AUDIO_PERIOD_CH4 0x276
|
| 987 | #define DP_TEST_AUDIO_PERIOD_CH5 0x277
|
| 988 | #define DP_TEST_AUDIO_PERIOD_CH6 0x278
|
| 989 | #define DP_TEST_AUDIO_PERIOD_CH7 0x279
|
| 990 | #define DP_TEST_AUDIO_PERIOD_CH8 0x27A
|
| 991 |
|
| 992 | #define DP_FEC_STATUS 0x280
|
| 993 | # define DP_FEC_DECODE_EN_DETECTED (1 << 0)
|
| 994 | # define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
|
| 995 |
|
| 996 | #define DP_FEC_ERROR_COUNT_LSB 0x0281
|
| 997 |
|
| 998 | #define DP_FEC_ERROR_COUNT_MSB 0x0282
|
| 999 | # define DP_FEC_ERROR_COUNT_MASK 0x7F
|
| 1000 | # define DP_FEC_ERR_COUNT_VALID (1 << 7)
|
| 1001 |
|
| 1002 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0
|
| 1003 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
|
| 1004 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1)
|
| 1005 |
|
| 1006 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1
|
| 1007 |
|
| 1008 |
|
| 1009 |
|
| 1010 | #define DP_SOURCE_OUI 0x300
|
| 1011 |
|
| 1012 |
|
| 1013 | #define DP_SINK_OUI 0x400
|
| 1014 |
|
| 1015 |
|
| 1016 | #define DP_BRANCH_OUI 0x500
|
| 1017 | #define DP_BRANCH_ID 0x503
|
| 1018 | #define DP_BRANCH_REVISION_START 0x509
|
| 1019 | #define DP_BRANCH_HW_REV 0x509
|
| 1020 | #define DP_BRANCH_SW_REV 0x50A
|
| 1021 |
|
| 1022 |
|
| 1023 | #define DP_SET_POWER 0x600
|
| 1024 | # define DP_SET_POWER_D0 0x1
|
| 1025 | # define DP_SET_POWER_D3 0x2
|
| 1026 | # define DP_SET_POWER_MASK 0x3
|
| 1027 | # define DP_SET_POWER_D3_AUX_ON 0x5
|
| 1028 |
|
| 1029 |
|
| 1030 | #define DP_EDP_DPCD_REV 0x700
|
| 1031 | # define DP_EDP_11 0x00
|
| 1032 | # define DP_EDP_12 0x01
|
| 1033 | # define DP_EDP_13 0x02
|
| 1034 | # define DP_EDP_14 0x03
|
| 1035 | # define DP_EDP_14a 0x04
|
| 1036 | # define DP_EDP_14b 0x05
|
| 1037 | # define DP_EDP_15 0x06
|
| 1038 |
|
| 1039 | #define DP_EDP_GENERAL_CAP_1 0x701
|
| 1040 | # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
|
| 1041 | # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
|
| 1042 | # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
|
| 1043 | # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
|
| 1044 | # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
|
| 1045 | # define DP_EDP_FRC_ENABLE_CAP (1 << 5)
|
| 1046 | # define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
|
| 1047 | # define DP_EDP_SET_POWER_CAP (1 << 7)
|
| 1048 |
|
| 1049 | #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
|
| 1050 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
|
| 1051 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
|
| 1052 | # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
|
| 1053 | # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
|
| 1054 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
|
| 1055 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
|
| 1056 | # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
|
| 1057 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
|
| 1058 |
|
| 1059 | #define DP_EDP_GENERAL_CAP_2 0x703
|
| 1060 | # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
|
| 1061 | # define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4)
|
| 1062 | # define DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE (1 << 6)
|
| 1063 |
|
| 1064 | #define DP_EDP_GENERAL_CAP_3 0x704
|
| 1065 | # define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
|
| 1066 | # define DP_EDP_X_REGION_CAP_SHIFT 0
|
| 1067 | # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
|
| 1068 | # define DP_EDP_Y_REGION_CAP_SHIFT 4
|
| 1069 |
|
| 1070 | #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
|
| 1071 | # define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
|
| 1072 | # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
|
| 1073 | # define DP_EDP_FRC_ENABLE (1 << 2)
|
| 1074 | # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
|
| 1075 | # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
|
| 1076 |
|
| 1077 | #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
|
| 1078 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
|
| 1079 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
|
| 1080 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
|
| 1081 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
|
| 1082 | # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
|
| 1083 | # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
|
| 1084 | # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
|
| 1085 | # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
|
| 1086 | # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
|
| 1087 | # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6)
|
| 1088 | # define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7)
|
| 1089 |
|
| 1090 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
|
| 1091 | #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
|
| 1092 |
|
| 1093 | #define DP_EDP_PWMGEN_BIT_COUNT 0x724
|
| 1094 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
|
| 1095 | #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
|
| 1096 | # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
|
| 1097 |
|
| 1098 | #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
|
| 1099 |
|
| 1100 | #define DP_EDP_BACKLIGHT_FREQ_SET 0x728
|
| 1101 | # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
|
| 1102 |
|
| 1103 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
|
| 1104 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
|
| 1105 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
|
| 1106 |
|
| 1107 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
|
| 1108 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
|
| 1109 | #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
|
| 1110 |
|
| 1111 | #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
|
| 1112 | #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
|
| 1113 | #define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734
|
| 1114 |
|
| 1115 | #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740
|
| 1116 | #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741
|
| 1117 |
|
| 1118 | #define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4
|
| 1119 | # define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
|
| 1120 | # define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
|
| 1121 | # define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
|
| 1122 |
|
| 1123 |
|
| 1124 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000
|
| 1125 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200
|
| 1126 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400
|
| 1127 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600
|
| 1128 |
|
| 1129 |
|
| 1130 | #define DP_SINK_COUNT_ESI 0x2002
|
| 1131 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003
|
| 1132 |
|
| 1133 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004
|
| 1134 | # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
|
| 1135 | # define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
|
| 1136 | # define DP_CEC_IRQ (1 << 2)
|
| 1137 |
|
| 1138 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005
|
| 1139 | # define RX_CAP_CHANGED (1 << 0)
|
| 1140 | # define LINK_STATUS_CHANGED (1 << 1)
|
| 1141 | # define STREAM_STATUS_CHANGED (1 << 2)
|
| 1142 | # define HDMI_LINK_STATUS_CHANGED (1 << 3)
|
| 1143 | # define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
|
| 1144 | # define DP_TUNNELING_IRQ (1 << 5)
|
| 1145 |
|
| 1146 | #define DP_PSR_ERROR_STATUS 0x2006
|
| 1147 | # define DP_PSR_LINK_CRC_ERROR (1 << 0)
|
| 1148 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
|
| 1149 | # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
|
| 1150 |
|
| 1151 | #define DP_PSR_ESI 0x2007
|
| 1152 | # define DP_PSR_CAPS_CHANGE (1 << 0)
|
| 1153 |
|
| 1154 | #define DP_PSR_STATUS 0x2008
|
| 1155 | # define DP_PSR_SINK_INACTIVE 0
|
| 1156 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
|
| 1157 | # define DP_PSR_SINK_ACTIVE_RFB 2
|
| 1158 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
|
| 1159 | # define DP_PSR_SINK_ACTIVE_RESYNC 4
|
| 1160 | # define DP_PSR_SINK_INTERNAL_ERROR 7
|
| 1161 | # define DP_PSR_SINK_STATE_MASK 0x07
|
| 1162 |
|
| 1163 | #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009
|
| 1164 | # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
|
| 1165 | # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
|
| 1166 | # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
|
| 1167 | # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
|
| 1168 |
|
| 1169 | #define DP_LAST_RECEIVED_PSR_SDP 0x200a
|
| 1170 | # define DP_PSR_STATE_BIT (1 << 0)
|
| 1171 | # define DP_UPDATE_RFB_BIT (1 << 1)
|
| 1172 | # define DP_CRC_VALID_BIT (1 << 2)
|
| 1173 | # define DP_SU_VALID (1 << 3)
|
| 1174 | # define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4)
|
| 1175 | # define DP_LAST_SCAN_LINE_SU_REGION (1 << 5)
|
| 1176 | # define DP_Y_COORDINATE_VALID (1 << 6)
|
| 1177 |
|
| 1178 | #define DP_RECEIVER_ALPM_STATUS 0x200b
|
| 1179 | # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
|
| 1180 |
|
| 1181 | #define DP_LANE0_1_STATUS_ESI 0x200c
|
| 1182 | #define DP_LANE2_3_STATUS_ESI 0x200d
|
| 1183 | #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e
|
| 1184 | #define DP_SINK_STATUS_ESI 0x200f
|
| 1185 |
|
| 1186 | #define DP_PANEL_REPLAY_ERROR_STATUS 0x2020
|
| 1187 | # define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0)
|
| 1188 | # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1)
|
| 1189 | # define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
|
| 1190 |
|
| 1191 | #define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022
|
| 1192 | # define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)
|
| 1193 | # define DP_SINK_FRAME_LOCKED_SHIFT 3
|
| 1194 | # define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
|
| 1195 | # define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5
|
| 1196 | # define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5)
|
| 1197 |
|
| 1198 |
|
| 1199 | #define DP_DP13_DPCD_REV 0x2200
|
| 1200 |
|
| 1201 | #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210
|
| 1202 | # define DP_GTC_CAP (1 << 0)
|
| 1203 | # define DP_SST_SPLIT_SDP_CAP (1 << 1)
|
| 1204 | # define DP_AV_SYNC_CAP (1 << 2)
|
| 1205 | # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3)
|
| 1206 | # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4)
|
| 1207 | # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5)
|
| 1208 | # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6)
|
| 1209 | # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7)
|
| 1210 |
|
| 1211 | #define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST 0x2211
|
| 1212 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_MASK 0xff
|
| 1213 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS 0x00
|
| 1214 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS 0x01
|
| 1215 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS 0x02
|
| 1216 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS 0x03
|
| 1217 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS 0x04
|
| 1218 | # define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS 0x05
|
| 1219 |
|
| 1220 | #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214
|
| 1221 | # define DP_ADAPTIVE_SYNC_SDP_SUPPORTED BIT(0)
|
| 1222 | # define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED BIT(1)
|
| 1223 | # define DP_AS_SDP_FAVT_PAYLOAD_FIELDS_PARSING_SUPPORTED BIT(2)
|
| 1224 | # define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED BIT(4)
|
| 1225 |
|
| 1226 | #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215
|
| 1227 | # define DP_UHBR10 (1 << 0)
|
| 1228 | # define DP_UHBR20 (1 << 1)
|
| 1229 | # define DP_UHBR13_5 (1 << 2)
|
| 1230 |
|
| 1231 | #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216
|
| 1232 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
|
| 1233 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
|
| 1234 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
|
| 1235 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
|
| 1236 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
|
| 1237 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
|
| 1238 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
|
| 1239 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
|
| 1240 | # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
|
| 1241 |
|
| 1242 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
|
| 1243 | #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
|
| 1244 |
|
| 1245 |
|
| 1246 | #define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260
|
| 1247 | # define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
|
| 1248 | # define DP_DSC_DECODER_COUNT_SHIFT 5
|
| 1249 | #define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270
|
| 1250 | # define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
|
| 1251 | # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
|
| 1252 | # define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
|
| 1253 |
|
| 1254 |
|
| 1255 |
|
| 1256 | #define DP_CEC_TUNNELING_CAPABILITY 0x3000
|
| 1257 | # define DP_CEC_TUNNELING_CAPABLE (1 << 0)
|
| 1258 | # define DP_CEC_SNOOPING_CAPABLE (1 << 1)
|
| 1259 | # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
|
| 1260 |
|
| 1261 | #define DP_CEC_TUNNELING_CONTROL 0x3001
|
| 1262 | # define DP_CEC_TUNNELING_ENABLE (1 << 0)
|
| 1263 | # define DP_CEC_SNOOPING_ENABLE (1 << 1)
|
| 1264 |
|
| 1265 | #define DP_CEC_RX_MESSAGE_INFO 0x3002
|
| 1266 | # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
|
| 1267 | # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
|
| 1268 | # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
|
| 1269 | # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
|
| 1270 | # define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
|
| 1271 | # define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
|
| 1272 |
|
| 1273 | #define DP_CEC_TX_MESSAGE_INFO 0x3003
|
| 1274 | # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
|
| 1275 | # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
|
| 1276 | # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
|
| 1277 | # define DP_CEC_TX_RETRY_COUNT_SHIFT 4
|
| 1278 | # define DP_CEC_TX_MESSAGE_SEND (1 << 7)
|
| 1279 |
|
| 1280 | #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
|
| 1281 | # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
|
| 1282 | # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
|
| 1283 | # define DP_CEC_TX_MESSAGE_SENT (1 << 4)
|
| 1284 | # define DP_CEC_TX_LINE_ERROR (1 << 5)
|
| 1285 | # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
|
| 1286 | # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
|
| 1287 |
|
| 1288 | #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E
|
| 1289 | # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
|
| 1290 | # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
|
| 1291 | # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
|
| 1292 | # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
|
| 1293 | # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
|
| 1294 | # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
|
| 1295 | # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
|
| 1296 | # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
|
| 1297 | #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F
|
| 1298 | # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
|
| 1299 | # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
|
| 1300 | # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
|
| 1301 | # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
|
| 1302 | # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
|
| 1303 | # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
|
| 1304 | # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
|
| 1305 | # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
|
| 1306 |
|
| 1307 | #define DP_CEC_RX_MESSAGE_BUFFER 0x3010
|
| 1308 | #define DP_CEC_TX_MESSAGE_BUFFER 0x3020
|
| 1309 | #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
|
| 1310 |
|
| 1311 |
|
| 1312 | #define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
|
| 1313 | # define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
|
| 1314 | # define DP_PCON_ENABLE_MAX_BW_0GBPS 0
|
| 1315 | # define DP_PCON_ENABLE_MAX_BW_9GBPS 1
|
| 1316 | # define DP_PCON_ENABLE_MAX_BW_18GBPS 2
|
| 1317 | # define DP_PCON_ENABLE_MAX_BW_24GBPS 3
|
| 1318 | # define DP_PCON_ENABLE_MAX_BW_32GBPS 4
|
| 1319 | # define DP_PCON_ENABLE_MAX_BW_40GBPS 5
|
| 1320 | # define DP_PCON_ENABLE_MAX_BW_48GBPS 6
|
| 1321 | # define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
|
| 1322 | # define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
|
| 1323 | # define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
|
| 1324 | # define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
|
| 1325 | # define DP_PCON_ENABLE_HPD_READY (1 << 6)
|
| 1326 | # define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
|
| 1327 |
|
| 1328 |
|
| 1329 | #define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
|
| 1330 | # define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
|
| 1331 | # define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
|
| 1332 | # define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
|
| 1333 | # define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
|
| 1334 | # define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
|
| 1335 | # define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
|
| 1336 | # define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
|
| 1337 | # define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
|
| 1338 | # define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
|
| 1339 |
|
| 1340 |
|
| 1341 | #define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
|
| 1342 | # define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
|
| 1343 | # define DP_PCON_FRL_READY (1 << 1)
|
| 1344 |
|
| 1345 |
|
| 1346 | #define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
|
| 1347 | # define DP_PCON_HDMI_LINK_MODE (1 << 0)
|
| 1348 | # define DP_PCON_HDMI_MODE_TMDS 0
|
| 1349 | # define DP_PCON_HDMI_MODE_FRL 1
|
| 1350 | # define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
|
| 1351 | # define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
|
| 1352 | # define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
|
| 1353 | # define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
|
| 1354 | # define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
|
| 1355 | # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
|
| 1356 | # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
|
| 1357 |
|
| 1358 | #define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050
|
| 1359 | # define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0)
|
| 1360 | #define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051
|
| 1361 | # define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0)
|
| 1362 | # define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1)
|
| 1363 | # define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2)
|
| 1364 | # define DP_HDMI_FORCE_SCRAMBLING (1 << 3)
|
| 1365 | #define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052
|
| 1366 | # define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0)
|
| 1367 | # define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
|
| 1368 | # define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
|
| 1369 | # define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
|
| 1370 | # define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
|
| 1371 | # define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
|
| 1372 | # define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
|
| 1373 | # define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
|
| 1374 | # define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
|
| 1375 | # define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
|
| 1376 |
|
| 1377 |
|
| 1378 | #define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
|
| 1379 | #define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
|
| 1380 | #define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
|
| 1381 | #define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
|
| 1382 | # define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
|
| 1383 | # define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
|
| 1384 | # define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
|
| 1385 | # define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
|
| 1386 |
|
| 1387 | |
| 1388 | * Valid Offsets to be added to Base : 0-127
|
| 1389 |
|
| 1390 | #define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
|
| 1391 |
|
| 1392 | |
| 1393 | * Offset-0 8LSBs of the Slice height.
|
| 1394 | * Offset-1 8MSBs of the Slice height.
|
| 1395 |
|
| 1396 | #define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
|
| 1397 |
|
| 1398 | |
| 1399 | * Offset-0 8LSBs of the Slice width.
|
| 1400 | * Offset-1 8MSBs of the Slice width.
|
| 1401 |
|
| 1402 | #define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
|
| 1403 |
|
| 1404 | |
| 1405 | * Offset-0 8LSBs of the bits_per_pixel.
|
| 1406 | * Offset-1 2MSBs of the bits_per_pixel.
|
| 1407 |
|
| 1408 | #define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
|
| 1409 |
|
| 1410 |
|
| 1411 | #define DP_AUX_HDCP_BKSV 0x68000
|
| 1412 | #define DP_AUX_HDCP_RI_PRIME 0x68005
|
| 1413 | #define DP_AUX_HDCP_AKSV 0x68007
|
| 1414 | #define DP_AUX_HDCP_AN 0x6800C
|
| 1415 | #define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
|
| 1416 | #define DP_AUX_HDCP_BCAPS 0x68028
|
| 1417 | # define DP_BCAPS_REPEATER_PRESENT BIT(1)
|
| 1418 | # define DP_BCAPS_HDCP_CAPABLE BIT(0)
|
| 1419 | #define DP_AUX_HDCP_BSTATUS 0x68029
|
| 1420 | # define DP_BSTATUS_REAUTH_REQ BIT(3)
|
| 1421 | # define DP_BSTATUS_LINK_FAILURE BIT(2)
|
| 1422 | # define DP_BSTATUS_R0_PRIME_READY BIT(1)
|
| 1423 | # define DP_BSTATUS_READY BIT(0)
|
| 1424 | #define DP_AUX_HDCP_BINFO 0x6802A
|
| 1425 | #define DP_AUX_HDCP_KSV_FIFO 0x6802C
|
| 1426 | #define DP_AUX_HDCP_AINFO 0x6803B
|
| 1427 |
|
| 1428 |
|
| 1429 | #define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
|
| 1430 | #define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
|
| 1431 | #define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
|
| 1432 | #define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
|
| 1433 | #define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
|
| 1434 | #define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
|
| 1435 | #define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
|
| 1436 | #define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
|
| 1437 | #define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
|
| 1438 | #define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
|
| 1439 | #define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
|
| 1440 | #define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
|
| 1441 | #define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
|
| 1442 | #define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
|
| 1443 | #define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
|
| 1444 | #define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
|
| 1445 | #define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
|
| 1446 | #define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
|
| 1447 | #define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
|
| 1448 | #define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
|
| 1449 | #define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
|
| 1450 | #define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
|
| 1451 | #define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
|
| 1452 | #define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
|
| 1453 | #define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
|
| 1454 | #define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
|
| 1455 |
|
| 1456 |
|
| 1457 | #define DP_TUNNELING_OUI 0xe0000
|
| 1458 | #define DP_TUNNELING_OUI_BYTES 3
|
| 1459 |
|
| 1460 | #define DP_TUNNELING_DEV_ID 0xe0003
|
| 1461 | #define DP_TUNNELING_DEV_ID_BYTES 6
|
| 1462 |
|
| 1463 | #define DP_TUNNELING_HW_REV 0xe0009
|
| 1464 | #define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4
|
| 1465 | #define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
|
| 1466 | #define DP_TUNNELING_HW_REV_MINOR_SHIFT 0
|
| 1467 | #define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
|
| 1468 |
|
| 1469 | #define DP_TUNNELING_SW_REV_MAJOR 0xe000a
|
| 1470 | #define DP_TUNNELING_SW_REV_MINOR 0xe000b
|
| 1471 |
|
| 1472 | #define DP_TUNNELING_CAPABILITIES 0xe000d
|
| 1473 | #define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
|
| 1474 | #define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6)
|
| 1475 | #define DP_TUNNELING_SUPPORT (1 << 0)
|
| 1476 |
|
| 1477 | #define DP_IN_ADAPTER_INFO 0xe000e
|
| 1478 | #define DP_IN_ADAPTER_NUMBER_BITS 7
|
| 1479 | #define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)
|
| 1480 |
|
| 1481 | #define DP_USB4_DRIVER_ID 0xe000f
|
| 1482 | #define DP_USB4_DRIVER_ID_BITS 4
|
| 1483 | #define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1)
|
| 1484 |
|
| 1485 | #define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020
|
| 1486 | #define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
|
| 1487 |
|
| 1488 | #define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021
|
| 1489 | #define DP_GROUP_ID_BITS 3
|
| 1490 | #define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1)
|
| 1491 |
|
| 1492 | #define DP_BW_GRANULARITY 0xe0022
|
| 1493 | #define DP_BW_GRANULARITY_MASK 0x3
|
| 1494 |
|
| 1495 | #define DP_ESTIMATED_BW 0xe0023
|
| 1496 | #define DP_ALLOCATED_BW 0xe0024
|
| 1497 |
|
| 1498 | #define DP_TUNNELING_STATUS 0xe0025
|
| 1499 | #define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3)
|
| 1500 | #define DP_ESTIMATED_BW_CHANGED (1 << 2)
|
| 1501 | #define DP_BW_REQUEST_SUCCEEDED (1 << 1)
|
| 1502 | #define DP_BW_REQUEST_FAILED (1 << 0)
|
| 1503 |
|
| 1504 | #define DP_TUNNELING_MAX_LINK_RATE 0xe0028
|
| 1505 |
|
| 1506 | #define DP_TUNNELING_MAX_LANE_COUNT 0xe0029
|
| 1507 | #define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f
|
| 1508 |
|
| 1509 | #define DP_TUNNELING_MAIN_LINK_CHANNEL_CODING 0xe002b
|
| 1510 | #define DP_128B132B_DP_SUPPORTED (1 << 0)
|
| 1511 |
|
| 1512 | #define DP_TUNNELING_128B132B_LINK_RATE 0xe002c
|
| 1513 | #define DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT (1 << 2)
|
| 1514 | #define DP_TUNNELING_20GBPS_PER_LANE_SUPPORT (1 << 1)
|
| 1515 | #define DP_TUNNELING_10GBPS_PER_LANE_SUPPORT (1 << 0)
|
| 1516 | #define DP_TUNNELING_128B132B_LINK_RATE_MASK (DP_TUNNELING_10GBPS_PER_LANE_SUPPORT | \
|
| 1517 | DP_TUNNELING_13_5GBPS_PER_LANE_SUPPORT | \
|
| 1518 | DP_TUNNELING_20GBPS_PER_LANE_SUPPORT)
|
| 1519 | #define DP_TUNNELING_128B132B_LL_LANE0_MAPPING_SUPPORT (1 << 7)
|
| 1520 |
|
| 1521 | #define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030
|
| 1522 | #define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7)
|
| 1523 | #define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6)
|
| 1524 |
|
| 1525 | #define DP_REQUEST_BW 0xe0031
|
| 1526 | #define MAX_DP_REQUEST_BW 255
|
| 1527 |
|
| 1528 |
|
| 1529 | #define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
|
| 1530 | #define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
|
| 1531 | #define DP_PHY_REPEATER_CNT 0xf0002
|
| 1532 | #define DP_PHY_REPEATER_MODE 0xf0003
|
| 1533 | #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
|
| 1534 | #define DP_Repeater_FEC_CAPABILITY 0xf0004
|
| 1535 | #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
|
| 1536 | # define DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK 0x7f
|
| 1537 | # define DP_EXTENDED_WAKE_TIMEOUT_GRANT (1 << 7)
|
| 1538 | #define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006
|
| 1539 | # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
|
| 1540 |
|
| 1541 | #define DP_PHY_REPEATER_128B132B_RATES 0xf0007
|
| 1542 | #define DP_PHY_REPEATER_EQ_DONE 0xf0008
|
| 1543 |
|
| 1544 | enum drm_dp_phy {
|
| 1545 | DP_PHY_DPRX,
|
| 1546 |
|
| 1547 | DP_PHY_LTTPR1,
|
| 1548 | DP_PHY_LTTPR2,
|
| 1549 | DP_PHY_LTTPR3,
|
| 1550 | DP_PHY_LTTPR4,
|
| 1551 | DP_PHY_LTTPR5,
|
| 1552 | DP_PHY_LTTPR6,
|
| 1553 | DP_PHY_LTTPR7,
|
| 1554 | DP_PHY_LTTPR8,
|
| 1555 |
|
| 1556 | DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
|
| 1557 | };
|
| 1558 |
|
| 1559 | #define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
|
| 1560 |
|
| 1561 | #define __DP_LTTPR1_BASE 0xf0010
|
| 1562 | #define __DP_LTTPR2_BASE 0xf0060
|
| 1563 | #define DP_LTTPR_BASE(dp_phy) \
|
| 1564 | (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
|
| 1565 | ((dp_phy) - DP_PHY_LTTPR1))
|
| 1566 |
|
| 1567 | #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
|
| 1568 | (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
|
| 1569 |
|
| 1570 | #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
|
| 1571 | #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
|
| 1572 | DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
|
| 1573 |
|
| 1574 | #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
|
| 1575 | #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
|
| 1576 | DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
|
| 1577 |
|
| 1578 | #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
|
| 1579 | #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
|
| 1580 | #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
|
| 1581 | #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
|
| 1582 | #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
|
| 1583 | DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
|
| 1584 |
|
| 1585 | #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
|
| 1586 | # define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
|
| 1587 | # define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
|
| 1588 |
|
| 1589 | #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022
|
| 1590 | #define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
|
| 1591 | DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
|
| 1592 |
|
| 1593 |
|
| 1594 | #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
|
| 1595 | #define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
|
| 1596 | DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
|
| 1597 |
|
| 1598 | #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
|
| 1599 |
|
| 1600 | #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
|
| 1601 | #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
|
| 1602 | #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
|
| 1603 | #define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
|
| 1604 | #define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
|
| 1605 | #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
|
| 1606 | #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
|
| 1607 |
|
| 1608 | #define DP_OUI_PHY_REPEATER1 0xf003d
|
| 1609 | #define DP_OUI_PHY_REPEATER(dp_phy) \
|
| 1610 | DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1)
|
| 1611 |
|
| 1612 | #define __DP_FEC1_BASE 0xf0290
|
| 1613 | #define __DP_FEC2_BASE 0xf0298
|
| 1614 | #define DP_FEC_BASE(dp_phy) \
|
| 1615 | (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
|
| 1616 | ((dp_phy) - DP_PHY_LTTPR1)))
|
| 1617 |
|
| 1618 | #define DP_FEC_REG(dp_phy, fec1_reg) \
|
| 1619 | (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
|
| 1620 |
|
| 1621 | #define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
|
| 1622 | #define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
|
| 1623 | DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
|
| 1624 |
|
| 1625 | #define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291
|
| 1626 | #define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294
|
| 1627 |
|
| 1628 | #define DP_LTTPR_MAX_ADD 0xf02ff
|
| 1629 |
|
| 1630 | #define DP_DPCD_MAX_ADD 0xfffff
|
| 1631 |
|
| 1632 |
|
| 1633 | #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55
|
| 1634 | #define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa
|
| 1635 |
|
| 1636 |
|
| 1637 | #define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
|
| 1638 | #define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
|
| 1639 | #define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
|
| 1640 | #define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
|
| 1641 | #define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
|
| 1642 | #define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
|
| 1643 | DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
|
| 1644 | #define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
|
| 1645 | #define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
|
| 1646 | #define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
|
| 1647 | #define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
|
| 1648 | #define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
|
| 1649 | #define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
|
| 1650 | #define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
|
| 1651 |
|
| 1652 | #define HDCP_2_2_DP_RXSTATUS_LEN 1
|
| 1653 | #define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
|
| 1654 | #define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
|
| 1655 | #define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
|
| 1656 | #define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
|
| 1657 | #define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
|
| 1658 |
|
| 1659 |
|
| 1660 |
|
| 1661 | #define DP_PEER_DEVICE_NONE 0x0
|
| 1662 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
|
| 1663 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2
|
| 1664 | #define DP_PEER_DEVICE_SST_SINK 0x3
|
| 1665 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
|
| 1666 |
|
| 1667 |
|
| 1668 | #define DP_GET_MSG_TRANSACTION_VERSION 0x00
|
| 1669 | #define DP_LINK_ADDRESS 0x01
|
| 1670 | #define DP_CONNECTION_STATUS_NOTIFY 0x02
|
| 1671 | #define DP_ENUM_PATH_RESOURCES 0x10
|
| 1672 | #define DP_ALLOCATE_PAYLOAD 0x11
|
| 1673 | #define DP_QUERY_PAYLOAD 0x12
|
| 1674 | #define DP_RESOURCE_STATUS_NOTIFY 0x13
|
| 1675 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
|
| 1676 | #define DP_REMOTE_DPCD_READ 0x20
|
| 1677 | #define DP_REMOTE_DPCD_WRITE 0x21
|
| 1678 | #define DP_REMOTE_I2C_READ 0x22
|
| 1679 | #define DP_REMOTE_I2C_WRITE 0x23
|
| 1680 | #define DP_POWER_UP_PHY 0x24
|
| 1681 | #define DP_POWER_DOWN_PHY 0x25
|
| 1682 | #define DP_SINK_EVENT_NOTIFY 0x30
|
| 1683 | #define DP_QUERY_STREAM_ENC_STATUS 0x38
|
| 1684 | #define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
|
| 1685 | #define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
|
| 1686 | #define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
|
| 1687 |
|
| 1688 |
|
| 1689 | #define DP_SIDEBAND_REPLY_ACK 0x00
|
| 1690 | #define DP_SIDEBAND_REPLY_NAK 0x01
|
| 1691 |
|
| 1692 |
|
| 1693 | #define DP_NAK_WRITE_FAILURE 0x01
|
| 1694 | #define DP_NAK_INVALID_READ 0x02
|
| 1695 | #define DP_NAK_CRC_FAILURE 0x03
|
| 1696 | #define DP_NAK_BAD_PARAM 0x04
|
| 1697 | #define DP_NAK_DEFER 0x05
|
| 1698 | #define DP_NAK_LINK_FAILURE 0x06
|
| 1699 | #define DP_NAK_NO_RESOURCES 0x07
|
| 1700 | #define DP_NAK_DPCD_FAIL 0x08
|
| 1701 | #define DP_NAK_I2C_NAK 0x09
|
| 1702 | #define DP_NAK_ALLOCATE_FAIL 0x0a
|
| 1703 |
|
| 1704 | #define MODE_I2C_START 1
|
| 1705 | #define MODE_I2C_WRITE 2
|
| 1706 | #define MODE_I2C_READ 4
|
| 1707 | #define MODE_I2C_STOP 8
|
| 1708 |
|
| 1709 |
|
| 1710 | #define DP_MST_PHYSICAL_PORT_0 0
|
| 1711 | #define DP_MST_LOGICAL_PORT_0 8
|
| 1712 |
|
| 1713 | #define DP_LINK_CONSTANT_N_VALUE 0x8000
|
| 1714 | #define DP_LINK_STATUS_SIZE 6
|
| 1715 |
|
| 1716 | #define DP_BRANCH_OUI_HEADER_SIZE 0xc
|
| 1717 | #define DP_RECEIVER_CAP_SIZE 0xf
|
| 1718 | #define DP_DSC_RECEIVER_CAP_SIZE 0x10
|
| 1719 | #define DP_DSC_BRANCH_CAP_SIZE 3
|
| 1720 | #define EDP_PSR_RECEIVER_CAP_SIZE 2
|
| 1721 | #define EDP_DISPLAY_CTL_CAP_SIZE 5
|
| 1722 | #define DP_LTTPR_COMMON_CAP_SIZE 8
|
| 1723 | #define DP_LTTPR_PHY_CAP_SIZE 3
|
| 1724 |
|
| 1725 | #define DP_SDP_AUDIO_TIMESTAMP 0x01
|
| 1726 | #define DP_SDP_AUDIO_STREAM 0x02
|
| 1727 | #define DP_SDP_EXTENSION 0x04
|
| 1728 | #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05
|
| 1729 | #define DP_SDP_ISRC 0x06
|
| 1730 | #define DP_SDP_VSC 0x07
|
| 1731 | #define DP_SDP_ADAPTIVE_SYNC 0x22
|
| 1732 | #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i))
|
| 1733 | #define DP_SDP_PPS 0x10
|
| 1734 | #define DP_SDP_VSC_EXT_VESA 0x20
|
| 1735 | #define DP_SDP_VSC_EXT_CEA 0x21
|
| 1736 |
|
| 1737 |
|
| 1738 |
|
| 1739 | #define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
|
| 1740 |
|
| 1741 | |
| 1742 | * struct dp_sdp_header - DP secondary data packet header
|
| 1743 | * @HB0: Secondary Data Packet ID
|
| 1744 | * @HB1: Secondary Data Packet Type
|
| 1745 | * @HB2: Secondary Data Packet Specific header, Byte 0
|
| 1746 | * @HB3: Secondary Data packet Specific header, Byte 1
|
| 1747 |
|
| 1748 | struct dp_sdp_header {
|
| 1749 | u8 HB0;
|
| 1750 | u8 HB1;
|
| 1751 | u8 HB2;
|
| 1752 | u8 HB3;
|
| 1753 | } __packed;
|
| 1754 |
|
| 1755 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F
|
| 1756 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
|
| 1757 | #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
|
| 1758 |
|
| 1759 | |
| 1760 | * struct dp_sdp - DP secondary data packet
|
| 1761 | * @sdp_header: DP secondary data packet header
|
| 1762 | * @db: DP secondaray data packet data blocks
|
| 1763 | * VSC SDP Payload for PSR
|
| 1764 | * db[0]: Stereo Interface
|
| 1765 | * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
|
| 1766 | * db[2]: CRC value bits 7:0 of the R or Cr component
|
| 1767 | * db[3]: CRC value bits 15:8 of the R or Cr component
|
| 1768 | * db[4]: CRC value bits 7:0 of the G or Y component
|
| 1769 | * db[5]: CRC value bits 15:8 of the G or Y component
|
| 1770 | * db[6]: CRC value bits 7:0 of the B or Cb component
|
| 1771 | * db[7]: CRC value bits 15:8 of the B or Cb component
|
| 1772 | * db[8] - db[31]: Reserved
|
| 1773 | * VSC SDP Payload for Pixel Encoding/Colorimetry Format
|
| 1774 | * db[0] - db[15]: Reserved
|
| 1775 | * db[16]: Pixel Encoding and Colorimetry Formats
|
| 1776 | * db[17]: Dynamic Range and Component Bit Depth
|
| 1777 | * db[18]: Content Type
|
| 1778 | * db[19] - db[31]: Reserved
|
| 1779 |
|
| 1780 | struct dp_sdp {
|
| 1781 | struct dp_sdp_header sdp_header;
|
| 1782 | u8 db[32];
|
| 1783 | } __packed;
|
| 1784 |
|
| 1785 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
|
| 1786 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1)
|
| 1787 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
|
| 1788 |
|
| 1789 | |
| 1790 | * enum dp_pixelformat - drm DP Pixel encoding formats
|
| 1791 | *
|
| 1792 | * This enum is used to indicate DP VSC SDP Pixel encoding formats.
|
| 1793 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
|
| 1794 | * DB18]
|
| 1795 | *
|
| 1796 | * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
|
| 1797 | * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
|
| 1798 | * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
|
| 1799 | * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
|
| 1800 | * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
|
| 1801 | * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
|
| 1802 | * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
|
| 1803 |
|
| 1804 | enum dp_pixelformat {
|
| 1805 | DP_PIXELFORMAT_RGB = 0,
|
| 1806 | DP_PIXELFORMAT_YUV444 = 0x1,
|
| 1807 | DP_PIXELFORMAT_YUV422 = 0x2,
|
| 1808 | DP_PIXELFORMAT_YUV420 = 0x3,
|
| 1809 | DP_PIXELFORMAT_Y_ONLY = 0x4,
|
| 1810 | DP_PIXELFORMAT_RAW = 0x5,
|
| 1811 | DP_PIXELFORMAT_RESERVED = 0x6,
|
| 1812 | };
|
| 1813 |
|
| 1814 | |
| 1815 | * enum dp_colorimetry - drm DP Colorimetry formats
|
| 1816 | *
|
| 1817 | * This enum is used to indicate DP VSC SDP Colorimetry formats.
|
| 1818 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
|
| 1819 | * DB18] and a name of enum member follows enum drm_colorimetry definition.
|
| 1820 | *
|
| 1821 | * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
|
| 1822 | * ITU-R BT.601 colorimetry format
|
| 1823 | * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
|
| 1824 | * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
|
| 1825 | * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
|
| 1826 | * (scRGB (IEC 61966-2-2)) colorimetry format
|
| 1827 | * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
|
| 1828 | * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
|
| 1829 | * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
|
| 1830 | * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
|
| 1831 | * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
|
| 1832 | * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
|
| 1833 | * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
|
| 1834 | * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
|
| 1835 | * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
|
| 1836 | * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
|
| 1837 |
|
| 1838 | enum dp_colorimetry {
|
| 1839 | DP_COLORIMETRY_DEFAULT = 0,
|
| 1840 | DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
|
| 1841 | DP_COLORIMETRY_BT709_YCC = 0x1,
|
| 1842 | DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
|
| 1843 | DP_COLORIMETRY_XVYCC_601 = 0x2,
|
| 1844 | DP_COLORIMETRY_OPRGB = 0x3,
|
| 1845 | DP_COLORIMETRY_XVYCC_709 = 0x3,
|
| 1846 | DP_COLORIMETRY_DCI_P3_RGB = 0x4,
|
| 1847 | DP_COLORIMETRY_SYCC_601 = 0x4,
|
| 1848 | DP_COLORIMETRY_RGB_CUSTOM = 0x5,
|
| 1849 | DP_COLORIMETRY_OPYCC_601 = 0x5,
|
| 1850 | DP_COLORIMETRY_BT2020_RGB = 0x6,
|
| 1851 | DP_COLORIMETRY_BT2020_CYCC = 0x6,
|
| 1852 | DP_COLORIMETRY_BT2020_YCC = 0x7,
|
| 1853 | };
|
| 1854 |
|
| 1855 | |
| 1856 | * enum dp_dynamic_range - drm DP Dynamic Range
|
| 1857 | *
|
| 1858 | * This enum is used to indicate DP VSC SDP Dynamic Range.
|
| 1859 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
|
| 1860 | * DB18]
|
| 1861 | *
|
| 1862 | * @DP_DYNAMIC_RANGE_VESA: VESA range
|
| 1863 | * @DP_DYNAMIC_RANGE_CTA: CTA range
|
| 1864 |
|
| 1865 | enum dp_dynamic_range {
|
| 1866 | DP_DYNAMIC_RANGE_VESA = 0,
|
| 1867 | DP_DYNAMIC_RANGE_CTA = 1,
|
| 1868 | };
|
| 1869 |
|
| 1870 | |
| 1871 | * enum dp_content_type - drm DP Content Type
|
| 1872 | *
|
| 1873 | * This enum is used to indicate DP VSC SDP Content Types.
|
| 1874 | * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
|
| 1875 | * DB18]
|
| 1876 | * CTA-861-G defines content types and expected processing by a sink device
|
| 1877 | *
|
| 1878 | * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
|
| 1879 | * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
|
| 1880 | * @DP_CONTENT_TYPE_PHOTO: Photo type
|
| 1881 | * @DP_CONTENT_TYPE_VIDEO: Video type
|
| 1882 | * @DP_CONTENT_TYPE_GAME: Game type
|
| 1883 |
|
| 1884 | enum dp_content_type {
|
| 1885 | DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
|
| 1886 | DP_CONTENT_TYPE_GRAPHICS = 0x01,
|
| 1887 | DP_CONTENT_TYPE_PHOTO = 0x02,
|
| 1888 | DP_CONTENT_TYPE_VIDEO = 0x03,
|
| 1889 | DP_CONTENT_TYPE_GAME = 0x04,
|
| 1890 | };
|
| 1891 |
|
| 1892 | enum operation_mode {
|
| 1893 | DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
|
| 1894 | DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
|
| 1895 | DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
|
| 1896 | DP_AS_SDP_FAVT_TRR_REACHED = 0x03
|
| 1897 | };
|
| 1898 |
|
| 1899 | #define DP_AS_SDP_OPERATION_MODE_MASK GENMASK(1, 0)
|
| 1900 | #define DP_AS_SDP_LENGTH_MASK GENMASK(5, 0)
|
| 1901 |
|
| 1902 | #endif
|