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| 2 | * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
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| 3 | *
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a
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| 5 | * copy of this software and associated documentation files (the "Software"),
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| 6 | * to deal in the Software without restriction, including without limitation
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sub license,
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the
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| 9 | * Software is furnished to do so, subject to the following conditions:
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| 10 | *
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| 11 | * The above copyright notice and this permission notice (including the
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| 12 | * next paragraph) shall be included in all copies or substantial portions
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| 13 | * of the Software.
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| 14 | *
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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| 21 | * DEALINGS IN THE SOFTWARE.
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| 22 |
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| 23 |
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| 24 | #ifndef DRM_SCDC_H
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| 25 | #define DRM_SCDC_H
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| 26 |
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| 27 | #define SCDC_SINK_VERSION 0x01
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| 28 |
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| 29 | #define SCDC_SOURCE_VERSION 0x02
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| 30 |
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| 31 | #define SCDC_UPDATE_0 0x10
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| 32 | #define SCDC_READ_REQUEST_TEST (1 << 2)
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| 33 | #define SCDC_CED_UPDATE (1 << 1)
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| 34 | #define SCDC_STATUS_UPDATE (1 << 0)
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| 35 |
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| 36 | #define SCDC_UPDATE_1 0x11
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| 37 |
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| 38 | #define SCDC_TMDS_CONFIG 0x20
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| 39 | #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
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| 40 | #define SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
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| 41 | #define SCDC_SCRAMBLING_ENABLE (1 << 0)
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| 42 |
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| 43 | #define SCDC_SCRAMBLER_STATUS 0x21
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| 44 | #define SCDC_SCRAMBLING_STATUS (1 << 0)
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| 45 |
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| 46 | #define SCDC_CONFIG_0 0x30
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| 47 | #define SCDC_READ_REQUEST_ENABLE (1 << 0)
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| 48 |
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| 49 | #define SCDC_STATUS_FLAGS_0 0x40
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| 50 | #define SCDC_CH2_LOCK (1 << 3)
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| 51 | #define SCDC_CH1_LOCK (1 << 2)
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| 52 | #define SCDC_CH0_LOCK (1 << 1)
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| 53 | #define SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
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| 54 | #define SCDC_CLOCK_DETECT (1 << 0)
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| 55 |
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| 56 | #define SCDC_STATUS_FLAGS_1 0x41
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| 57 |
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| 58 | #define SCDC_ERR_DET_0_L 0x50
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| 59 | #define SCDC_ERR_DET_0_H 0x51
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| 60 | #define SCDC_ERR_DET_1_L 0x52
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| 61 | #define SCDC_ERR_DET_1_H 0x53
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| 62 | #define SCDC_ERR_DET_2_L 0x54
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| 63 | #define SCDC_ERR_DET_2_H 0x55
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| 64 | #define SCDC_CHANNEL_VALID (1 << 7)
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| 65 |
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| 66 | #define SCDC_ERR_DET_CHECKSUM 0x56
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| 67 |
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| 68 | #define SCDC_TEST_CONFIG_0 0xc0
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| 69 | #define SCDC_TEST_READ_REQUEST (1 << 7)
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| 70 | #define SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
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| 71 |
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| 72 | #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
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| 73 | #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
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| 74 |
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| 75 | #define SCDC_DEVICE_ID 0xd3
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| 76 | #define SCDC_DEVICE_ID_SIZE 8
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| 77 |
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| 78 | #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
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| 79 | #define SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
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| 80 | #define SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
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| 81 |
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| 82 | #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
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| 83 | #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
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| 84 |
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| 85 | #define SCDC_MANUFACTURER_SPECIFIC 0xde
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| 86 | #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
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| 87 |
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| 88 | #endif
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