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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Type definitions for the Microsoft hypervisor.
4 */
5#ifndef _HV_HVGDK_MINI_H
6#define _HV_HVGDK_MINI_H
7
8#include <linux/types.h>
9#include <linux/bits.h>
10
11struct hv_u128 {
12 u64 low_part;
13 u64 high_part;
14} __packed;
15
16/* NOTE: when adding below, update hv_result_to_string() */
17#define HV_STATUS_SUCCESS 0x0
18#define HV_STATUS_INVALID_HYPERCALL_CODE 0x2
19#define HV_STATUS_INVALID_HYPERCALL_INPUT 0x3
20#define HV_STATUS_INVALID_ALIGNMENT 0x4
21#define HV_STATUS_INVALID_PARAMETER 0x5
22#define HV_STATUS_ACCESS_DENIED 0x6
23#define HV_STATUS_INVALID_PARTITION_STATE 0x7
24#define HV_STATUS_OPERATION_DENIED 0x8
25#define HV_STATUS_UNKNOWN_PROPERTY 0x9
26#define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0xA
27#define HV_STATUS_INSUFFICIENT_MEMORY 0xB
28#define HV_STATUS_INVALID_PARTITION_ID 0xD
29#define HV_STATUS_INVALID_VP_INDEX 0xE
30#define HV_STATUS_NOT_FOUND 0x10
31#define HV_STATUS_INVALID_PORT_ID 0x11
32#define HV_STATUS_INVALID_CONNECTION_ID 0x12
33#define HV_STATUS_INSUFFICIENT_BUFFERS 0x13
34#define HV_STATUS_NOT_ACKNOWLEDGED 0x14
35#define HV_STATUS_INVALID_VP_STATE 0x15
36#define HV_STATUS_NO_RESOURCES 0x1D
37#define HV_STATUS_PROCESSOR_FEATURE_NOT_SUPPORTED 0x20
38#define HV_STATUS_INVALID_LP_INDEX 0x41
39#define HV_STATUS_INVALID_REGISTER_VALUE 0x50
40#define HV_STATUS_OPERATION_FAILED 0x71
41#define HV_STATUS_INSUFFICIENT_ROOT_MEMORY 0x73
42#define HV_STATUS_INSUFFICIENT_CONTIGUOUS_MEMORY 0x75
43#define HV_STATUS_TIME_OUT 0x78
44#define HV_STATUS_CALL_PENDING 0x79
45#define HV_STATUS_INSUFFICIENT_CONTIGUOUS_ROOT_MEMORY 0x83
46#define HV_STATUS_VTL_ALREADY_ENABLED 0x86
47
48/*
49 * The Hyper-V TimeRefCount register and the TSC
50 * page provide a guest VM clock with 100ns tick rate
51 */
52#define HV_CLOCK_HZ (NSEC_PER_SEC / 100)
53
54#define HV_HYP_PAGE_SHIFT 12
55#define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
56#define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
57#define HV_HYP_LARGE_PAGE_SHIFT 21
58
59#define HV_PARTITION_ID_INVALID ((u64)0)
60#define HV_PARTITION_ID_SELF ((u64)-1)
61
62/* Hyper-V specific model specific registers (MSRs) */
63
64#if defined(CONFIG_X86)
65/* HV_X64_SYNTHETIC_MSR */
66#define HV_X64_MSR_GUEST_OS_ID 0x40000000
67#define HV_X64_MSR_HYPERCALL 0x40000001
68#define HV_X64_MSR_VP_INDEX 0x40000002
69#define HV_X64_MSR_RESET 0x40000003
70#define HV_X64_MSR_VP_RUNTIME 0x40000010
71#define HV_X64_MSR_TIME_REF_COUNT 0x40000020
72#define HV_X64_MSR_REFERENCE_TSC 0x40000021
73#define HV_X64_MSR_TSC_FREQUENCY 0x40000022
74#define HV_X64_MSR_APIC_FREQUENCY 0x40000023
75
76/* Define the virtual APIC registers */
77#define HV_X64_MSR_EOI 0x40000070
78#define HV_X64_MSR_ICR 0x40000071
79#define HV_X64_MSR_TPR 0x40000072
80#define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073
81
82/* Define synthetic interrupt controller model specific registers. */
83#define HV_X64_MSR_SCONTROL 0x40000080
84#define HV_X64_MSR_SVERSION 0x40000081
85#define HV_X64_MSR_SIEFP 0x40000082
86#define HV_X64_MSR_SIMP 0x40000083
87#define HV_X64_MSR_EOM 0x40000084
88#define HV_X64_MSR_SIRBP 0x40000085
89#define HV_X64_MSR_SINT0 0x40000090
90#define HV_X64_MSR_SINT1 0x40000091
91#define HV_X64_MSR_SINT2 0x40000092
92#define HV_X64_MSR_SINT3 0x40000093
93#define HV_X64_MSR_SINT4 0x40000094
94#define HV_X64_MSR_SINT5 0x40000095
95#define HV_X64_MSR_SINT6 0x40000096
96#define HV_X64_MSR_SINT7 0x40000097
97#define HV_X64_MSR_SINT8 0x40000098
98#define HV_X64_MSR_SINT9 0x40000099
99#define HV_X64_MSR_SINT10 0x4000009A
100#define HV_X64_MSR_SINT11 0x4000009B
101#define HV_X64_MSR_SINT12 0x4000009C
102#define HV_X64_MSR_SINT13 0x4000009D
103#define HV_X64_MSR_SINT14 0x4000009E
104#define HV_X64_MSR_SINT15 0x4000009F
105
106/* Define synthetic interrupt controller model specific registers for nested hypervisor */
107#define HV_X64_MSR_NESTED_SCONTROL 0x40001080
108#define HV_X64_MSR_NESTED_SVERSION 0x40001081
109#define HV_X64_MSR_NESTED_SIEFP 0x40001082
110#define HV_X64_MSR_NESTED_SIMP 0x40001083
111#define HV_X64_MSR_NESTED_EOM 0x40001084
112#define HV_X64_MSR_NESTED_SINT0 0x40001090
113
114/*
115 * Synthetic Timer MSRs. Four timers per vcpu.
116 */
117#define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
118#define HV_X64_MSR_STIMER0_COUNT 0x400000B1
119#define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
120#define HV_X64_MSR_STIMER1_COUNT 0x400000B3
121#define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
122#define HV_X64_MSR_STIMER2_COUNT 0x400000B5
123#define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
124#define HV_X64_MSR_STIMER3_COUNT 0x400000B7
125
126/* Hyper-V guest idle MSR */
127#define HV_X64_MSR_GUEST_IDLE 0x400000F0
128
129/* Hyper-V guest crash notification MSR's */
130#define HV_X64_MSR_CRASH_P0 0x40000100
131#define HV_X64_MSR_CRASH_P1 0x40000101
132#define HV_X64_MSR_CRASH_P2 0x40000102
133#define HV_X64_MSR_CRASH_P3 0x40000103
134#define HV_X64_MSR_CRASH_P4 0x40000104
135#define HV_X64_MSR_CRASH_CTL 0x40000105
136
137#define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001
138#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12
139#define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \
140 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
141
142#define HV_X64_MSR_CRASH_PARAMS \
143 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0))
144
145#define HV_IPI_LOW_VECTOR 0x10
146#define HV_IPI_HIGH_VECTOR 0xff
147
148#define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001
149#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
150#define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \
151 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
152
153/* Hyper-V Enlightened VMCS version mask in nested features CPUID */
154#define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff
155
156#define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001
157#define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12
158
159/* Number of XMM registers used in hypercall input/output */
160#define HV_HYPERCALL_MAX_XMM_REGISTERS 6
161
162struct hv_reenlightenment_control {
163 u64 vector : 8;
164 u64 reserved1 : 8;
165 u64 enabled : 1;
166 u64 reserved2 : 15;
167 u64 target_vp : 32;
168} __packed;
169
170struct hv_tsc_emulation_status { /* HV_TSC_EMULATION_STATUS */
171 u64 inprogress : 1;
172 u64 reserved : 63;
173} __packed;
174
175struct hv_tsc_emulation_control { /* HV_TSC_INVARIANT_CONTROL */
176 u64 enabled : 1;
177 u64 reserved : 63;
178} __packed;
179
180/* TSC emulation after migration */
181#define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
182#define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
183#define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
184#define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
185#define HV_EXPOSE_INVARIANT_TSC BIT_ULL(0)
186
187#endif /* CONFIG_X86 */
188
189struct hv_output_get_partition_id {
190 u64 partition_id;
191} __packed;
192
193/* HV_CRASH_CTL_REG_CONTENTS */
194#define HV_CRASH_CTL_CRASH_NOTIFY_MSG BIT_ULL(62)
195#define HV_CRASH_CTL_CRASH_NOTIFY BIT_ULL(63)
196
197union hv_reference_tsc_msr {
198 u64 as_uint64;
199 struct {
200 u64 enable : 1;
201 u64 reserved : 11;
202 u64 pfn : 52;
203 } __packed;
204};
205
206/* The maximum number of sparse vCPU banks which can be encoded by 'struct hv_vpset' */
207#define HV_MAX_SPARSE_VCPU_BANKS (64)
208/* The number of vCPUs in one sparse bank */
209#define HV_VCPUS_PER_SPARSE_BANK (64)
210
211/*
212 * Some of Hyper-V structs do not use hv_vpset where linux uses them.
213 *
214 * struct hv_vpset is usually used as part of hypercall input. The portion
215 * that counts as "fixed size input header" vs. "variable size input header"
216 * varies per hypercall. See comments at relevant hypercall call sites as to
217 * how the "valid_bank_mask" field should be accounted.
218 */
219struct hv_vpset { /* HV_VP_SET */
220 u64 format;
221 u64 valid_bank_mask;
222 u64 bank_contents[];
223} __packed;
224
225/*
226 * Version info reported by hypervisor
227 * Changed to a union for convenience
228 */
229union hv_hypervisor_version_info {
230 struct {
231 u32 build_number;
232
233 u32 minor_version : 16;
234 u32 major_version : 16;
235
236 u32 service_pack;
237
238 u32 service_number : 24;
239 u32 service_branch : 8;
240 };
241 struct {
242 u32 eax;
243 u32 ebx;
244 u32 ecx;
245 u32 edx;
246 };
247};
248
249/* HV_CPUID_FUNCTION */
250#define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
251#define HYPERV_CPUID_INTERFACE 0x40000001
252#define HYPERV_CPUID_VERSION 0x40000002
253#define HYPERV_CPUID_FEATURES 0x40000003
254#define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
255#define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
256#define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007
257#define HYPERV_CPUID_NESTED_FEATURES 0x4000000A
258#define HYPERV_CPUID_ISOLATION_CONFIG 0x4000000C
259
260#define HYPERV_CPUID_VIRT_STACK_INTERFACE 0x40000081
261#define HYPERV_VS_INTERFACE_EAX_SIGNATURE 0x31235356 /* "VS#1" */
262
263#define HYPERV_CPUID_VIRT_STACK_PROPERTIES 0x40000082
264/* Support for the extended IOAPIC RTE format */
265#define HYPERV_VS_PROPERTIES_EAX_EXTENDED_IOAPIC_RTE BIT(2)
266#define HYPERV_VS_PROPERTIES_EAX_CONFIDENTIAL_VMBUS_AVAILABLE BIT(3)
267
268#define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000
269#define HYPERV_CPUID_MIN 0x40000005
270#define HYPERV_CPUID_MAX 0x4000ffff
271
272/*
273 * HV_X64_HYPERVISOR_FEATURES (EAX), or
274 * HV_PARTITION_PRIVILEGE_MASK [31-0]
275 */
276#define HV_MSR_VP_RUNTIME_AVAILABLE BIT(0)
277#define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)
278#define HV_MSR_SYNIC_AVAILABLE BIT(2)
279#define HV_MSR_SYNTIMER_AVAILABLE BIT(3)
280#define HV_MSR_APIC_ACCESS_AVAILABLE BIT(4)
281#define HV_MSR_HYPERCALL_AVAILABLE BIT(5)
282#define HV_MSR_VP_INDEX_AVAILABLE BIT(6)
283#define HV_MSR_RESET_AVAILABLE BIT(7)
284#define HV_MSR_STAT_PAGES_AVAILABLE BIT(8)
285#define HV_MSR_REFERENCE_TSC_AVAILABLE BIT(9)
286#define HV_MSR_GUEST_IDLE_AVAILABLE BIT(10)
287#define HV_ACCESS_FREQUENCY_MSRS BIT(11)
288#define HV_ACCESS_REENLIGHTENMENT BIT(13)
289#define HV_ACCESS_TSC_INVARIANT BIT(15)
290
291/*
292 * HV_X64_HYPERVISOR_FEATURES (EBX), or
293 * HV_PARTITION_PRIVILEGE_MASK [63-32]
294 */
295#define HV_CREATE_PARTITIONS BIT(0)
296#define HV_ACCESS_PARTITION_ID BIT(1)
297#define HV_ACCESS_MEMORY_POOL BIT(2)
298#define HV_ADJUST_MESSAGE_BUFFERS BIT(3)
299#define HV_POST_MESSAGES BIT(4)
300#define HV_SIGNAL_EVENTS BIT(5)
301#define HV_CREATE_PORT BIT(6)
302#define HV_CONNECT_PORT BIT(7)
303#define HV_ACCESS_STATS BIT(8)
304#define HV_DEBUGGING BIT(11)
305#define HV_CPU_MANAGEMENT BIT(12)
306#define HV_ENABLE_EXTENDED_HYPERCALLS BIT(20)
307#define HV_ISOLATION BIT(22)
308
309#if defined(CONFIG_X86)
310/* HV_X64_HYPERVISOR_FEATURES (EDX) */
311#define HV_X64_MWAIT_AVAILABLE BIT(0)
312#define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1)
313#define HV_X64_PERF_MONITOR_AVAILABLE BIT(2)
314#define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3)
315#define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE BIT(4)
316#define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5)
317#define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8)
318#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10)
319#define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11)
320#define HV_FEATURE_EXT_GVA_RANGES_FLUSH BIT(14)
321/*
322 * Support for returning hypercall output block via XMM
323 * registers is available
324 */
325#define HV_X64_HYPERCALL_XMM_OUTPUT_AVAILABLE BIT(15)
326/* stimer Direct Mode is available */
327#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19)
328
329/*
330 * Implementation recommendations. Indicates which behaviors the hypervisor
331 * recommends the OS implement for optimal performance.
332 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits.
333 */
334/* HV_X64_ENLIGHTENMENT_INFORMATION */
335#define HV_X64_AS_SWITCH_RECOMMENDED BIT(0)
336#define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1)
337#define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2)
338#define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3)
339#define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4)
340#define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5)
341#define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9)
342#define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10)
343#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11)
344#define HV_X64_HYPERV_NESTED BIT(12)
345#define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14)
346#define HV_X64_USE_MMIO_HYPERCALLS BIT(21)
347
348/*
349 * CPU management features identification.
350 * These are HYPERV_CPUID_CPU_MANAGEMENT_FEATURES.EAX bits.
351 */
352#define HV_X64_START_LOGICAL_PROCESSOR BIT(0)
353#define HV_X64_CREATE_ROOT_VIRTUAL_PROCESSOR BIT(1)
354#define HV_X64_PERFORMANCE_COUNTER_SYNC BIT(2)
355#define HV_X64_RESERVED_IDENTITY_BIT BIT(31)
356
357/*
358 * Virtual processor will never share a physical core with another virtual
359 * processor, except for virtual processors that are reported as sibling SMT
360 * threads.
361 */
362#define HV_X64_NO_NONARCH_CORESHARING BIT(18)
363
364/* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */
365#define HV_X64_NESTED_DIRECT_FLUSH BIT(17)
366#define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18)
367#define HV_X64_NESTED_MSR_BITMAP BIT(19)
368
369/* Nested features #2. These are HYPERV_CPUID_NESTED_FEATURES.EBX bits. */
370#define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL BIT(0)
371
372/*
373 * This is specific to AMD and specifies that enlightened TLB flush is
374 * supported. If guest opts in to this feature, ASID invalidations only
375 * flushes gva -> hpa mapping entries. To flush the TLB entries derived
376 * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
377 * or HvFlushGuestPhysicalAddressList).
378 */
379#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22)
380
381/* HYPERV_CPUID_ISOLATION_CONFIG.EAX bits. */
382#define HV_PARAVISOR_PRESENT BIT(0)
383
384/* HYPERV_CPUID_ISOLATION_CONFIG.EBX bits. */
385#define HV_ISOLATION_TYPE GENMASK(3, 0)
386#define HV_SHARED_GPA_BOUNDARY_ACTIVE BIT(5)
387#define HV_SHARED_GPA_BOUNDARY_BITS GENMASK(11, 6)
388
389/* HYPERV_CPUID_FEATURES.ECX bits. */
390#define HV_VP_DISPATCH_INTERRUPT_INJECTION_AVAILABLE BIT(9)
391#define HV_VP_GHCB_ROOT_MAPPING_AVAILABLE BIT(10)
392
393enum hv_isolation_type {
394 HV_ISOLATION_TYPE_NONE = 0, /* HV_PARTITION_ISOLATION_TYPE_NONE */
395 HV_ISOLATION_TYPE_VBS = 1,
396 HV_ISOLATION_TYPE_SNP = 2,
397 HV_ISOLATION_TYPE_TDX = 3
398};
399
400union hv_x64_msr_hypercall_contents {
401 u64 as_uint64;
402 struct {
403 u64 enable : 1;
404 u64 reserved : 11;
405 u64 guest_physical_address : 52;
406 } __packed;
407};
408#endif /* CONFIG_X86 */
409
410#if defined(CONFIG_ARM64)
411#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8)
412#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13)
413#endif /* CONFIG_ARM64 */
414
415#if defined(CONFIG_X86)
416#define HV_MAXIMUM_PROCESSORS 2048
417#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
418#define HV_MAXIMUM_PROCESSORS 320
419#endif /* CONFIG_ARM64 */
420
421#define HV_MAX_VP_INDEX (HV_MAXIMUM_PROCESSORS - 1)
422#define HV_VP_INDEX_SELF ((u32)-2)
423#define HV_ANY_VP ((u32)-1)
424
425union hv_vp_assist_msr_contents { /* HV_REGISTER_VP_ASSIST_PAGE */
426 u64 as_uint64;
427 struct {
428 u64 enable : 1;
429 u64 reserved : 11;
430 u64 pfn : 52;
431 } __packed;
432};
433
434/* Declare the various hypercall operations. */
435/* HV_CALL_CODE */
436#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
437#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
438#define HVCALL_GET_LOGICAL_PROCESSOR_RUN_TIME 0x0004
439#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
440#define HVCALL_SEND_IPI 0x000b
441#define HVCALL_ENABLE_VP_VTL 0x000f
442#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
443#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
444#define HVCALL_SEND_IPI_EX 0x0015
445#define HVCALL_CREATE_PARTITION 0x0040
446#define HVCALL_INITIALIZE_PARTITION 0x0041
447#define HVCALL_FINALIZE_PARTITION 0x0042
448#define HVCALL_DELETE_PARTITION 0x0043
449#define HVCALL_GET_PARTITION_PROPERTY 0x0044
450#define HVCALL_SET_PARTITION_PROPERTY 0x0045
451#define HVCALL_GET_PARTITION_ID 0x0046
452#define HVCALL_DEPOSIT_MEMORY 0x0048
453#define HVCALL_WITHDRAW_MEMORY 0x0049
454#define HVCALL_MAP_GPA_PAGES 0x004b
455#define HVCALL_UNMAP_GPA_PAGES 0x004c
456#define HVCALL_INSTALL_INTERCEPT 0x004d
457#define HVCALL_CREATE_VP 0x004e
458#define HVCALL_DELETE_VP 0x004f
459#define HVCALL_GET_VP_REGISTERS 0x0050
460#define HVCALL_SET_VP_REGISTERS 0x0051
461#define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052
462#define HVCALL_CLEAR_VIRTUAL_INTERRUPT 0x0056
463#define HVCALL_DELETE_PORT 0x0058
464#define HVCALL_DISCONNECT_PORT 0x005b
465#define HVCALL_POST_MESSAGE 0x005c
466#define HVCALL_SIGNAL_EVENT 0x005d
467#define HVCALL_POST_DEBUG_DATA 0x0069
468#define HVCALL_RETRIEVE_DEBUG_DATA 0x006a
469#define HVCALL_RESET_DEBUG_SESSION 0x006b
470#define HVCALL_MAP_STATS_PAGE 0x006c
471#define HVCALL_UNMAP_STATS_PAGE 0x006d
472#define HVCALL_SET_SYSTEM_PROPERTY 0x006f
473#define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076
474#define HVCALL_GET_SYSTEM_PROPERTY 0x007b
475#define HVCALL_MAP_DEVICE_INTERRUPT 0x007c
476#define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d
477#define HVCALL_RETARGET_INTERRUPT 0x007e
478#define HVCALL_NOTIFY_PARTITION_EVENT 0x0087
479#define HVCALL_ENTER_SLEEP_STATE 0x0084
480#define HVCALL_NOTIFY_PORT_RING_EMPTY 0x008b
481#define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091
482#define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094
483#define HVCALL_CREATE_PORT 0x0095
484#define HVCALL_CONNECT_PORT 0x0096
485#define HVCALL_START_VP 0x0099
486#define HVCALL_GET_VP_INDEX_FROM_APIC_ID 0x009a
487#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
488#define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
489#define HVCALL_SIGNAL_EVENT_DIRECT 0x00c0
490#define HVCALL_POST_MESSAGE_DIRECT 0x00c1
491#define HVCALL_DISPATCH_VP 0x00c2
492#define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9
493#define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7
494#define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8
495#define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db
496#define HVCALL_MAP_VP_STATE_PAGE 0x00e1
497#define HVCALL_UNMAP_VP_STATE_PAGE 0x00e2
498#define HVCALL_GET_VP_STATE 0x00e3
499#define HVCALL_SET_VP_STATE 0x00e4
500#define HVCALL_GET_VP_CPUID_VALUES 0x00f4
501#define HVCALL_GET_PARTITION_PROPERTY_EX 0x0101
502#define HVCALL_MMIO_READ 0x0106
503#define HVCALL_MMIO_WRITE 0x0107
504#define HVCALL_DISABLE_HYP_EX 0x010f
505#define HVCALL_MAP_STATS_PAGE2 0x0131
506
507/* HV_HYPERCALL_INPUT */
508#define HV_HYPERCALL_RESULT_MASK GENMASK_ULL(15, 0)
509#define HV_HYPERCALL_FAST_BIT BIT(16)
510#define HV_HYPERCALL_VARHEAD_OFFSET 17
511#define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17)
512#define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27)
513#define HV_HYPERCALL_NESTED BIT_ULL(31)
514#define HV_HYPERCALL_REP_COMP_OFFSET 32
515#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
516#define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32)
517#define HV_HYPERCALL_RSVD1_MASK GENMASK_ULL(47, 44)
518#define HV_HYPERCALL_REP_START_OFFSET 48
519#define HV_HYPERCALL_REP_START_MASK GENMASK_ULL(59, 48)
520#define HV_HYPERCALL_RSVD2_MASK GENMASK_ULL(63, 60)
521#define HV_HYPERCALL_RSVD_MASK (HV_HYPERCALL_RSVD0_MASK | \
522 HV_HYPERCALL_RSVD1_MASK | \
523 HV_HYPERCALL_RSVD2_MASK)
524
525/* HvFlushGuestPhysicalAddressSpace hypercalls */
526struct hv_guest_mapping_flush {
527 u64 address_space;
528 u64 flags;
529} __packed;
530
531/*
532 * HV_MAX_FLUSH_PAGES = "additional_pages" + 1. It's limited
533 * by the bitwidth of "additional_pages" in union hv_gpa_page_range.
534 */
535#define HV_MAX_FLUSH_PAGES (2048)
536#define HV_GPA_PAGE_RANGE_PAGE_SIZE_2MB 0
537#define HV_GPA_PAGE_RANGE_PAGE_SIZE_1GB 1
538
539#define HV_FLUSH_ALL_PROCESSORS BIT(0)
540#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
541#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
542#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
543
544/* HvFlushGuestPhysicalAddressList, HvExtCallMemoryHeatHint hypercall */
545union hv_gpa_page_range {
546 u64 address_space;
547 struct {
548 u64 additional_pages : 11;
549 u64 largepage : 1;
550 u64 basepfn : 52;
551 } page;
552 struct {
553 u64 reserved : 12;
554 u64 page_size : 1;
555 u64 reserved1 : 8;
556 u64 base_large_pfn : 43;
557 };
558};
559
560/*
561 * All input flush parameters should be in single page. The max flush
562 * count is equal with how many entries of union hv_gpa_page_range can
563 * be populated into the input parameter page.
564 */
565#define HV_MAX_FLUSH_REP_COUNT ((HV_HYP_PAGE_SIZE - 2 * sizeof(u64)) / \
566 sizeof(union hv_gpa_page_range))
567
568struct hv_guest_mapping_flush_list {
569 u64 address_space;
570 u64 flags;
571 union hv_gpa_page_range gpa_list[HV_MAX_FLUSH_REP_COUNT];
572};
573
574struct hv_tlb_flush { /* HV_INPUT_FLUSH_VIRTUAL_ADDRESS_LIST */
575 u64 address_space;
576 u64 flags;
577 u64 processor_mask;
578 u64 gva_list[];
579} __packed;
580
581/* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
582struct hv_tlb_flush_ex {
583 u64 address_space;
584 u64 flags;
585 __TRAILING_OVERLAP(struct hv_vpset, hv_vp_set, bank_contents, __packed,
586 u64 gva_list[];
587 );
588} __packed;
589static_assert(offsetof(struct hv_tlb_flush_ex, hv_vp_set.bank_contents) ==
590 offsetof(struct hv_tlb_flush_ex, gva_list));
591
592struct ms_hyperv_tsc_page { /* HV_REFERENCE_TSC_PAGE */
593 volatile u32 tsc_sequence;
594 u32 reserved1;
595 volatile u64 tsc_scale;
596 volatile s64 tsc_offset;
597} __packed;
598
599/* Define the number of synthetic interrupt sources. */
600#define HV_SYNIC_SINT_COUNT (16)
601
602/* Define the expected SynIC version. */
603#define HV_SYNIC_VERSION_1 (0x1)
604/* Valid SynIC vectors are 16-255. */
605#define HV_SYNIC_FIRST_VALID_VECTOR (16)
606
607#define HV_SYNIC_CONTROL_ENABLE (1ULL << 0)
608#define HV_SYNIC_SIMP_ENABLE (1ULL << 0)
609#define HV_SYNIC_SIEFP_ENABLE (1ULL << 0)
610#define HV_SYNIC_SINT_MASKED (1ULL << 16)
611#define HV_SYNIC_SINT_AUTO_EOI (1ULL << 17)
612#define HV_SYNIC_SINT_VECTOR_MASK (0xFF)
613
614/* Hyper-V defined statically assigned SINTs */
615#define HV_SYNIC_INTERCEPTION_SINT_INDEX 0x00000000
616#define HV_SYNIC_IOMMU_FAULT_SINT_INDEX 0x00000001
617#define HV_SYNIC_VMBUS_SINT_INDEX 0x00000002
618#define HV_SYNIC_FIRST_UNUSED_SINT_INDEX 0x00000005
619
620/* mshv assigned SINT for doorbell */
621#define HV_SYNIC_DOORBELL_SINT_INDEX HV_SYNIC_FIRST_UNUSED_SINT_INDEX
622
623enum hv_interrupt_type {
624 HV_X64_INTERRUPT_TYPE_FIXED = 0x0000,
625 HV_X64_INTERRUPT_TYPE_LOWESTPRIORITY = 0x0001,
626 HV_X64_INTERRUPT_TYPE_SMI = 0x0002,
627 HV_X64_INTERRUPT_TYPE_REMOTEREAD = 0x0003,
628 HV_X64_INTERRUPT_TYPE_NMI = 0x0004,
629 HV_X64_INTERRUPT_TYPE_INIT = 0x0005,
630 HV_X64_INTERRUPT_TYPE_SIPI = 0x0006,
631 HV_X64_INTERRUPT_TYPE_EXTINT = 0x0007,
632 HV_X64_INTERRUPT_TYPE_LOCALINT0 = 0x0008,
633 HV_X64_INTERRUPT_TYPE_LOCALINT1 = 0x0009,
634 HV_X64_INTERRUPT_TYPE_MAXIMUM = 0x000A,
635};
636
637/* Define synthetic interrupt source. */
638union hv_synic_sint {
639 u64 as_uint64;
640 struct {
641 u64 vector : 8;
642 u64 reserved1 : 8;
643 u64 masked : 1;
644 u64 auto_eoi : 1;
645 u64 polling : 1;
646 u64 as_intercept : 1;
647 u64 proxy : 1;
648 u64 reserved2 : 43;
649 } __packed;
650};
651
652union hv_x64_xsave_xfem_register {
653 u64 as_uint64;
654 struct {
655 u32 low_uint32;
656 u32 high_uint32;
657 } __packed;
658 struct {
659 u64 legacy_x87 : 1;
660 u64 legacy_sse : 1;
661 u64 avx : 1;
662 u64 mpx_bndreg : 1;
663 u64 mpx_bndcsr : 1;
664 u64 avx_512_op_mask : 1;
665 u64 avx_512_zmmhi : 1;
666 u64 avx_512_zmm16_31 : 1;
667 u64 rsvd8_9 : 2;
668 u64 pasid : 1;
669 u64 cet_u : 1;
670 u64 cet_s : 1;
671 u64 rsvd13_16 : 4;
672 u64 xtile_cfg : 1;
673 u64 xtile_data : 1;
674 u64 rsvd19_63 : 45;
675 } __packed;
676};
677
678/* Synthetic timer configuration */
679union hv_stimer_config { /* HV_X64_MSR_STIMER_CONFIG_CONTENTS */
680 u64 as_uint64;
681 struct {
682 u64 enable : 1;
683 u64 periodic : 1;
684 u64 lazy : 1;
685 u64 auto_enable : 1;
686 u64 apic_vector : 8;
687 u64 direct_mode : 1;
688 u64 reserved_z0 : 3;
689 u64 sintx : 4;
690 u64 reserved_z1 : 44;
691 } __packed;
692};
693
694/* Define the number of synthetic timers */
695#define HV_SYNIC_STIMER_COUNT (4)
696
697/* Define port identifier type. */
698union hv_port_id {
699 u32 asu32;
700 struct {
701 u32 id : 24;
702 u32 reserved : 8;
703 } __packed u;
704};
705
706#define HV_MESSAGE_SIZE (256)
707#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
708#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
709
710/* Define hypervisor message types. */
711enum hv_message_type {
712 HVMSG_NONE = 0x00000000,
713
714 /* Memory access messages. */
715 HVMSG_UNMAPPED_GPA = 0x80000000,
716 HVMSG_GPA_INTERCEPT = 0x80000001,
717
718 /* Timer notification messages. */
719 HVMSG_TIMER_EXPIRED = 0x80000010,
720
721 /* Error messages. */
722 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
723 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
724 HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
725
726 /*
727 * Opaque intercept message. The original intercept message is only
728 * accessible from the mapped intercept message page.
729 */
730 HVMSG_OPAQUE_INTERCEPT = 0x8000003F,
731
732 /* Trace buffer complete messages. */
733 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
734
735 /* Hypercall intercept */
736 HVMSG_HYPERCALL_INTERCEPT = 0x80000050,
737
738 /* SynIC intercepts */
739 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060,
740 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061,
741 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062,
742
743 /* Async call completion intercept */
744 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070,
745
746 /* Root scheduler messages */
747 HVMSG_SCHEDULER_VP_SIGNAL_BITSET = 0x80000100,
748 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101,
749
750 /* Platform-specific processor intercept messages. */
751 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000,
752 HVMSG_X64_MSR_INTERCEPT = 0x80010001,
753 HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
754 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
755 HVMSG_X64_APIC_EOI = 0x80010004,
756 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005,
757 HVMSG_X64_IOMMU_PRQ = 0x80010006,
758 HVMSG_X64_HALT = 0x80010007,
759 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008,
760 HVMSG_X64_SIPI_INTERCEPT = 0x80010009,
761};
762
763/* Define the format of the SIMP register */
764union hv_synic_simp {
765 u64 as_uint64;
766 struct {
767 u64 simp_enabled : 1;
768 u64 preserved : 11;
769 u64 base_simp_gpa : 52;
770 } __packed;
771};
772
773union hv_message_flags {
774 u8 asu8;
775 struct {
776 u8 msg_pending : 1;
777 u8 reserved : 7;
778 } __packed;
779};
780
781struct hv_message_header {
782 u32 message_type;
783 u8 payload_size;
784 union hv_message_flags message_flags;
785 u8 reserved[2];
786 union {
787 u64 sender;
788 union hv_port_id port;
789 };
790} __packed;
791
792/*
793 * Message format for notifications delivered via
794 * intercept message(as_intercept=1)
795 */
796struct hv_notification_message_payload {
797 u32 sint_index;
798} __packed;
799
800struct hv_message {
801 struct hv_message_header header;
802 union {
803 u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
804 } u;
805} __packed;
806
807/* Define the synthetic interrupt message page layout. */
808struct hv_message_page {
809 struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
810} __packed;
811
812/* Define timer message payload structure. */
813struct hv_timer_message_payload {
814 u32 timer_index;
815 u32 reserved;
816 u64 expiration_time; /* When the timer expired */
817 u64 delivery_time; /* When the message was delivered */
818} __packed;
819
820struct hv_x64_segment_register {
821 u64 base;
822 u32 limit;
823 u16 selector;
824 union {
825 struct {
826 u16 segment_type : 4;
827 u16 non_system_segment : 1;
828 u16 descriptor_privilege_level : 2;
829 u16 present : 1;
830 u16 reserved : 4;
831 u16 available : 1;
832 u16 _long : 1;
833 u16 _default : 1;
834 u16 granularity : 1;
835 } __packed;
836 u16 attributes;
837 };
838} __packed;
839
840struct hv_x64_table_register {
841 u16 pad[3];
842 u16 limit;
843 u64 base;
844} __packed;
845
846#define HV_NORMAL_VTL 0
847
848union hv_input_vtl {
849 u8 as_uint8;
850 struct {
851 u8 target_vtl : 4;
852 u8 use_target_vtl : 1;
853 u8 reserved_z : 3;
854 };
855} __packed;
856
857struct hv_init_vp_context {
858 u64 rip;
859 u64 rsp;
860 u64 rflags;
861
862 struct hv_x64_segment_register cs;
863 struct hv_x64_segment_register ds;
864 struct hv_x64_segment_register es;
865 struct hv_x64_segment_register fs;
866 struct hv_x64_segment_register gs;
867 struct hv_x64_segment_register ss;
868 struct hv_x64_segment_register tr;
869 struct hv_x64_segment_register ldtr;
870
871 struct hv_x64_table_register idtr;
872 struct hv_x64_table_register gdtr;
873
874 u64 efer;
875 u64 cr0;
876 u64 cr3;
877 u64 cr4;
878 u64 msr_cr_pat;
879} __packed;
880
881struct hv_enable_vp_vtl {
882 u64 partition_id;
883 u32 vp_index;
884 union hv_input_vtl target_vtl;
885 u8 mbz0;
886 u16 mbz1;
887 struct hv_init_vp_context vp_context;
888} __packed;
889
890struct hv_get_vp_from_apic_id_in {
891 u64 partition_id;
892 union hv_input_vtl target_vtl;
893 u8 res[7];
894 u32 apic_ids[];
895} __packed;
896
897union hv_register_vsm_partition_config {
898 u64 as_uint64;
899 struct {
900 u64 enable_vtl_protection : 1;
901 u64 default_vtl_protection_mask : 4;
902 u64 zero_memory_on_reset : 1;
903 u64 deny_lower_vtl_startup : 1;
904 u64 intercept_acceptance : 1;
905 u64 intercept_enable_vtl_protection : 1;
906 u64 intercept_vp_startup : 1;
907 u64 intercept_cpuid_unimplemented : 1;
908 u64 intercept_unrecoverable_exception : 1;
909 u64 intercept_page : 1;
910 u64 mbz : 51;
911 } __packed;
912};
913
914union hv_register_vsm_capabilities {
915 u64 as_uint64;
916 struct {
917 u64 dr6_shared: 1;
918 u64 mbec_vtl_mask: 16;
919 u64 deny_lower_vtl_startup: 1;
920 u64 supervisor_shadow_stack: 1;
921 u64 hardware_hvpt_available: 1;
922 u64 software_hvpt_available: 1;
923 u64 hardware_hvpt_range_bits: 6;
924 u64 intercept_page_available: 1;
925 u64 return_action_available: 1;
926 u64 reserved: 35;
927 } __packed;
928};
929
930union hv_register_vsm_page_offsets {
931 struct {
932 u64 vtl_call_offset : 12;
933 u64 vtl_return_offset : 12;
934 u64 reserved_mbz : 40;
935 } __packed;
936 u64 as_uint64;
937};
938
939struct hv_nested_enlightenments_control {
940 struct {
941 u32 directhypercall : 1;
942 u32 reserved : 31;
943 } __packed features;
944 struct {
945 u32 inter_partition_comm : 1;
946 u32 reserved : 31;
947 } __packed hypercall_controls;
948} __packed;
949
950/* Define virtual processor assist page structure. */
951struct hv_vp_assist_page {
952 u32 apic_assist;
953 u32 reserved1;
954 u32 vtl_entry_reason;
955 u32 vtl_reserved;
956 u64 vtl_ret_x64rax;
957 u64 vtl_ret_x64rcx;
958 struct hv_nested_enlightenments_control nested_control;
959 u8 enlighten_vmentry;
960 u8 reserved2[7];
961 u64 current_nested_vmcs;
962 u8 synthetic_time_unhalted_timer_expired;
963 u8 reserved3[7];
964 u8 virtualization_fault_information[40];
965 u8 reserved4[8];
966 u8 intercept_message[256];
967 u8 vtl_ret_actions[256];
968} __packed;
969
970enum hv_register_name {
971 /* Suspend Registers */
972 HV_REGISTER_EXPLICIT_SUSPEND = 0x00000000,
973 HV_REGISTER_INTERCEPT_SUSPEND = 0x00000001,
974 HV_REGISTER_DISPATCH_SUSPEND = 0x00000003,
975
976 /* Version - 128-bit result same as CPUID 0x40000002 */
977 HV_REGISTER_HYPERVISOR_VERSION = 0x00000100,
978
979 /* Feature Access (registers are 128 bits) - same as CPUID 0x40000003 - 0x4000000B */
980 HV_REGISTER_PRIVILEGES_AND_FEATURES_INFO = 0x00000200,
981 HV_REGISTER_FEATURES_INFO = 0x00000201,
982 HV_REGISTER_IMPLEMENTATION_LIMITS_INFO = 0x00000202,
983 HV_REGISTER_HARDWARE_FEATURES_INFO = 0x00000203,
984 HV_REGISTER_CPU_MANAGEMENT_FEATURES_INFO = 0x00000204,
985 HV_REGISTER_SVM_FEATURES_INFO = 0x00000205,
986 HV_REGISTER_SKIP_LEVEL_FEATURES_INFO = 0x00000206,
987 HV_REGISTER_NESTED_VIRT_FEATURES_INFO = 0x00000207,
988 HV_REGISTER_IPT_FEATURES_INFO = 0x00000208,
989
990 /* Guest Crash Registers */
991 HV_REGISTER_GUEST_CRASH_P0 = 0x00000210,
992 HV_REGISTER_GUEST_CRASH_P1 = 0x00000211,
993 HV_REGISTER_GUEST_CRASH_P2 = 0x00000212,
994 HV_REGISTER_GUEST_CRASH_P3 = 0x00000213,
995 HV_REGISTER_GUEST_CRASH_P4 = 0x00000214,
996 HV_REGISTER_GUEST_CRASH_CTL = 0x00000215,
997
998 /* Misc */
999 HV_REGISTER_VP_RUNTIME = 0x00090000,
1000 HV_REGISTER_GUEST_OS_ID = 0x00090002,
1001 HV_REGISTER_VP_INDEX = 0x00090003,
1002 HV_REGISTER_TIME_REF_COUNT = 0x00090004,
1003 HV_REGISTER_CPU_MANAGEMENT_VERSION = 0x00090007,
1004 HV_REGISTER_VP_ASSIST_PAGE = 0x00090013,
1005 HV_REGISTER_VP_ROOT_SIGNAL_COUNT = 0x00090014,
1006 HV_REGISTER_REFERENCE_TSC = 0x00090017,
1007
1008 /* Hypervisor-defined Registers (Synic) */
1009 HV_REGISTER_SINT0 = 0x000A0000,
1010 HV_REGISTER_SINT1 = 0x000A0001,
1011 HV_REGISTER_SINT2 = 0x000A0002,
1012 HV_REGISTER_SINT3 = 0x000A0003,
1013 HV_REGISTER_SINT4 = 0x000A0004,
1014 HV_REGISTER_SINT5 = 0x000A0005,
1015 HV_REGISTER_SINT6 = 0x000A0006,
1016 HV_REGISTER_SINT7 = 0x000A0007,
1017 HV_REGISTER_SINT8 = 0x000A0008,
1018 HV_REGISTER_SINT9 = 0x000A0009,
1019 HV_REGISTER_SINT10 = 0x000A000A,
1020 HV_REGISTER_SINT11 = 0x000A000B,
1021 HV_REGISTER_SINT12 = 0x000A000C,
1022 HV_REGISTER_SINT13 = 0x000A000D,
1023 HV_REGISTER_SINT14 = 0x000A000E,
1024 HV_REGISTER_SINT15 = 0x000A000F,
1025 HV_REGISTER_SCONTROL = 0x000A0010,
1026 HV_REGISTER_SVERSION = 0x000A0011,
1027 HV_REGISTER_SIEFP = 0x000A0012,
1028 HV_REGISTER_SIMP = 0x000A0013,
1029 HV_REGISTER_EOM = 0x000A0014,
1030 HV_REGISTER_SIRBP = 0x000A0015,
1031
1032 HV_REGISTER_NESTED_SINT0 = 0x000A1000,
1033 HV_REGISTER_NESTED_SINT1 = 0x000A1001,
1034 HV_REGISTER_NESTED_SINT2 = 0x000A1002,
1035 HV_REGISTER_NESTED_SINT3 = 0x000A1003,
1036 HV_REGISTER_NESTED_SINT4 = 0x000A1004,
1037 HV_REGISTER_NESTED_SINT5 = 0x000A1005,
1038 HV_REGISTER_NESTED_SINT6 = 0x000A1006,
1039 HV_REGISTER_NESTED_SINT7 = 0x000A1007,
1040 HV_REGISTER_NESTED_SINT8 = 0x000A1008,
1041 HV_REGISTER_NESTED_SINT9 = 0x000A1009,
1042 HV_REGISTER_NESTED_SINT10 = 0x000A100A,
1043 HV_REGISTER_NESTED_SINT11 = 0x000A100B,
1044 HV_REGISTER_NESTED_SINT12 = 0x000A100C,
1045 HV_REGISTER_NESTED_SINT13 = 0x000A100D,
1046 HV_REGISTER_NESTED_SINT14 = 0x000A100E,
1047 HV_REGISTER_NESTED_SINT15 = 0x000A100F,
1048 HV_REGISTER_NESTED_SCONTROL = 0x000A1010,
1049 HV_REGISTER_NESTED_SVERSION = 0x000A1011,
1050 HV_REGISTER_NESTED_SIFP = 0x000A1012,
1051 HV_REGISTER_NESTED_SIPP = 0x000A1013,
1052 HV_REGISTER_NESTED_EOM = 0x000A1014,
1053 HV_REGISTER_NESTED_SIRBP = 0x000a1015,
1054
1055 /* Hypervisor-defined Registers (Synthetic Timers) */
1056 HV_REGISTER_STIMER0_CONFIG = 0x000B0000,
1057 HV_REGISTER_STIMER0_COUNT = 0x000B0001,
1058
1059 /* VSM */
1060 HV_REGISTER_VSM_VP_STATUS = 0x000D0003,
1061
1062 /* Synthetic VSM registers */
1063 HV_REGISTER_VSM_CODE_PAGE_OFFSETS = 0x000D0002,
1064 HV_REGISTER_VSM_CAPABILITIES = 0x000D0006,
1065 HV_REGISTER_VSM_PARTITION_CONFIG = 0x000D0007,
1066
1067#if defined(CONFIG_X86)
1068 /* X64 Debug Registers */
1069 HV_X64_REGISTER_DR0 = 0x00050000,
1070 HV_X64_REGISTER_DR1 = 0x00050001,
1071 HV_X64_REGISTER_DR2 = 0x00050002,
1072 HV_X64_REGISTER_DR3 = 0x00050003,
1073 HV_X64_REGISTER_DR6 = 0x00050004,
1074 HV_X64_REGISTER_DR7 = 0x00050005,
1075
1076 /* X64 Cache control MSRs */
1077 HV_X64_REGISTER_MSR_MTRR_CAP = 0x0008000D,
1078 HV_X64_REGISTER_MSR_MTRR_DEF_TYPE = 0x0008000E,
1079 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 = 0x00080010,
1080 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1 = 0x00080011,
1081 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2 = 0x00080012,
1082 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3 = 0x00080013,
1083 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4 = 0x00080014,
1084 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5 = 0x00080015,
1085 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6 = 0x00080016,
1086 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7 = 0x00080017,
1087 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8 = 0x00080018,
1088 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9 = 0x00080019,
1089 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA = 0x0008001A,
1090 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB = 0x0008001B,
1091 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC = 0x0008001C,
1092 HV_X64_REGISTER_MSR_MTRR_PHYS_BASED = 0x0008001D,
1093 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE = 0x0008001E,
1094 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF = 0x0008001F,
1095 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 = 0x00080040,
1096 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1 = 0x00080041,
1097 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2 = 0x00080042,
1098 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3 = 0x00080043,
1099 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4 = 0x00080044,
1100 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5 = 0x00080045,
1101 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6 = 0x00080046,
1102 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7 = 0x00080047,
1103 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8 = 0x00080048,
1104 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9 = 0x00080049,
1105 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA = 0x0008004A,
1106 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB = 0x0008004B,
1107 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC = 0x0008004C,
1108 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD = 0x0008004D,
1109 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE = 0x0008004E,
1110 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF = 0x0008004F,
1111 HV_X64_REGISTER_MSR_MTRR_FIX64K00000 = 0x00080070,
1112 HV_X64_REGISTER_MSR_MTRR_FIX16K80000 = 0x00080071,
1113 HV_X64_REGISTER_MSR_MTRR_FIX16KA0000 = 0x00080072,
1114 HV_X64_REGISTER_MSR_MTRR_FIX4KC0000 = 0x00080073,
1115 HV_X64_REGISTER_MSR_MTRR_FIX4KC8000 = 0x00080074,
1116 HV_X64_REGISTER_MSR_MTRR_FIX4KD0000 = 0x00080075,
1117 HV_X64_REGISTER_MSR_MTRR_FIX4KD8000 = 0x00080076,
1118 HV_X64_REGISTER_MSR_MTRR_FIX4KE0000 = 0x00080077,
1119 HV_X64_REGISTER_MSR_MTRR_FIX4KE8000 = 0x00080078,
1120 HV_X64_REGISTER_MSR_MTRR_FIX4KF0000 = 0x00080079,
1121 HV_X64_REGISTER_MSR_MTRR_FIX4KF8000 = 0x0008007A,
1122
1123 HV_X64_REGISTER_REG_PAGE = 0x0009001C,
1124#elif defined(CONFIG_ARM64)
1125 HV_ARM64_REGISTER_SINT_RESERVED_INTERRUPT_ID = 0x00070001,
1126#endif
1127};
1128
1129/*
1130 * Arch compatibility regs for use with hv_set/get_register
1131 */
1132#if defined(CONFIG_X86)
1133
1134/*
1135 * To support arch-generic code calling hv_set/get_register:
1136 * - On x86, HV_MSR_ indicates an MSR accessed via rdmsrq/wrmsrq
1137 * - On ARM, HV_MSR_ indicates a VP register accessed via hypercall
1138 */
1139#define HV_MSR_CRASH_P0 (HV_X64_MSR_CRASH_P0)
1140#define HV_MSR_CRASH_P1 (HV_X64_MSR_CRASH_P1)
1141#define HV_MSR_CRASH_P2 (HV_X64_MSR_CRASH_P2)
1142#define HV_MSR_CRASH_P3 (HV_X64_MSR_CRASH_P3)
1143#define HV_MSR_CRASH_P4 (HV_X64_MSR_CRASH_P4)
1144#define HV_MSR_CRASH_CTL (HV_X64_MSR_CRASH_CTL)
1145
1146#define HV_MSR_VP_INDEX (HV_X64_MSR_VP_INDEX)
1147#define HV_MSR_TIME_REF_COUNT (HV_X64_MSR_TIME_REF_COUNT)
1148#define HV_MSR_REFERENCE_TSC (HV_X64_MSR_REFERENCE_TSC)
1149
1150#define HV_MSR_SINT0 (HV_X64_MSR_SINT0)
1151#define HV_MSR_SVERSION (HV_X64_MSR_SVERSION)
1152#define HV_MSR_SCONTROL (HV_X64_MSR_SCONTROL)
1153#define HV_MSR_SIEFP (HV_X64_MSR_SIEFP)
1154#define HV_MSR_SIMP (HV_X64_MSR_SIMP)
1155#define HV_MSR_EOM (HV_X64_MSR_EOM)
1156#define HV_MSR_SIRBP (HV_X64_MSR_SIRBP)
1157
1158#define HV_MSR_NESTED_SCONTROL (HV_X64_MSR_NESTED_SCONTROL)
1159#define HV_MSR_NESTED_SVERSION (HV_X64_MSR_NESTED_SVERSION)
1160#define HV_MSR_NESTED_SIEFP (HV_X64_MSR_NESTED_SIEFP)
1161#define HV_MSR_NESTED_SIMP (HV_X64_MSR_NESTED_SIMP)
1162#define HV_MSR_NESTED_EOM (HV_X64_MSR_NESTED_EOM)
1163#define HV_MSR_NESTED_SINT0 (HV_X64_MSR_NESTED_SINT0)
1164
1165#define HV_MSR_STIMER0_CONFIG (HV_X64_MSR_STIMER0_CONFIG)
1166#define HV_MSR_STIMER0_COUNT (HV_X64_MSR_STIMER0_COUNT)
1167
1168#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
1169
1170#define HV_MSR_CRASH_P0 (HV_REGISTER_GUEST_CRASH_P0)
1171#define HV_MSR_CRASH_P1 (HV_REGISTER_GUEST_CRASH_P1)
1172#define HV_MSR_CRASH_P2 (HV_REGISTER_GUEST_CRASH_P2)
1173#define HV_MSR_CRASH_P3 (HV_REGISTER_GUEST_CRASH_P3)
1174#define HV_MSR_CRASH_P4 (HV_REGISTER_GUEST_CRASH_P4)
1175#define HV_MSR_CRASH_CTL (HV_REGISTER_GUEST_CRASH_CTL)
1176
1177#define HV_MSR_VP_INDEX (HV_REGISTER_VP_INDEX)
1178#define HV_MSR_TIME_REF_COUNT (HV_REGISTER_TIME_REF_COUNT)
1179#define HV_MSR_REFERENCE_TSC (HV_REGISTER_REFERENCE_TSC)
1180
1181#define HV_MSR_SINT0 (HV_REGISTER_SINT0)
1182#define HV_MSR_SCONTROL (HV_REGISTER_SCONTROL)
1183#define HV_MSR_SIEFP (HV_REGISTER_SIEFP)
1184#define HV_MSR_SIMP (HV_REGISTER_SIMP)
1185#define HV_MSR_EOM (HV_REGISTER_EOM)
1186#define HV_MSR_SIRBP (HV_REGISTER_SIRBP)
1187
1188#define HV_MSR_STIMER0_CONFIG (HV_REGISTER_STIMER0_CONFIG)
1189#define HV_MSR_STIMER0_COUNT (HV_REGISTER_STIMER0_COUNT)
1190
1191#endif /* CONFIG_ARM64 */
1192
1193union hv_explicit_suspend_register {
1194 u64 as_uint64;
1195 struct {
1196 u64 suspended : 1;
1197 u64 reserved : 63;
1198 } __packed;
1199};
1200
1201union hv_intercept_suspend_register {
1202 u64 as_uint64;
1203 struct {
1204 u64 suspended : 1;
1205 u64 reserved : 63;
1206 } __packed;
1207};
1208
1209union hv_dispatch_suspend_register {
1210 u64 as_uint64;
1211 struct {
1212 u64 suspended : 1;
1213 u64 reserved : 63;
1214 } __packed;
1215};
1216
1217union hv_arm64_pending_interruption_register {
1218 u64 as_uint64;
1219 struct {
1220 u64 interruption_pending : 1;
1221 u64 interruption_type: 1;
1222 u64 reserved : 30;
1223 u64 error_code : 32;
1224 } __packed;
1225};
1226
1227union hv_arm64_interrupt_state_register {
1228 u64 as_uint64;
1229 struct {
1230 u64 interrupt_shadow : 1;
1231 u64 reserved : 63;
1232 } __packed;
1233};
1234
1235union hv_arm64_pending_synthetic_exception_event {
1236 u64 as_uint64[2];
1237 struct {
1238 u8 event_pending : 1;
1239 u8 event_type : 3;
1240 u8 reserved : 4;
1241 u8 rsvd[3];
1242 u32 exception_type;
1243 u64 context;
1244 } __packed;
1245};
1246
1247union hv_x64_interrupt_state_register {
1248 u64 as_uint64;
1249 struct {
1250 u64 interrupt_shadow : 1;
1251 u64 nmi_masked : 1;
1252 u64 reserved : 62;
1253 } __packed;
1254};
1255
1256union hv_x64_pending_interruption_register {
1257 u64 as_uint64;
1258 struct {
1259 u32 interruption_pending : 1;
1260 u32 interruption_type : 3;
1261 u32 deliver_error_code : 1;
1262 u32 instruction_length : 4;
1263 u32 nested_event : 1;
1264 u32 reserved : 6;
1265 u32 interruption_vector : 16;
1266 u32 error_code;
1267 } __packed;
1268};
1269
1270union hv_register_value {
1271 struct hv_u128 reg128;
1272 u64 reg64;
1273 u32 reg32;
1274 u16 reg16;
1275 u8 reg8;
1276
1277 struct hv_x64_segment_register segment;
1278 struct hv_x64_table_register table;
1279 union hv_explicit_suspend_register explicit_suspend;
1280 union hv_intercept_suspend_register intercept_suspend;
1281 union hv_dispatch_suspend_register dispatch_suspend;
1282#ifdef CONFIG_ARM64
1283 union hv_arm64_interrupt_state_register interrupt_state;
1284 union hv_arm64_pending_interruption_register pending_interruption;
1285#endif
1286#ifdef CONFIG_X86
1287 union hv_x64_interrupt_state_register interrupt_state;
1288 union hv_x64_pending_interruption_register pending_interruption;
1289#endif
1290 union hv_arm64_pending_synthetic_exception_event pending_synthetic_exception_event;
1291};
1292
1293/* NOTE: Linux helper struct - NOT from Hyper-V code. */
1294struct hv_output_get_vp_registers {
1295 DECLARE_FLEX_ARRAY(union hv_register_value, values);
1296};
1297
1298#if defined(CONFIG_ARM64)
1299/* HvGetVpRegisters returns an array of these output elements */
1300struct hv_get_vp_registers_output {
1301 union {
1302 struct {
1303 u32 a;
1304 u32 b;
1305 u32 c;
1306 u32 d;
1307 } as32 __packed;
1308 struct {
1309 u64 low;
1310 u64 high;
1311 } as64 __packed;
1312 };
1313};
1314
1315#endif /* CONFIG_ARM64 */
1316
1317struct hv_register_assoc {
1318 u32 name; /* enum hv_register_name */
1319 u32 reserved1;
1320 u64 reserved2;
1321 union hv_register_value value;
1322} __packed;
1323
1324struct hv_input_get_vp_registers {
1325 u64 partition_id;
1326 u32 vp_index;
1327 union hv_input_vtl input_vtl;
1328 u8 rsvd_z8;
1329 u16 rsvd_z16;
1330 u32 names[];
1331} __packed;
1332
1333struct hv_input_set_vp_registers {
1334 u64 partition_id;
1335 u32 vp_index;
1336 union hv_input_vtl input_vtl;
1337 u8 rsvd_z8;
1338 u16 rsvd_z16;
1339 struct hv_register_assoc elements[];
1340} __packed;
1341
1342#define HV_UNMAP_GPA_LARGE_PAGE 0x2
1343
1344/* HvCallSendSyntheticClusterIpi hypercall */
1345struct hv_send_ipi { /* HV_INPUT_SEND_SYNTHETIC_CLUSTER_IPI */
1346 u32 vector;
1347 u32 reserved;
1348 u64 cpu_mask;
1349} __packed;
1350
1351#define HV_VTL_MASK GENMASK(3, 0)
1352
1353/* Hyper-V memory host visibility */
1354enum hv_mem_host_visibility {
1355 VMBUS_PAGE_NOT_VISIBLE = 0,
1356 VMBUS_PAGE_VISIBLE_READ_ONLY = 1,
1357 VMBUS_PAGE_VISIBLE_READ_WRITE = 3
1358};
1359
1360/* HvCallModifySparseGpaPageHostVisibility hypercall */
1361#define HV_MAX_MODIFY_GPA_REP_COUNT ((HV_HYP_PAGE_SIZE / sizeof(u64)) - 2)
1362struct hv_gpa_range_for_visibility {
1363 u64 partition_id;
1364 u32 host_visibility : 2;
1365 u32 reserved0 : 30;
1366 u32 reserved1;
1367 u64 gpa_page_list[HV_MAX_MODIFY_GPA_REP_COUNT];
1368} __packed;
1369
1370#if defined(CONFIG_X86)
1371union hv_msi_address_register { /* HV_MSI_ADDRESS */
1372 u32 as_uint32;
1373 struct {
1374 u32 reserved1 : 2;
1375 u32 destination_mode : 1;
1376 u32 redirection_hint : 1;
1377 u32 reserved2 : 8;
1378 u32 destination_id : 8;
1379 u32 msi_base : 12;
1380 };
1381} __packed;
1382
1383union hv_msi_data_register { /* HV_MSI_ENTRY.Data */
1384 u32 as_uint32;
1385 struct {
1386 u32 vector : 8;
1387 u32 delivery_mode : 3;
1388 u32 reserved1 : 3;
1389 u32 level_assert : 1;
1390 u32 trigger_mode : 1;
1391 u32 reserved2 : 16;
1392 };
1393} __packed;
1394
1395union hv_msi_entry { /* HV_MSI_ENTRY */
1396
1397 u64 as_uint64;
1398 struct {
1399 union hv_msi_address_register address;
1400 union hv_msi_data_register data;
1401 } __packed;
1402};
1403
1404#elif defined(CONFIG_ARM64) /* CONFIG_X86 */
1405
1406union hv_msi_entry {
1407 u64 as_uint64[2];
1408 struct {
1409 u64 address;
1410 u32 data;
1411 u32 reserved;
1412 } __packed;
1413};
1414#endif /* CONFIG_ARM64 */
1415
1416union hv_ioapic_rte {
1417 u64 as_uint64;
1418
1419 struct {
1420 u32 vector : 8;
1421 u32 delivery_mode : 3;
1422 u32 destination_mode : 1;
1423 u32 delivery_status : 1;
1424 u32 interrupt_polarity : 1;
1425 u32 remote_irr : 1;
1426 u32 trigger_mode : 1;
1427 u32 interrupt_mask : 1;
1428 u32 reserved1 : 15;
1429
1430 u32 reserved2 : 24;
1431 u32 destination_id : 8;
1432 };
1433
1434 struct {
1435 u32 low_uint32;
1436 u32 high_uint32;
1437 };
1438} __packed;
1439
1440enum hv_interrupt_source { /* HV_INTERRUPT_SOURCE */
1441 HV_INTERRUPT_SOURCE_MSI = 1, /* MSI and MSI-X */
1442 HV_INTERRUPT_SOURCE_IOAPIC,
1443};
1444
1445struct hv_interrupt_entry { /* HV_INTERRUPT_ENTRY */
1446 u32 source;
1447 u32 reserved1;
1448 union {
1449 union hv_msi_entry msi_entry;
1450 union hv_ioapic_rte ioapic_rte;
1451 };
1452} __packed;
1453
1454#define HV_DEVICE_INTERRUPT_TARGET_MULTICAST 1
1455#define HV_DEVICE_INTERRUPT_TARGET_PROCESSOR_SET 2
1456
1457struct hv_device_interrupt_target { /* HV_DEVICE_INTERRUPT_TARGET */
1458 u32 vector;
1459 u32 flags; /* HV_DEVICE_INTERRUPT_TARGET_* above */
1460 union {
1461 u64 vp_mask;
1462 struct hv_vpset vp_set;
1463 };
1464} __packed;
1465
1466struct hv_retarget_device_interrupt { /* HV_INPUT_RETARGET_DEVICE_INTERRUPT */
1467 u64 partition_id; /* use "self" */
1468 u64 device_id;
1469 struct hv_interrupt_entry int_entry;
1470 u64 reserved2;
1471 struct hv_device_interrupt_target int_target;
1472} __packed __aligned(8);
1473
1474enum hv_intercept_type {
1475#if defined(CONFIG_X86)
1476 HV_INTERCEPT_TYPE_X64_IO_PORT = 0x00000000,
1477 HV_INTERCEPT_TYPE_X64_MSR = 0x00000001,
1478 HV_INTERCEPT_TYPE_X64_CPUID = 0x00000002,
1479#endif
1480 HV_INTERCEPT_TYPE_EXCEPTION = 0x00000003,
1481 /* Used to be HV_INTERCEPT_TYPE_REGISTER */
1482 HV_INTERCEPT_TYPE_RESERVED0 = 0x00000004,
1483 HV_INTERCEPT_TYPE_MMIO = 0x00000005,
1484#if defined(CONFIG_X86)
1485 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0x00000006,
1486 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0x00000007,
1487#endif
1488 HV_INTERCEPT_TYPE_HYPERCALL = 0x00000008,
1489#if defined(CONFIG_X86)
1490 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0x00000009,
1491 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0x0000000A,
1492 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0x0000000B,
1493 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0x0000000C,
1494#endif
1495 HV_INTERCEPT_TYPE_MAX,
1496 HV_INTERCEPT_TYPE_INVALID = 0xFFFFFFFF,
1497};
1498
1499union hv_intercept_parameters {
1500 /* HV_INTERCEPT_PARAMETERS is defined to be an 8-byte field. */
1501 u64 as_uint64;
1502#if defined(CONFIG_X86)
1503 /* HV_INTERCEPT_TYPE_X64_IO_PORT */
1504 u16 io_port;
1505 /* HV_INTERCEPT_TYPE_X64_CPUID */
1506 u32 cpuid_index;
1507 /* HV_INTERCEPT_TYPE_X64_APIC_WRITE */
1508 u32 apic_write_mask;
1509 /* HV_INTERCEPT_TYPE_EXCEPTION */
1510 u16 exception_vector;
1511 /* HV_INTERCEPT_TYPE_X64_MSR_INDEX */
1512 u32 msr_index;
1513#endif
1514 /* N.B. Other intercept types do not have any parameters. */
1515};
1516
1517/* Data structures for HVCALL_MMIO_READ and HVCALL_MMIO_WRITE */
1518#define HV_HYPERCALL_MMIO_MAX_DATA_LENGTH 64
1519
1520struct hv_mmio_read_input { /* HV_INPUT_MEMORY_MAPPED_IO_READ */
1521 u64 gpa;
1522 u32 size;
1523 u32 reserved;
1524} __packed;
1525
1526struct hv_mmio_read_output {
1527 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH];
1528} __packed;
1529
1530struct hv_mmio_write_input {
1531 u64 gpa;
1532 u32 size;
1533 u32 reserved;
1534 u8 data[HV_HYPERCALL_MMIO_MAX_DATA_LENGTH];
1535} __packed;
1536
1537enum hv_intercept_access_type {
1538 HV_INTERCEPT_ACCESS_READ = 0,
1539 HV_INTERCEPT_ACCESS_WRITE = 1,
1540 HV_INTERCEPT_ACCESS_EXECUTE = 2
1541};
1542
1543#endif /* _HV_HVGDK_MINI_H */