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| 2 | |
| 3 | * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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| 4 |
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| 5 |
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| 6 | #ifndef __SOC_QCOM_TCS_H__
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| 7 | #define __SOC_QCOM_TCS_H__
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| 8 |
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| 9 | #include <linux/bitfield.h>
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| 10 | #include <linux/bits.h>
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| 11 |
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| 12 | #define MAX_RPMH_PAYLOAD 16
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| 13 |
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| 14 | |
| 15 | * rpmh_state: state for the request
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| 16 | *
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| 17 | * RPMH_SLEEP_STATE: State of the resource when the processor subsystem
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| 18 | * is powered down. There is no client using the
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| 19 | * resource actively.
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| 20 | * RPMH_WAKE_ONLY_STATE: Resume resource state to the value previously
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| 21 | * requested before the processor was powered down.
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| 22 | * RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
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| 23 | * is aggregated immediately.
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| 24 |
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| 25 | enum rpmh_state {
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| 26 | RPMH_SLEEP_STATE,
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| 27 | RPMH_WAKE_ONLY_STATE,
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| 28 | RPMH_ACTIVE_ONLY_STATE,
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| 29 | };
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| 30 |
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| 31 | |
| 32 | * struct tcs_cmd: an individual request to RPMH.
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| 33 | *
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| 34 | * @addr: the address of the resource slv_id:18:16 | offset:0:15
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| 35 | * @data: the resource state request
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| 36 | * @wait: ensure that this command is complete before returning.
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| 37 | * Setting "wait" here only makes sense during rpmh_write_batch() for
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| 38 | * active-only transfers, this is because:
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| 39 | * rpmh_write() - Always waits.
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| 40 | * (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
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| 41 | * rpmh_write_async() - Never waits.
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| 42 | * (There's no request completion callback)
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| 43 |
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| 44 | struct tcs_cmd {
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| 45 | u32 addr;
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| 46 | u32 data;
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| 47 | u32 wait;
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| 48 | };
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| 49 |
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| 50 | |
| 51 | * struct tcs_request: A set of tcs_cmds sent together in a TCS
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| 52 | *
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| 53 | * @state: state for the request.
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| 54 | * @is_read: set for read only requests
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| 55 | * @wait_for_compl: wait until we get a response from the h/w accelerator
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| 56 | * (same as setting cmd->wait for all commands in the request)
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| 57 | * @num_cmds: the number of @cmds in this request
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| 58 | * @cmds: an array of tcs_cmds
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| 59 |
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| 60 | struct tcs_request {
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| 61 | enum rpmh_state state;
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| 62 | bool is_read;
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| 63 | u32 wait_for_compl;
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| 64 | u32 num_cmds;
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| 65 | struct tcs_cmd *cmds;
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| 66 | };
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| 67 |
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| 68 | #define BCM_TCS_CMD_COMMIT_MASK BIT(30)
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| 69 | #define BCM_TCS_CMD_VALID_MASK BIT(29)
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| 70 | #define BCM_TCS_CMD_VOTE_MASK GENMASK(13, 0)
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| 71 | #define BCM_TCS_CMD_VOTE_Y_MASK GENMASK(13, 0)
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| 72 | #define BCM_TCS_CMD_VOTE_X_MASK GENMASK(27, 14)
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| 73 |
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| 74 |
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| 75 | #define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
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| 76 | (u32_encode_bits(commit, BCM_TCS_CMD_COMMIT_MASK) | \
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| 77 | u32_encode_bits(valid, BCM_TCS_CMD_VALID_MASK) | \
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| 78 | u32_encode_bits(vote_x, BCM_TCS_CMD_VOTE_X_MASK) | \
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| 79 | u32_encode_bits(vote_y, BCM_TCS_CMD_VOTE_Y_MASK))
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| 80 |
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| 81 | #endif
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