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| 2 | |
| 3 | * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved.
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| 4 |
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| 5 |
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| 6 | #ifndef __SOC_TEGRA_FUSE_H__
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| 7 | #define __SOC_TEGRA_FUSE_H__
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| 8 |
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| 9 | #include <linux/types.h>
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| 10 |
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| 11 | #define TEGRA20 0x20
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| 12 | #define TEGRA30 0x30
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| 13 | #define TEGRA114 0x35
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| 14 | #define TEGRA124 0x40
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| 15 | #define TEGRA132 0x13
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| 16 | #define TEGRA210 0x21
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| 17 | #define TEGRA186 0x18
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| 18 | #define TEGRA194 0x19
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| 19 | #define TEGRA234 0x23
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| 20 | #define TEGRA241 0x24
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| 21 | #define TEGRA264 0x26
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| 22 |
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| 23 | #define TEGRA_FUSE_SKU_CALIB_0 0xf0
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| 24 | #define TEGRA30_FUSE_SATA_CALIB 0x124
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| 25 | #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
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| 26 |
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| 27 | #ifndef __ASSEMBLER__
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| 28 |
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| 29 | enum tegra_revision {
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| 30 | TEGRA_REVISION_UNKNOWN = 0,
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| 31 | TEGRA_REVISION_A01,
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| 32 | TEGRA_REVISION_A02,
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| 33 | TEGRA_REVISION_A03,
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| 34 | TEGRA_REVISION_A03p,
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| 35 | TEGRA_REVISION_A04,
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| 36 | TEGRA_REVISION_MAX,
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| 37 | };
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| 38 |
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| 39 | enum tegra_platform {
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| 40 | TEGRA_PLATFORM_SILICON = 0,
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| 41 | TEGRA_PLATFORM_QT,
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| 42 | TEGRA_PLATFORM_SYSTEM_FPGA,
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| 43 | TEGRA_PLATFORM_UNIT_FPGA,
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| 44 | TEGRA_PLATFORM_ASIM_QT,
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| 45 | TEGRA_PLATFORM_ASIM_LINSIM,
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| 46 | TEGRA_PLATFORM_DSIM_ASIM_LINSIM,
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| 47 | TEGRA_PLATFORM_VERIFICATION_SIMULATION,
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| 48 | TEGRA_PLATFORM_VDK,
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| 49 | TEGRA_PLATFORM_VSP,
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| 50 | TEGRA_PLATFORM_MAX,
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| 51 | };
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| 52 |
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| 53 | struct tegra_sku_info {
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| 54 | int sku_id;
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| 55 | int cpu_process_id;
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| 56 | int cpu_speedo_id;
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| 57 | int cpu_speedo_value;
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| 58 | int cpu_iddq_value;
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| 59 | int soc_process_id;
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| 60 | int soc_speedo_id;
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| 61 | int soc_speedo_value;
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| 62 | int gpu_process_id;
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| 63 | int gpu_speedo_id;
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| 64 | int gpu_speedo_value;
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| 65 | enum tegra_revision revision;
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| 66 | enum tegra_platform platform;
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| 67 | };
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| 68 |
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| 69 | #ifdef CONFIG_ARCH_TEGRA
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| 70 | extern struct tegra_sku_info tegra_sku_info;
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| 71 | u32 tegra_read_straps(void);
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| 72 | u32 tegra_read_ram_code(void);
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| 73 | int tegra_fuse_readl(unsigned long offset, u32 *value);
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| 74 | u32 tegra_read_chipid(void);
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| 75 | u8 tegra_get_chip_id(void);
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| 76 | u8 tegra_get_platform(void);
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| 77 | bool tegra_is_silicon(void);
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| 78 | int tegra194_miscreg_mask_serror(void);
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| 79 | #else
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| 80 | static struct tegra_sku_info tegra_sku_info __maybe_unused;
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| 81 |
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| 82 | static inline u32 tegra_read_straps(void)
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| 83 | {
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| 84 | return 0;
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| 85 | }
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| 86 |
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| 87 | static inline u32 tegra_read_ram_code(void)
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| 88 | {
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| 89 | return 0;
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| 90 | }
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| 91 |
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| 92 | static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
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| 93 | {
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| 94 | return -ENODEV;
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| 95 | }
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| 96 |
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| 97 | static inline u32 tegra_read_chipid(void)
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| 98 | {
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| 99 | return 0;
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| 100 | }
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| 101 |
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| 102 | static inline u8 tegra_get_chip_id(void)
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| 103 | {
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| 104 | return 0;
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| 105 | }
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| 106 |
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| 107 | static inline u8 tegra_get_platform(void)
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| 108 | {
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| 109 | return 0;
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| 110 | }
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| 111 |
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| 112 | static inline bool tegra_is_silicon(void)
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| 113 | {
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| 114 | return false;
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| 115 | }
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| 116 |
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| 117 | static inline int tegra194_miscreg_mask_serror(void)
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| 118 | {
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| 119 | return false;
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| 120 | }
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| 121 | #endif
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| 122 |
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| 123 | struct device *tegra_soc_device_register(void);
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| 124 |
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| 125 | #endif
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| 126 |
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| 127 | #endif
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