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1/*
2 * Copyright 2013 Red Hat
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24#ifndef VIRTGPU_DRM_H
25#define VIRTGPU_DRM_H
26
27#include "drm.h"
28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
33/* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
35 *
36 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
37 * compatibility Keep fields aligned to their size
38 */
39
40#define DRM_VIRTGPU_MAP 0x01
41#define DRM_VIRTGPU_EXECBUFFER 0x02
42#define DRM_VIRTGPU_GETPARAM 0x03
43#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
44#define DRM_VIRTGPU_RESOURCE_INFO 0x05
45#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
46#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
47#define DRM_VIRTGPU_WAIT 0x08
48#define DRM_VIRTGPU_GET_CAPS 0x09
49#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
50#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
51
52#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
53#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
54#define VIRTGPU_EXECBUF_RING_IDX 0x04
55#define VIRTGPU_EXECBUF_FLAGS (\
56 VIRTGPU_EXECBUF_FENCE_FD_IN |\
57 VIRTGPU_EXECBUF_FENCE_FD_OUT |\
58 VIRTGPU_EXECBUF_RING_IDX |\
59 0)
60
61struct drm_virtgpu_map {
62 __u64 offset; /* use for mmap system call */
63 __u32 handle;
64 __u32 pad;
65};
66
67#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
68#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
69 VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
70 0)
71struct drm_virtgpu_execbuffer_syncobj {
72 __u32 handle;
73 __u32 flags;
74 __u64 point;
75};
76
77/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
78struct drm_virtgpu_execbuffer {
79 __u32 flags;
80 __u32 size;
81 __u64 command; /* void* */
82 __u64 bo_handles;
83 __u32 num_bo_handles;
84 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
85 __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
86 __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
87 __u32 num_in_syncobjs;
88 __u32 num_out_syncobjs;
89 __u64 in_syncobjs;
90 __u64 out_syncobjs;
91};
92
93#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
94#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
95#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
96#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
97#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
98#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
99#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
100#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */
101#define VIRTGPU_PARAM_BLOB_ALIGNMENT 9 /* Device alignment requirements for blobs */
102
103struct drm_virtgpu_getparam {
104 __u64 param;
105 __u64 value;
106};
107
108/* NO_BO flags? NO resource flag? */
109/* resource flag for y_0_top */
110struct drm_virtgpu_resource_create {
111 __u32 target;
112 __u32 format;
113 __u32 bind;
114 __u32 width;
115 __u32 height;
116 __u32 depth;
117 __u32 array_size;
118 __u32 last_level;
119 __u32 nr_samples;
120 __u32 flags;
121 __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
122 __u32 res_handle; /* returned by kernel */
123 __u32 size; /* validate transfer in the host */
124 __u32 stride; /* validate transfer in the host */
125};
126
127struct drm_virtgpu_resource_info {
128 __u32 bo_handle;
129 __u32 res_handle;
130 __u32 size;
131 __u32 blob_mem;
132};
133
134struct drm_virtgpu_3d_box {
135 __u32 x;
136 __u32 y;
137 __u32 z;
138 __u32 w;
139 __u32 h;
140 __u32 d;
141};
142
143struct drm_virtgpu_3d_transfer_to_host {
144 __u32 bo_handle;
145 struct drm_virtgpu_3d_box box;
146 __u32 level;
147 __u32 offset;
148 __u32 stride;
149 __u32 layer_stride;
150};
151
152struct drm_virtgpu_3d_transfer_from_host {
153 __u32 bo_handle;
154 struct drm_virtgpu_3d_box box;
155 __u32 level;
156 __u32 offset;
157 __u32 stride;
158 __u32 layer_stride;
159};
160
161#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
162struct drm_virtgpu_3d_wait {
163 __u32 handle; /* 0 is an invalid handle */
164 __u32 flags;
165};
166
167#define VIRTGPU_DRM_CAPSET_VIRGL 1
168#define VIRTGPU_DRM_CAPSET_VIRGL2 2
169#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3
170#define VIRTGPU_DRM_CAPSET_VENUS 4
171#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5
172#define VIRTGPU_DRM_CAPSET_DRM 6
173struct drm_virtgpu_get_caps {
174 __u32 cap_set_id;
175 __u32 cap_set_ver;
176 __u64 addr;
177 __u32 size;
178 __u32 pad;
179};
180
181struct drm_virtgpu_resource_create_blob {
182#define VIRTGPU_BLOB_MEM_GUEST 0x0001
183#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
184#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
185
186#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
187#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
188#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
189 /* zero is invalid blob_mem */
190 __u32 blob_mem;
191 __u32 blob_flags;
192 __u32 bo_handle;
193 __u32 res_handle;
194 __u64 size;
195
196 /*
197 * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
198 * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
199 */
200 __u32 pad;
201 __u32 cmd_size;
202 __u64 cmd;
203 __u64 blob_id;
204
205#define DRM_VIRTGPU_BLOB_FLAG_HINT_DEFER_MAPPING 0x0001
206 __u32 blob_hints;
207 __u32 pad2;
208};
209
210#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
211#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
212#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
213#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004
214struct drm_virtgpu_context_set_param {
215 __u64 param;
216 __u64 value;
217};
218
219struct drm_virtgpu_context_init {
220 __u32 num_params;
221 __u32 pad;
222
223 /* pointer to drm_virtgpu_context_set_param array */
224 __u64 ctx_set_params;
225};
226
227/*
228 * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
229 * effect. The event size is sizeof(drm_event), since there is no additional
230 * payload.
231 */
232#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
233
234#define DRM_IOCTL_VIRTGPU_MAP \
235 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
236
237#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
238 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
239 struct drm_virtgpu_execbuffer)
240
241#define DRM_IOCTL_VIRTGPU_GETPARAM \
242 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
243 struct drm_virtgpu_getparam)
244
245#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
246 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
247 struct drm_virtgpu_resource_create)
248
249#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
250 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
251 struct drm_virtgpu_resource_info)
252
253#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
254 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
255 struct drm_virtgpu_3d_transfer_from_host)
256
257#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
258 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
259 struct drm_virtgpu_3d_transfer_to_host)
260
261#define DRM_IOCTL_VIRTGPU_WAIT \
262 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
263 struct drm_virtgpu_3d_wait)
264
265#define DRM_IOCTL_VIRTGPU_GET_CAPS \
266 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
267 struct drm_virtgpu_get_caps)
268
269#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
270 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
271 struct drm_virtgpu_resource_create_blob)
272
273#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
274 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
275 struct drm_virtgpu_context_init)
276
277#if defined(__cplusplus)
278}
279#endif
280
281#endif