projects/linux·blob master · refs

1308 lines · 34.3 KiB

1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Implementation of primary alsa driver code base for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation
7 *
8 * Copyright (c) 2004 Takashi Iwai <[email protected]>
9 * PeiSen Hou <[email protected]>
10 */
11
12#include <linux/clocksource.h>
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pm_runtime.h>
18#include <linux/slab.h>
19
20#ifdef CONFIG_X86
21/* for art-tsc conversion */
22#include <asm/tsc.h>
23#endif
24
25#include <sound/core.h>
26#include <sound/initval.h>
27#include <sound/pcm_params.h>
28#include "hda_controller.h"
29#include "hda_local.h"
30
31#define CREATE_TRACE_POINTS
32#include "controller_trace.h"
33
34/* DSP lock helpers */
35#ifdef CONFIG_SND_HDA_DSP_LOADER
36#define guard_dsp_lock(dev) guard(snd_hdac_dsp_lock)(azx_stream(dev))
37#else
38#define guard_dsp_lock(dev) do {} while (0)
39#endif
40#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
41
42/* assign a stream for the PCM */
43static inline struct azx_dev *
44azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
45{
46 struct hdac_stream *s;
47
48 s = snd_hdac_stream_assign(azx_bus(chip), substream);
49 if (!s)
50 return NULL;
51 return stream_to_azx_dev(s);
52}
53
54/* release the assigned stream */
55static inline void azx_release_device(struct azx_dev *azx_dev)
56{
57 snd_hdac_stream_release(azx_stream(azx_dev));
58}
59
60static inline struct hda_pcm_stream *
61to_hda_pcm_stream(struct snd_pcm_substream *substream)
62{
63 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
64 return &apcm->info->stream[substream->stream];
65}
66
67static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
68 u64 nsec)
69{
70 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
71 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
72 u64 codec_frames, codec_nsecs;
73
74 if (!hinfo->ops.get_delay)
75 return nsec;
76
77 codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
78 codec_nsecs = div_u64(codec_frames * 1000000000LL,
79 substream->runtime->rate);
80
81 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
82 return nsec + codec_nsecs;
83
84 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
85}
86
87/*
88 * PCM ops
89 */
90
91static int azx_pcm_close(struct snd_pcm_substream *substream)
92{
93 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
94 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
95 struct azx *chip = apcm->chip;
96 struct azx_dev *azx_dev = get_azx_dev(substream);
97
98 trace_azx_pcm_close(chip, azx_dev);
99 scoped_guard(mutex, &chip->open_mutex) {
100 if (chip->ops->pcm_close)
101 chip->ops->pcm_close(chip, azx_dev);
102 azx_release_device(azx_dev);
103 if (hinfo->ops.close)
104 hinfo->ops.close(hinfo, apcm->codec, substream);
105 snd_hda_power_down(apcm->codec);
106 }
107 snd_hda_codec_pcm_put(apcm->info);
108 return 0;
109}
110
111static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
112 struct snd_pcm_hw_params *hw_params)
113{
114 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
115 struct azx *chip = apcm->chip;
116 struct azx_dev *azx_dev = get_azx_dev(substream);
117 struct hdac_stream *hdas = azx_stream(azx_dev);
118
119 trace_azx_pcm_hw_params(chip, azx_dev);
120 guard_dsp_lock(azx_dev);
121 if (dsp_is_locked(azx_dev))
122 return -EBUSY;
123
124 /* Set up BDLEs here, return -ENOMEM if too many BDLEs are required */
125 hdas->bufsize = params_buffer_bytes(hw_params);
126 hdas->period_bytes = params_period_bytes(hw_params);
127 hdas->format_val = 0;
128 hdas->no_period_wakeup =
129 (hw_params->info & SNDRV_PCM_INFO_NO_PERIOD_WAKEUP) &&
130 (hw_params->flags & SNDRV_PCM_HW_PARAMS_NO_PERIOD_WAKEUP);
131 if (snd_hdac_stream_setup_periods(hdas) < 0)
132 return -ENOMEM;
133
134 return 0;
135}
136
137static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
138{
139 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
140 struct azx_dev *azx_dev = get_azx_dev(substream);
141 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
142
143 /* reset BDL address */
144 guard_dsp_lock(azx_dev);
145 if (!dsp_is_locked(azx_dev))
146 snd_hdac_stream_cleanup(azx_stream(azx_dev));
147
148 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
149
150 azx_stream(azx_dev)->prepared = 0;
151 return 0;
152}
153
154static int azx_pcm_prepare(struct snd_pcm_substream *substream)
155{
156 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
157 struct azx *chip = apcm->chip;
158 struct azx_dev *azx_dev = get_azx_dev(substream);
159 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
160 struct snd_pcm_runtime *runtime = substream->runtime;
161 unsigned int format_val, stream_tag, bits;
162 int err;
163 struct hda_spdif_out *spdif =
164 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
165 unsigned short ctls = spdif ? spdif->ctls : 0;
166
167 trace_azx_pcm_prepare(chip, azx_dev);
168 guard_dsp_lock(azx_dev);
169 if (dsp_is_locked(azx_dev))
170 return -EBUSY;
171
172 snd_hdac_stream_reset(azx_stream(azx_dev));
173 bits = snd_hdac_stream_format_bits(runtime->format, SNDRV_PCM_SUBFORMAT_STD, hinfo->maxbps);
174
175 format_val = snd_hdac_spdif_stream_format(runtime->channels, bits, runtime->rate, ctls);
176 if (!format_val) {
177 dev_err(chip->card->dev,
178 "invalid format_val, rate=%d, ch=%d, format=%d\n",
179 runtime->rate, runtime->channels, runtime->format);
180 return -EINVAL;
181 }
182
183 err = snd_hdac_stream_set_params(azx_stream(azx_dev), format_val);
184 if (err < 0)
185 return err;
186
187 snd_hdac_stream_setup(azx_stream(azx_dev), false);
188
189 stream_tag = azx_dev->core.stream_tag;
190 /* CA-IBG chips need the playback stream starting from 1 */
191 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
192 stream_tag > chip->capture_streams)
193 stream_tag -= chip->capture_streams;
194 err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
195 azx_dev->core.format_val, substream);
196 if (err < 0)
197 return err;
198
199 azx_stream(azx_dev)->prepared = 1;
200 return 0;
201}
202
203static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
204{
205 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
206 struct azx *chip = apcm->chip;
207 struct hdac_bus *bus = azx_bus(chip);
208 struct azx_dev *azx_dev;
209 struct snd_pcm_substream *s;
210 struct hdac_stream *hstr;
211 bool start;
212 int sbits = 0;
213 int sync_reg;
214
215 azx_dev = get_azx_dev(substream);
216 trace_azx_pcm_trigger(chip, azx_dev, cmd);
217
218 hstr = azx_stream(azx_dev);
219 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
220 sync_reg = AZX_REG_OLD_SSYNC;
221 else
222 sync_reg = AZX_REG_SSYNC;
223
224 if (dsp_is_locked(azx_dev) || !hstr->prepared)
225 return -EPIPE;
226
227 switch (cmd) {
228 case SNDRV_PCM_TRIGGER_START:
229 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
230 case SNDRV_PCM_TRIGGER_RESUME:
231 start = true;
232 break;
233 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
234 case SNDRV_PCM_TRIGGER_SUSPEND:
235 case SNDRV_PCM_TRIGGER_STOP:
236 start = false;
237 break;
238 default:
239 return -EINVAL;
240 }
241
242 snd_pcm_group_for_each_entry(s, substream) {
243 if (s->pcm->card != substream->pcm->card)
244 continue;
245 azx_dev = get_azx_dev(s);
246 sbits |= 1 << azx_dev->core.index;
247 snd_pcm_trigger_done(s, substream);
248 }
249
250 scoped_guard(spinlock, &bus->reg_lock) {
251 /* first, set SYNC bits of corresponding streams */
252 snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
253
254 snd_pcm_group_for_each_entry(s, substream) {
255 if (s->pcm->card != substream->pcm->card)
256 continue;
257 azx_dev = get_azx_dev(s);
258 if (start) {
259 azx_dev->insufficient = 1;
260 snd_hdac_stream_start(azx_stream(azx_dev));
261 } else {
262 snd_hdac_stream_stop(azx_stream(azx_dev));
263 }
264 }
265 }
266
267 snd_hdac_stream_sync(hstr, start, sbits);
268
269 guard(spinlock)(&bus->reg_lock);
270 /* reset SYNC bits */
271 snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
272 snd_hdac_stream_timecounter_init(hstr, sbits, start);
273 return 0;
274}
275
276unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
277{
278 return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
279}
280EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
281
282unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
283{
284 return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
285}
286EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
287
288unsigned int azx_get_position(struct azx *chip,
289 struct azx_dev *azx_dev)
290{
291 struct snd_pcm_substream *substream = azx_dev->core.substream;
292 unsigned int pos;
293 int stream = substream->stream;
294 int delay = 0;
295
296 if (chip->get_position[stream])
297 pos = chip->get_position[stream](chip, azx_dev);
298 else /* use the position buffer as default */
299 pos = azx_get_pos_posbuf(chip, azx_dev);
300
301 if (pos >= azx_dev->core.bufsize)
302 pos = 0;
303
304 if (substream->runtime) {
305 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
306 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
307
308 if (chip->get_delay[stream])
309 delay += chip->get_delay[stream](chip, azx_dev, pos);
310 if (hinfo->ops.get_delay)
311 delay += hinfo->ops.get_delay(hinfo, apcm->codec,
312 substream);
313 substream->runtime->delay = delay;
314 }
315
316 trace_azx_get_position(chip, azx_dev, pos, delay);
317 return pos;
318}
319EXPORT_SYMBOL_GPL(azx_get_position);
320
321static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
322{
323 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
324 struct azx *chip = apcm->chip;
325 struct azx_dev *azx_dev = get_azx_dev(substream);
326 return bytes_to_frames(substream->runtime,
327 azx_get_position(chip, azx_dev));
328}
329
330/*
331 * azx_scale64: Scale base by mult/div while not overflowing sanely
332 *
333 * Derived from scale64_check_overflow in kernel/time/timekeeping.c
334 *
335 * The tmestamps for a 48Khz stream can overflow after (2^64/10^9)/48K which
336 * is about 384307 ie ~4.5 days.
337 *
338 * This scales the calculation so that overflow will happen but after 2^64 /
339 * 48000 secs, which is pretty large!
340 *
341 * In caln below:
342 * base may overflow, but since there isn’t any additional division
343 * performed on base it’s OK
344 * rem can’t overflow because both are 32-bit values
345 */
346
347#ifdef CONFIG_X86
348static u64 azx_scale64(u64 base, u32 num, u32 den)
349{
350 u64 rem;
351
352 rem = do_div(base, den);
353
354 base *= num;
355 rem *= num;
356
357 do_div(rem, den);
358
359 return base + rem;
360}
361
362static int azx_get_sync_time(ktime_t *device,
363 struct system_counterval_t *system, void *ctx)
364{
365 struct snd_pcm_substream *substream = ctx;
366 struct azx_dev *azx_dev = get_azx_dev(substream);
367 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
368 struct azx *chip = apcm->chip;
369 struct snd_pcm_runtime *runtime;
370 u64 ll_counter, ll_counter_l, ll_counter_h;
371 u64 tsc_counter, tsc_counter_l, tsc_counter_h;
372 u32 wallclk_ctr, wallclk_cycles;
373 bool direction;
374 u32 dma_select;
375 u32 timeout;
376 u32 retry_count = 0;
377
378 runtime = substream->runtime;
379
380 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
381 direction = 1;
382 else
383 direction = 0;
384
385 /* 0th stream tag is not used, so DMA ch 0 is for 1st stream tag */
386 do {
387 timeout = 100;
388 dma_select = (direction << GTSCC_CDMAS_DMA_DIR_SHIFT) |
389 (azx_dev->core.stream_tag - 1);
390 snd_hdac_chip_writel(azx_bus(chip), GTSCC, dma_select);
391
392 /* Enable the capture */
393 snd_hdac_chip_updatel(azx_bus(chip), GTSCC, 0, GTSCC_TSCCI_MASK);
394
395 while (timeout) {
396 if (snd_hdac_chip_readl(azx_bus(chip), GTSCC) &
397 GTSCC_TSCCD_MASK)
398 break;
399
400 timeout--;
401 }
402
403 if (!timeout) {
404 dev_err(chip->card->dev, "GTSCC capture Timedout!\n");
405 return -EIO;
406 }
407
408 /* Read wall clock counter */
409 wallclk_ctr = snd_hdac_chip_readl(azx_bus(chip), WALFCC);
410
411 /* Read TSC counter */
412 tsc_counter_l = snd_hdac_chip_readl(azx_bus(chip), TSCCL);
413 tsc_counter_h = snd_hdac_chip_readl(azx_bus(chip), TSCCU);
414
415 /* Read Link counter */
416 ll_counter_l = snd_hdac_chip_readl(azx_bus(chip), LLPCL);
417 ll_counter_h = snd_hdac_chip_readl(azx_bus(chip), LLPCU);
418
419 /* Ack: registers read done */
420 snd_hdac_chip_writel(azx_bus(chip), GTSCC, GTSCC_TSCCD_SHIFT);
421
422 tsc_counter = (tsc_counter_h << TSCCU_CCU_SHIFT) |
423 tsc_counter_l;
424
425 ll_counter = (ll_counter_h << LLPC_CCU_SHIFT) | ll_counter_l;
426 wallclk_cycles = wallclk_ctr & WALFCC_CIF_MASK;
427
428 /*
429 * An error occurs near frame "rollover". The clocks in
430 * frame value indicates whether this error may have
431 * occurred. Here we use the value of 10 i.e.,
432 * HDA_MAX_CYCLE_OFFSET
433 */
434 if (wallclk_cycles < HDA_MAX_CYCLE_VALUE - HDA_MAX_CYCLE_OFFSET
435 && wallclk_cycles > HDA_MAX_CYCLE_OFFSET)
436 break;
437
438 /*
439 * Sleep before we read again, else we may again get
440 * value near to MAX_CYCLE. Try to sleep for different
441 * amount of time so we dont hit the same number again
442 */
443 udelay(retry_count++);
444
445 } while (retry_count != HDA_MAX_CYCLE_READ_RETRY);
446
447 if (retry_count == HDA_MAX_CYCLE_READ_RETRY) {
448 dev_err_ratelimited(chip->card->dev,
449 "Error in WALFCC cycle count\n");
450 return -EIO;
451 }
452
453 *device = ns_to_ktime(azx_scale64(ll_counter,
454 NSEC_PER_SEC, runtime->rate));
455 *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) /
456 ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate));
457
458 system->cycles = tsc_counter;
459 system->cs_id = CSID_X86_ART;
460
461 return 0;
462}
463
464#else
465static int azx_get_sync_time(ktime_t *device,
466 struct system_counterval_t *system, void *ctx)
467{
468 return -ENXIO;
469}
470#endif
471
472static int azx_get_crosststamp(struct snd_pcm_substream *substream,
473 struct system_device_crosststamp *xtstamp)
474{
475 return get_device_system_crosststamp(azx_get_sync_time,
476 substream, NULL, xtstamp);
477}
478
479static inline bool is_link_time_supported(struct snd_pcm_runtime *runtime,
480 struct snd_pcm_audio_tstamp_config *ts)
481{
482 if (runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME)
483 if (ts->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED)
484 return true;
485
486 return false;
487}
488
489static int azx_get_time_info(struct snd_pcm_substream *substream,
490 struct timespec64 *system_ts, struct timespec64 *audio_ts,
491 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
492 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
493{
494 struct system_device_crosststamp xtstamp = { .clock_id = CLOCK_REALTIME };
495 struct azx_dev *azx_dev = get_azx_dev(substream);
496 struct snd_pcm_runtime *runtime = substream->runtime;
497 int ret;
498 u64 nsec;
499
500 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
501 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
502
503 snd_pcm_gettime(substream->runtime, system_ts);
504
505 nsec = timecounter_read(&azx_dev->core.tc);
506 if (audio_tstamp_config->report_delay)
507 nsec = azx_adjust_codec_delay(substream, nsec);
508
509 *audio_ts = ns_to_timespec64(nsec);
510
511 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
512 audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
513 audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */
514
515 } else if (is_link_time_supported(runtime, audio_tstamp_config)) {
516
517 ret = azx_get_crosststamp(substream, &xtstamp);
518 if (ret)
519 return ret;
520
521 switch (runtime->tstamp_type) {
522 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC:
523 return -EINVAL;
524
525 case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW:
526 *system_ts = ktime_to_timespec64(xtstamp.sys_monoraw);
527 break;
528
529 default:
530 *system_ts = ktime_to_timespec64(xtstamp.sys_systime);
531 break;
532
533 }
534
535 *audio_ts = ktime_to_timespec64(xtstamp.device);
536
537 audio_tstamp_report->actual_type =
538 SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK_SYNCHRONIZED;
539 audio_tstamp_report->accuracy_report = 1;
540 /* 24 MHz WallClock == 42ns resolution */
541 audio_tstamp_report->accuracy = 42;
542
543 } else {
544 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
545 }
546
547 return 0;
548}
549
550static const struct snd_pcm_hardware azx_pcm_hw = {
551 .info = (SNDRV_PCM_INFO_MMAP |
552 SNDRV_PCM_INFO_INTERLEAVED |
553 SNDRV_PCM_INFO_BLOCK_TRANSFER |
554 SNDRV_PCM_INFO_MMAP_VALID |
555 /* No full-resume yet implemented */
556 /* SNDRV_PCM_INFO_RESUME |*/
557 SNDRV_PCM_INFO_PAUSE |
558 SNDRV_PCM_INFO_SYNC_START |
559 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
560 SNDRV_PCM_INFO_HAS_LINK_ATIME |
561 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
562 .formats = SNDRV_PCM_FMTBIT_S16_LE,
563 .rates = SNDRV_PCM_RATE_48000,
564 .rate_min = 48000,
565 .rate_max = 48000,
566 .channels_min = 2,
567 .channels_max = 2,
568 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
569 .period_bytes_min = 128,
570 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
571 .periods_min = 2,
572 .periods_max = AZX_MAX_FRAG,
573 .fifo_size = 0,
574};
575
576static int azx_pcm_open(struct snd_pcm_substream *substream)
577{
578 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
579 struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
580 struct azx *chip = apcm->chip;
581 struct azx_dev *azx_dev;
582 struct snd_pcm_runtime *runtime = substream->runtime;
583 int err;
584 int buff_step;
585
586 snd_hda_codec_pcm_get(apcm->info);
587 mutex_lock(&chip->open_mutex);
588 azx_dev = azx_assign_device(chip, substream);
589 if (azx_dev == NULL) {
590 err = -EBUSY;
591 goto unlock;
592 }
593 trace_azx_pcm_open(chip, azx_dev);
594 runtime->private_data = azx_dev;
595
596 runtime->hw = azx_pcm_hw;
597 if (chip->gts_present)
598 runtime->hw.info |= SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME;
599 runtime->hw.channels_min = hinfo->channels_min;
600 runtime->hw.channels_max = hinfo->channels_max;
601 runtime->hw.formats = hinfo->formats;
602 runtime->hw.rates = hinfo->rates;
603 snd_pcm_limit_hw_rates(runtime);
604 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
605
606 /* avoid wrap-around with wall-clock */
607 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
608 20,
609 178000000);
610
611 if (chip->align_buffer_size)
612 /* constrain buffer sizes to be multiple of 128
613 bytes. This is more efficient in terms of memory
614 access but isn't required by the HDA spec and
615 prevents users from specifying exact period/buffer
616 sizes. For example for 44.1kHz, a period size set
617 to 20ms will be rounded to 19.59ms. */
618 buff_step = 128;
619 else
620 /* Don't enforce steps on buffer sizes, still need to
621 be multiple of 4 bytes (HDA spec). Tested on Intel
622 HDA controllers, may not work on all devices where
623 option needs to be disabled */
624 buff_step = 4;
625
626 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
627 buff_step);
628 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
629 buff_step);
630 snd_hda_power_up(apcm->codec);
631 if (hinfo->ops.open)
632 err = hinfo->ops.open(hinfo, apcm->codec, substream);
633 else
634 err = -ENODEV;
635 if (err < 0) {
636 azx_release_device(azx_dev);
637 goto powerdown;
638 }
639 snd_pcm_limit_hw_rates(runtime);
640 /* sanity check */
641 if (snd_BUG_ON(!runtime->hw.channels_min) ||
642 snd_BUG_ON(!runtime->hw.channels_max) ||
643 snd_BUG_ON(!runtime->hw.formats) ||
644 snd_BUG_ON(!runtime->hw.rates)) {
645 azx_release_device(azx_dev);
646 if (hinfo->ops.close)
647 hinfo->ops.close(hinfo, apcm->codec, substream);
648 err = -EINVAL;
649 goto powerdown;
650 }
651
652 /* disable LINK_ATIME timestamps for capture streams
653 until we figure out how to handle digital inputs */
654 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
655 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
656 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
657 }
658
659 snd_pcm_set_sync(substream);
660 mutex_unlock(&chip->open_mutex);
661 return 0;
662
663 powerdown:
664 snd_hda_power_down(apcm->codec);
665 unlock:
666 mutex_unlock(&chip->open_mutex);
667 snd_hda_codec_pcm_put(apcm->info);
668 return err;
669}
670
671static const struct snd_pcm_ops azx_pcm_ops = {
672 .open = azx_pcm_open,
673 .close = azx_pcm_close,
674 .hw_params = azx_pcm_hw_params,
675 .hw_free = azx_pcm_hw_free,
676 .prepare = azx_pcm_prepare,
677 .trigger = azx_pcm_trigger,
678 .pointer = azx_pcm_pointer,
679 .get_time_info = azx_get_time_info,
680};
681
682static void azx_pcm_free(struct snd_pcm *pcm)
683{
684 struct azx_pcm *apcm = pcm->private_data;
685 if (apcm) {
686 list_del(&apcm->list);
687 apcm->info->pcm = NULL;
688 kfree(apcm);
689 }
690}
691
692#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
693
694int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
695 struct hda_pcm *cpcm)
696{
697 struct hdac_bus *bus = &_bus->core;
698 struct azx *chip = bus_to_azx(bus);
699 struct snd_pcm *pcm;
700 struct azx_pcm *apcm;
701 int pcm_dev = cpcm->device;
702 unsigned int size;
703 int s, err;
704 int type = SNDRV_DMA_TYPE_DEV_SG;
705
706 list_for_each_entry(apcm, &chip->pcm_list, list) {
707 if (apcm->pcm->device == pcm_dev) {
708 dev_err(chip->card->dev, "PCM %d already exists\n",
709 pcm_dev);
710 return -EBUSY;
711 }
712 }
713 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
714 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
715 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
716 &pcm);
717 if (err < 0)
718 return err;
719 strscpy(pcm->name, cpcm->name, sizeof(pcm->name));
720 apcm = kzalloc_obj(*apcm);
721 if (apcm == NULL) {
722 snd_device_free(chip->card, pcm);
723 return -ENOMEM;
724 }
725 apcm->chip = chip;
726 apcm->pcm = pcm;
727 apcm->codec = codec;
728 apcm->info = cpcm;
729 pcm->private_data = apcm;
730 pcm->private_free = azx_pcm_free;
731 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
732 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
733 list_add_tail(&apcm->list, &chip->pcm_list);
734 cpcm->pcm = pcm;
735 for (s = 0; s < 2; s++) {
736 if (cpcm->stream[s].substreams)
737 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
738 }
739 /* buffer pre-allocation */
740 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
741 if (size > MAX_PREALLOC_SIZE)
742 size = MAX_PREALLOC_SIZE;
743 if (chip->uc_buffer)
744 type = SNDRV_DMA_TYPE_DEV_WC_SG;
745 snd_pcm_set_managed_buffer_all(pcm, type, chip->card->dev,
746 size, MAX_PREALLOC_SIZE);
747 return 0;
748}
749
750static unsigned int azx_command_addr(u32 cmd)
751{
752 unsigned int addr = cmd >> 28;
753
754 if (addr >= AZX_MAX_CODECS) {
755 snd_BUG();
756 addr = 0;
757 }
758
759 return addr;
760}
761
762/* receive a response */
763static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
764 unsigned int *res)
765{
766 struct azx *chip = bus_to_azx(bus);
767 struct hda_bus *hbus = &chip->bus;
768 int err;
769
770 again:
771 err = snd_hdac_bus_get_response(bus, addr, res);
772 if (!err)
773 return 0;
774
775 if (hbus->no_response_fallback)
776 return -EIO;
777
778 if (!bus->polling_mode) {
779 dev_warn(chip->card->dev,
780 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
781 bus->last_cmd[addr]);
782 bus->polling_mode = 1;
783 goto again;
784 }
785
786 if (chip->msi) {
787 dev_warn(chip->card->dev,
788 "No response from codec, disabling MSI: last cmd=0x%08x\n",
789 bus->last_cmd[addr]);
790 if (chip->ops->disable_msi_reset_irq &&
791 chip->ops->disable_msi_reset_irq(chip) < 0)
792 return -EIO;
793 goto again;
794 }
795
796 if (chip->probing) {
797 /* If this critical timeout happens during the codec probing
798 * phase, this is likely an access to a non-existing codec
799 * slot. Better to return an error and reset the system.
800 */
801 return -EIO;
802 }
803
804 /* no fallback mechanism? */
805 if (!chip->fallback_to_single_cmd)
806 return -EIO;
807
808 /* a fatal communication error; need either to reset or to fallback
809 * to the single_cmd mode
810 */
811 if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
812 hbus->response_reset = 1;
813 dev_err(chip->card->dev,
814 "No response from codec, resetting bus: last cmd=0x%08x\n",
815 bus->last_cmd[addr]);
816 return -EAGAIN; /* give a chance to retry */
817 }
818
819 dev_err(chip->card->dev,
820 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
821 bus->last_cmd[addr]);
822 chip->single_cmd = 1;
823 hbus->response_reset = 0;
824 snd_hdac_bus_stop_cmd_io(bus);
825 return -EIO;
826}
827
828/*
829 * Use the single immediate command instead of CORB/RIRB for simplicity
830 *
831 * Note: according to Intel, this is not preferred use. The command was
832 * intended for the BIOS only, and may get confused with unsolicited
833 * responses. So, we shouldn't use it for normal operation from the
834 * driver.
835 * I left the codes, however, for debugging/testing purposes.
836 */
837
838/* receive a response */
839static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
840{
841 int timeout = 50;
842
843 while (timeout--) {
844 /* check IRV busy bit */
845 if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
846 /* reuse rirb.res as the response return value */
847 azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
848 return 0;
849 }
850 udelay(1);
851 }
852 if (printk_ratelimit())
853 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
854 azx_readw(chip, IRS));
855 azx_bus(chip)->rirb.res[addr] = -1;
856 return -EIO;
857}
858
859/* send a command */
860static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
861{
862 struct azx *chip = bus_to_azx(bus);
863 unsigned int addr = azx_command_addr(val);
864 int timeout = 50;
865
866 bus->last_cmd[azx_command_addr(val)] = val;
867 while (timeout--) {
868 /* check ICB busy bit */
869 if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
870 /* Clear IRV valid bit */
871 azx_writew(chip, IRS, azx_readw(chip, IRS) |
872 AZX_IRS_VALID);
873 azx_writel(chip, IC, val);
874 azx_writew(chip, IRS, azx_readw(chip, IRS) |
875 AZX_IRS_BUSY);
876 return azx_single_wait_for_response(chip, addr);
877 }
878 udelay(1);
879 }
880 if (printk_ratelimit())
881 dev_dbg(chip->card->dev,
882 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
883 azx_readw(chip, IRS), val);
884 return -EIO;
885}
886
887/* receive a response */
888static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
889 unsigned int *res)
890{
891 if (res)
892 *res = bus->rirb.res[addr];
893 return 0;
894}
895
896/*
897 * The below are the main callbacks from hda_codec.
898 *
899 * They are just the skeleton to call sub-callbacks according to the
900 * current setting of chip->single_cmd.
901 */
902
903/* send a command */
904static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
905{
906 struct azx *chip = bus_to_azx(bus);
907
908 if (chip->disabled)
909 return 0;
910 if (chip->single_cmd || bus->use_pio_for_commands)
911 return azx_single_send_cmd(bus, val);
912 else
913 return snd_hdac_bus_send_cmd(bus, val);
914}
915
916/* get a response */
917static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
918 unsigned int *res)
919{
920 struct azx *chip = bus_to_azx(bus);
921
922 if (chip->disabled)
923 return 0;
924 if (chip->single_cmd || bus->use_pio_for_commands)
925 return azx_single_get_response(bus, addr, res);
926 else
927 return azx_rirb_get_response(bus, addr, res);
928}
929
930static const struct hdac_bus_ops bus_core_ops = {
931 .command = azx_send_cmd,
932 .get_response = azx_get_response,
933};
934
935#ifdef CONFIG_SND_HDA_DSP_LOADER
936/*
937 * DSP loading code (e.g. for CA0132)
938 */
939
940/* use the first stream for loading DSP */
941static struct azx_dev *
942azx_get_dsp_loader_dev(struct azx *chip)
943{
944 struct hdac_bus *bus = azx_bus(chip);
945 struct hdac_stream *s;
946
947 list_for_each_entry(s, &bus->stream_list, list)
948 if (s->index == chip->playback_index_offset)
949 return stream_to_azx_dev(s);
950
951 return NULL;
952}
953
954int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
955 unsigned int byte_size,
956 struct snd_dma_buffer *bufp)
957{
958 struct hdac_bus *bus = &codec->bus->core;
959 struct azx *chip = bus_to_azx(bus);
960 struct azx_dev *azx_dev;
961 struct hdac_stream *hstr;
962 bool saved = false;
963 int err;
964
965 azx_dev = azx_get_dsp_loader_dev(chip);
966 hstr = azx_stream(azx_dev);
967 scoped_guard(spinlock_irq, &bus->reg_lock) {
968 if (hstr->opened) {
969 chip->saved_azx_dev = *azx_dev;
970 saved = true;
971 }
972 }
973
974 err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
975 if (err < 0) {
976 guard(spinlock_irq)(&bus->reg_lock);
977 if (saved)
978 *azx_dev = chip->saved_azx_dev;
979 return err;
980 }
981
982 hstr->prepared = 0;
983 return err;
984}
985EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
986
987void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
988{
989 struct hdac_bus *bus = &codec->bus->core;
990 struct azx *chip = bus_to_azx(bus);
991 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
992
993 snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
994}
995EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
996
997void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
998 struct snd_dma_buffer *dmab)
999{
1000 struct hdac_bus *bus = &codec->bus->core;
1001 struct azx *chip = bus_to_azx(bus);
1002 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1003 struct hdac_stream *hstr = azx_stream(azx_dev);
1004
1005 if (!dmab->area || !hstr->locked)
1006 return;
1007
1008 snd_hdac_dsp_cleanup(hstr, dmab);
1009 guard(spinlock_irq)(&bus->reg_lock);
1010 if (hstr->opened)
1011 *azx_dev = chip->saved_azx_dev;
1012 hstr->locked = false;
1013}
1014EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
1015#endif /* CONFIG_SND_HDA_DSP_LOADER */
1016
1017/*
1018 * reset and start the controller registers
1019 */
1020void azx_init_chip(struct azx *chip, bool full_reset)
1021{
1022 if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
1023 /* correct RINTCNT for CXT */
1024 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1025 azx_writew(chip, RINTCNT, 0xc0);
1026 }
1027}
1028EXPORT_SYMBOL_GPL(azx_init_chip);
1029
1030void azx_stop_all_streams(struct azx *chip)
1031{
1032 struct hdac_bus *bus = azx_bus(chip);
1033
1034 snd_hdac_stop_streams(bus);
1035}
1036EXPORT_SYMBOL_GPL(azx_stop_all_streams);
1037
1038void azx_stop_chip(struct azx *chip)
1039{
1040 snd_hdac_bus_stop_chip(azx_bus(chip));
1041}
1042EXPORT_SYMBOL_GPL(azx_stop_chip);
1043
1044/*
1045 * interrupt handler
1046 */
1047static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
1048{
1049 struct azx *chip = bus_to_azx(bus);
1050 struct azx_dev *azx_dev = stream_to_azx_dev(s);
1051
1052 /* check whether this IRQ is really acceptable */
1053 if (!chip->ops->position_check ||
1054 chip->ops->position_check(chip, azx_dev)) {
1055 spin_unlock(&bus->reg_lock);
1056 snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
1057 spin_lock(&bus->reg_lock);
1058 }
1059}
1060
1061irqreturn_t azx_interrupt(int irq, void *dev_id)
1062{
1063 struct azx *chip = dev_id;
1064 struct hdac_bus *bus = azx_bus(chip);
1065 u32 status;
1066 bool active, handled = false;
1067 int repeat = 0; /* count for avoiding endless loop */
1068
1069 if (azx_has_pm_runtime(chip))
1070 if (!pm_runtime_active(chip->card->dev))
1071 return IRQ_NONE;
1072
1073 guard(spinlock)(&bus->reg_lock);
1074
1075 if (chip->disabled)
1076 return IRQ_NONE;
1077
1078 do {
1079 status = azx_readl(chip, INTSTS);
1080 if (status == 0 || status == 0xffffffff)
1081 break;
1082
1083 handled = true;
1084 active = false;
1085 if (snd_hdac_bus_handle_stream_irq(bus, status, stream_update))
1086 active = true;
1087
1088 status = azx_readb(chip, RIRBSTS);
1089 if (status & RIRB_INT_MASK) {
1090 /*
1091 * Clearing the interrupt status here ensures that no
1092 * interrupt gets masked after the RIRB wp is read in
1093 * snd_hdac_bus_update_rirb. This avoids a possible
1094 * race condition where codec response in RIRB may
1095 * remain unserviced by IRQ, eventually falling back
1096 * to polling mode in azx_rirb_get_response.
1097 */
1098 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1099 active = true;
1100 if (status & RIRB_INT_RESPONSE) {
1101 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
1102 udelay(80);
1103 snd_hdac_bus_update_rirb(bus);
1104 }
1105 }
1106 } while (active && ++repeat < 10);
1107
1108 return IRQ_RETVAL(handled);
1109}
1110EXPORT_SYMBOL_GPL(azx_interrupt);
1111
1112/*
1113 * Codec initerface
1114 */
1115
1116/*
1117 * Probe the given codec address
1118 */
1119static int probe_codec(struct azx *chip, int addr)
1120{
1121 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1122 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1123 struct hdac_bus *bus = azx_bus(chip);
1124 int err;
1125 unsigned int res = -1;
1126
1127 scoped_guard(mutex, &bus->cmd_mutex) {
1128 chip->probing = 1;
1129 azx_send_cmd(bus, cmd);
1130 err = azx_get_response(bus, addr, &res);
1131 chip->probing = 0;
1132 }
1133 if (err < 0 || res == -1)
1134 return -EIO;
1135 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1136 return 0;
1137}
1138
1139void snd_hda_bus_reset(struct hda_bus *bus)
1140{
1141 struct azx *chip = bus_to_azx(&bus->core);
1142
1143 bus->in_reset = 1;
1144 azx_stop_chip(chip);
1145 azx_init_chip(chip, true);
1146 if (bus->core.chip_init)
1147 snd_hda_bus_reset_codecs(bus);
1148 bus->in_reset = 0;
1149}
1150
1151/* HD-audio bus initialization */
1152int azx_bus_init(struct azx *chip, const char *model)
1153{
1154 struct hda_bus *bus = &chip->bus;
1155 int err;
1156
1157 err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops);
1158 if (err < 0)
1159 return err;
1160
1161 bus->card = chip->card;
1162 mutex_init(&bus->prepare_mutex);
1163 bus->pci = chip->pci;
1164 bus->modelname = model;
1165 bus->mixer_assigned = -1;
1166 bus->core.snoop = azx_snoop(chip);
1167 if (chip->get_position[0] != azx_get_pos_lpib ||
1168 chip->get_position[1] != azx_get_pos_lpib)
1169 bus->core.use_posbuf = true;
1170 bus->core.bdl_pos_adj = chip->bdl_pos_adj;
1171 if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
1172 bus->core.corbrp_self_clear = true;
1173
1174 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY)
1175 bus->core.align_bdle_4k = true;
1176
1177 if (chip->driver_caps & AZX_DCAPS_PIO_COMMANDS)
1178 bus->core.use_pio_for_commands = true;
1179
1180 /* enable sync_write flag for stable communication as default */
1181 bus->core.sync_write = 1;
1182
1183 return 0;
1184}
1185EXPORT_SYMBOL_GPL(azx_bus_init);
1186
1187/* Probe codecs */
1188int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
1189{
1190 struct hdac_bus *bus = azx_bus(chip);
1191 int c, codecs, err;
1192
1193 codecs = 0;
1194 if (!max_slots)
1195 max_slots = AZX_DEFAULT_CODECS;
1196
1197 /* First try to probe all given codec slots */
1198 for (c = 0; c < max_slots; c++) {
1199 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1200 if (probe_codec(chip, c) < 0) {
1201 /* Some BIOSen give you wrong codec addresses
1202 * that don't exist
1203 */
1204 dev_warn(chip->card->dev,
1205 "Codec #%d probe error; disabling it...\n", c);
1206 bus->codec_mask &= ~(1 << c);
1207 /* no codecs */
1208 if (bus->codec_mask == 0)
1209 break;
1210 /* More badly, accessing to a non-existing
1211 * codec often screws up the controller chip,
1212 * and disturbs the further communications.
1213 * Thus if an error occurs during probing,
1214 * better to reset the controller chip to
1215 * get back to the sanity state.
1216 */
1217 azx_stop_chip(chip);
1218 azx_init_chip(chip, true);
1219 }
1220 }
1221 }
1222
1223 /* Then create codec instances */
1224 for (c = 0; c < max_slots; c++) {
1225 if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1226 struct hda_codec *codec;
1227 err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1228 if (err < 0)
1229 continue;
1230 codec->jackpoll_interval = chip->jackpoll_interval;
1231 codec->beep_mode = chip->beep_mode;
1232 codec->ctl_dev_id = chip->ctl_dev_id;
1233 codecs++;
1234 }
1235 }
1236 if (!codecs) {
1237 dev_err(chip->card->dev, "no codecs initialized\n");
1238 return -ENXIO;
1239 }
1240 return 0;
1241}
1242EXPORT_SYMBOL_GPL(azx_probe_codecs);
1243
1244/* configure each codec instance */
1245int azx_codec_configure(struct azx *chip)
1246{
1247 struct hda_codec *codec, *next;
1248 int success = 0;
1249
1250 list_for_each_codec(codec, &chip->bus) {
1251 if (!snd_hda_codec_configure(codec))
1252 success++;
1253 }
1254
1255 if (success) {
1256 /* unregister failed codecs if any codec has been probed */
1257 list_for_each_codec_safe(codec, next, &chip->bus) {
1258 if (!codec->configured) {
1259 codec_err(codec, "Unable to configure, disabling\n");
1260 snd_hdac_device_unregister(&codec->core);
1261 }
1262 }
1263 }
1264
1265 return success ? 0 : -ENODEV;
1266}
1267EXPORT_SYMBOL_GPL(azx_codec_configure);
1268
1269void azx_add_stream(struct azx *chip, struct azx_dev *azx_dev, int idx, int tag)
1270{
1271 snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev), idx,
1272 azx_stream_direction(chip, idx), tag);
1273}
1274EXPORT_SYMBOL_GPL(azx_add_stream);
1275
1276/* initialize SD streams */
1277int azx_init_streams(struct azx *chip)
1278{
1279 int i;
1280
1281 /* initialize each stream (aka device)
1282 * assign the starting bdl address to each stream (device)
1283 * and initialize
1284 */
1285 for (i = 0; i < chip->num_streams; i++) {
1286 struct azx_dev *azx_dev = kzalloc_obj(*azx_dev);
1287
1288 if (!azx_dev)
1289 return -ENOMEM;
1290 azx_add_stream(chip, azx_dev, i, i + 1);
1291 }
1292
1293 return 0;
1294}
1295EXPORT_SYMBOL_GPL(azx_init_streams);
1296
1297void azx_free_streams(struct azx *chip)
1298{
1299 struct hdac_bus *bus = azx_bus(chip);
1300 struct hdac_stream *s;
1301
1302 while (!list_empty(&bus->stream_list)) {
1303 s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
1304 list_del(&s->list);
1305 kfree(stream_to_azx_dev(s));
1306 }
1307}
1308EXPORT_SYMBOL_GPL(azx_free_streams);