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1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2018 Intel Corporation
7//
8// Author: Liam Girdwood <[email protected]>
9//
10
11/*
12 * Hardware interface for audio DSP on Broadwell
13 */
14
15#include <linux/module.h>
16#include <sound/sof.h>
17#include <sound/sof/xtensa.h>
18#include <sound/soc-acpi.h>
19#include <sound/soc-acpi-intel-match.h>
20#include <sound/intel-dsp-config.h>
21#include "../ops.h"
22#include "shim.h"
23#include "../sof-acpi-dev.h"
24#include "../sof-audio.h"
25
26/* BARs */
27#define BDW_DSP_BAR 0
28#define BDW_PCI_BAR 1
29
30/*
31 * Debug
32 */
33
34/* DSP memories for BDW */
35#define IRAM_OFFSET 0xA0000
36#define BDW_IRAM_SIZE (10 * 32 * 1024)
37#define DRAM_OFFSET 0x00000
38#define BDW_DRAM_SIZE (20 * 32 * 1024)
39#define SHIM_OFFSET 0xFB000
40#define SHIM_SIZE 0x100
41#define MBOX_OFFSET 0x9E000
42#define MBOX_SIZE 0x1000
43#define MBOX_DUMP_SIZE 0x30
44#define EXCEPT_OFFSET 0x800
45#define EXCEPT_MAX_HDR_SIZE 0x400
46
47/* DSP peripherals */
48#define DMAC0_OFFSET 0xFE000
49#define DMAC1_OFFSET 0xFF000
50#define DMAC_SIZE 0x420
51#define SSP0_OFFSET 0xFC000
52#define SSP1_OFFSET 0xFD000
53#define SSP_SIZE 0x100
54
55#define BDW_STACK_DUMP_SIZE 32
56
57#define BDW_PANIC_OFFSET(x) ((x) & 0xFFFF)
58
59static const struct snd_sof_debugfs_map bdw_debugfs[] = {
60 {"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
61 SOF_DEBUGFS_ACCESS_ALWAYS},
62 {"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
63 SOF_DEBUGFS_ACCESS_ALWAYS},
64 {"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
65 SOF_DEBUGFS_ACCESS_ALWAYS},
66 {"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
67 SOF_DEBUGFS_ACCESS_ALWAYS},
68 {"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
69 SOF_DEBUGFS_ACCESS_D0_ONLY},
70 {"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
71 SOF_DEBUGFS_ACCESS_D0_ONLY},
72 {"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
73 SOF_DEBUGFS_ACCESS_ALWAYS},
74};
75
76static void bdw_host_done(struct snd_sof_dev *sdev);
77static void bdw_dsp_done(struct snd_sof_dev *sdev);
78
79/*
80 * DSP Control.
81 */
82
83static int bdw_run(struct snd_sof_dev *sdev)
84{
85 /* set opportunistic mode on engine 0,1 for all channels */
86 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
87 SHIM_HMDC_HDDA_E0_ALLCH |
88 SHIM_HMDC_HDDA_E1_ALLCH, 0);
89
90 /* set DSP to RUN */
91 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
92 SHIM_CSR_STALL, 0x0);
93
94 /* return init core mask */
95 return 1;
96}
97
98static int bdw_reset(struct snd_sof_dev *sdev)
99{
100 /* put DSP into reset and stall */
101 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
102 SHIM_CSR_RST | SHIM_CSR_STALL,
103 SHIM_CSR_RST | SHIM_CSR_STALL);
104
105 /* keep in reset for 10ms */
106 mdelay(10);
107
108 /* take DSP out of reset and keep stalled for FW loading */
109 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
110 SHIM_CSR_RST | SHIM_CSR_STALL,
111 SHIM_CSR_STALL);
112
113 return 0;
114}
115
116static int bdw_set_dsp_D0(struct snd_sof_dev *sdev)
117{
118 int tries = 10;
119 u32 reg;
120
121 /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */
122 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
123 PCI_VDRTCL2_DCLCGE |
124 PCI_VDRTCL2_DTCGE, 0);
125
126 /* Disable D3PG (VDRTCTL0.D3PGD = 1) */
127 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
128 PCI_VDRTCL0_D3PGD, PCI_VDRTCL0_D3PGD);
129
130 /* Set D0 state */
131 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_PMCS,
132 PCI_PMCS_PS_MASK, 0);
133
134 /* check that ADSP shim is enabled */
135 while (tries--) {
136 reg = readl(sdev->bar[BDW_PCI_BAR] + PCI_PMCS)
137 & PCI_PMCS_PS_MASK;
138 if (reg == 0)
139 goto finish;
140
141 msleep(20);
142 }
143
144 return -ENODEV;
145
146finish:
147 /*
148 * select SSP1 19.2MHz base clock, SSP clock 0,
149 * turn off Low Power Clock
150 */
151 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,
152 SHIM_CSR_S1IOCS | SHIM_CSR_SBCS1 |
153 SHIM_CSR_LPCS, 0x0);
154
155 /* stall DSP core, set clk to 192/96Mhz */
156 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
157 SHIM_CSR, SHIM_CSR_STALL |
158 SHIM_CSR_DCS_MASK,
159 SHIM_CSR_STALL |
160 SHIM_CSR_DCS(4));
161
162 /* Set 24MHz MCLK, prevent local clock gating, enable SSP0 clock */
163 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,
164 SHIM_CLKCTL_MASK |
165 SHIM_CLKCTL_DCPLCG |
166 SHIM_CLKCTL_SCOE0,
167 SHIM_CLKCTL_MASK |
168 SHIM_CLKCTL_DCPLCG |
169 SHIM_CLKCTL_SCOE0);
170
171 /* Stall and reset core, set CSR */
172 bdw_reset(sdev);
173
174 /* Enable core clock gating (VDRTCTL2.DCLCGE = 1), delay 50 us */
175 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
176 PCI_VDRTCL2_DCLCGE |
177 PCI_VDRTCL2_DTCGE,
178 PCI_VDRTCL2_DCLCGE |
179 PCI_VDRTCL2_DTCGE);
180
181 usleep_range(50, 55);
182
183 /* switch on audio PLL */
184 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL2,
185 PCI_VDRTCL2_APLLSE_MASK, 0);
186
187 /*
188 * set default power gating control, enable power gating control for
189 * all blocks. that is, can't be accessed, please enable each block
190 * before accessing.
191 */
192 snd_sof_dsp_update_bits_unlocked(sdev, BDW_PCI_BAR, PCI_VDRTCTL0,
193 0xfffffffC, 0x0);
194
195 /* disable DMA finish function for SSP0 & SSP1 */
196 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR2,
197 SHIM_CSR2_SDFD_SSP1,
198 SHIM_CSR2_SDFD_SSP1);
199
200 /* set on-demond mode on engine 0,1 for all channels */
201 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,
202 SHIM_HMDC_HDDA_E0_ALLCH |
203 SHIM_HMDC_HDDA_E1_ALLCH,
204 SHIM_HMDC_HDDA_E0_ALLCH |
205 SHIM_HMDC_HDDA_E1_ALLCH);
206
207 /* Enable Interrupt from both sides */
208 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,
209 (SHIM_IMRX_BUSY | SHIM_IMRX_DONE), 0x0);
210 snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,
211 (SHIM_IMRD_DONE | SHIM_IMRD_BUSY |
212 SHIM_IMRD_SSP0 | SHIM_IMRD_DMAC), 0x0);
213
214 /* clear IPC registers */
215 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);
216 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);
217 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);
218 snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);
219
220 return 0;
221}
222
223static void bdw_get_registers(struct snd_sof_dev *sdev,
224 struct sof_ipc_dsp_oops_xtensa *xoops,
225 struct sof_ipc_panic_info *panic_info,
226 u32 *stack, size_t stack_words)
227{
228 u32 offset = sdev->dsp_oops_offset;
229
230 /* first read registers */
231 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
232
233 /* note: variable AR register array is not read */
234
235 /* then get panic info */
236 if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
237 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
238 xoops->arch_hdr.totalsize);
239 return;
240 }
241 offset += xoops->arch_hdr.totalsize;
242 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
243
244 /* then get the stack */
245 offset += sizeof(*panic_info);
246 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
247}
248
249static void bdw_dump(struct snd_sof_dev *sdev, u32 flags)
250{
251 struct sof_ipc_dsp_oops_xtensa xoops;
252 struct sof_ipc_panic_info panic_info;
253 u32 stack[BDW_STACK_DUMP_SIZE];
254 u32 status, panic, imrx, imrd;
255
256 /* now try generic SOF status messages */
257 status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
258 panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
259 bdw_get_registers(sdev, &xoops, &panic_info, stack,
260 BDW_STACK_DUMP_SIZE);
261 sof_print_oops_and_stack(sdev, KERN_ERR, status, panic, &xoops,
262 &panic_info, stack, BDW_STACK_DUMP_SIZE);
263
264 /* provide some context for firmware debug */
265 imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);
266 imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);
267 dev_err(sdev->dev,
268 "error: ipc host -> DSP: pending %s complete %s raw 0x%8.8x\n",
269 str_yes_no(panic & SHIM_IPCX_BUSY),
270 str_yes_no(panic & SHIM_IPCX_DONE), panic);
271 dev_err(sdev->dev,
272 "error: mask host: pending %s complete %s raw 0x%8.8x\n",
273 str_yes_no(imrx & SHIM_IMRX_BUSY),
274 str_yes_no(imrx & SHIM_IMRX_DONE), imrx);
275 dev_err(sdev->dev,
276 "error: ipc DSP -> host: pending %s complete %s raw 0x%8.8x\n",
277 str_yes_no(status & SHIM_IPCD_BUSY),
278 str_yes_no(status & SHIM_IPCD_DONE), status);
279 dev_err(sdev->dev,
280 "error: mask DSP: pending %s complete %s raw 0x%8.8x\n",
281 str_yes_no(imrd & SHIM_IMRD_BUSY),
282 str_yes_no(imrd & SHIM_IMRD_DONE), imrd);
283}
284
285/*
286 * IPC Doorbell IRQ handler and thread.
287 */
288
289static irqreturn_t bdw_irq_handler(int irq, void *context)
290{
291 struct snd_sof_dev *sdev = context;
292 u32 isr;
293 int ret = IRQ_NONE;
294
295 /* Interrupt arrived, check src */
296 isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);
297 if (isr & (SHIM_ISRX_DONE | SHIM_ISRX_BUSY))
298 ret = IRQ_WAKE_THREAD;
299
300 return ret;
301}
302
303static irqreturn_t bdw_irq_thread(int irq, void *context)
304{
305 struct snd_sof_dev *sdev = context;
306 u32 ipcx, ipcd, imrx;
307
308 imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);
309 ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);
310
311 /* reply message from DSP */
312 if (ipcx & SHIM_IPCX_DONE &&
313 !(imrx & SHIM_IMRX_DONE)) {
314 /* Mask Done interrupt before return */
315 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
316 SHIM_IMRX, SHIM_IMRX_DONE,
317 SHIM_IMRX_DONE);
318 /*
319 * handle immediate reply from DSP core. If the msg is
320 * found, set done bit in cmd_done which is called at the
321 * end of message processing function, else set it here
322 * because the done bit can't be set in cmd_done function
323 * which is triggered by msg
324 */
325 guard(spinlock_irq)(&sdev->ipc_lock);
326 snd_sof_ipc_process_reply(sdev, ipcx);
327 bdw_dsp_done(sdev);
328 }
329
330 ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);
331
332 /* new message from DSP */
333 if (ipcd & SHIM_IPCD_BUSY &&
334 !(imrx & SHIM_IMRX_BUSY)) {
335 /* Mask Busy interrupt before return */
336 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,
337 SHIM_IMRX, SHIM_IMRX_BUSY,
338 SHIM_IMRX_BUSY);
339
340 /* Handle messages from DSP Core */
341 if ((ipcd & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
342 snd_sof_dsp_panic(sdev, BDW_PANIC_OFFSET(ipcx) + MBOX_OFFSET,
343 true);
344 } else {
345 snd_sof_ipc_msgs_rx(sdev);
346 }
347
348 bdw_host_done(sdev);
349 }
350
351 return IRQ_HANDLED;
352}
353
354/*
355 * IPC Mailbox IO
356 */
357
358static int bdw_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
359{
360 /* send the message */
361 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
362 msg->msg_size);
363 snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);
364
365 return 0;
366}
367
368static int bdw_get_mailbox_offset(struct snd_sof_dev *sdev)
369{
370 return MBOX_OFFSET;
371}
372
373static int bdw_get_window_offset(struct snd_sof_dev *sdev, u32 id)
374{
375 return MBOX_OFFSET;
376}
377
378static void bdw_host_done(struct snd_sof_dev *sdev)
379{
380 /* clear BUSY bit and set DONE bit - accept new messages */
381 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,
382 SHIM_IPCD_BUSY | SHIM_IPCD_DONE,
383 SHIM_IPCD_DONE);
384
385 /* unmask busy interrupt */
386 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
387 SHIM_IMRX_BUSY, 0);
388}
389
390static void bdw_dsp_done(struct snd_sof_dev *sdev)
391{
392 /* clear DONE bit - tell DSP we have completed */
393 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,
394 SHIM_IPCX_DONE, 0);
395
396 /* unmask Done interrupt */
397 snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,
398 SHIM_IMRX_DONE, 0);
399}
400
401/*
402 * Probe and remove.
403 */
404static int bdw_probe(struct snd_sof_dev *sdev)
405{
406 struct snd_sof_pdata *pdata = sdev->pdata;
407 const struct sof_dev_desc *desc = pdata->desc;
408 struct platform_device *pdev = to_platform_device(sdev->dev);
409 const struct sof_intel_dsp_desc *chip;
410 struct resource *mmio;
411 u32 base, size;
412 int ret;
413
414 chip = get_chip_info(sdev->pdata);
415 if (!chip) {
416 dev_err(sdev->dev, "error: no such device supported\n");
417 return -EIO;
418 }
419
420 sdev->num_cores = chip->cores_num;
421
422 /* LPE base */
423 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
424 desc->resindex_lpe_base);
425 if (mmio) {
426 base = mmio->start;
427 size = resource_size(mmio);
428 } else {
429 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
430 desc->resindex_lpe_base);
431 return -EINVAL;
432 }
433
434 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
435 sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
436 if (!sdev->bar[BDW_DSP_BAR]) {
437 dev_err(sdev->dev,
438 "error: failed to ioremap LPE base 0x%x size 0x%x\n",
439 base, size);
440 return -ENODEV;
441 }
442 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);
443
444 /* TODO: add offsets */
445 sdev->mmio_bar = BDW_DSP_BAR;
446 sdev->mailbox_bar = BDW_DSP_BAR;
447 sdev->dsp_oops_offset = MBOX_OFFSET;
448
449 /* PCI base */
450 mmio = platform_get_resource(pdev, IORESOURCE_MEM,
451 desc->resindex_pcicfg_base);
452 if (mmio) {
453 base = mmio->start;
454 size = resource_size(mmio);
455 } else {
456 dev_err(sdev->dev, "error: failed to get PCI base at idx %d\n",
457 desc->resindex_pcicfg_base);
458 return -ENODEV;
459 }
460
461 dev_dbg(sdev->dev, "PCI base at 0x%x size 0x%x", base, size);
462 sdev->bar[BDW_PCI_BAR] = devm_ioremap(sdev->dev, base, size);
463 if (!sdev->bar[BDW_PCI_BAR]) {
464 dev_err(sdev->dev,
465 "error: failed to ioremap PCI base 0x%x size 0x%x\n",
466 base, size);
467 return -ENODEV;
468 }
469 dev_dbg(sdev->dev, "PCI VADDR %p\n", sdev->bar[BDW_PCI_BAR]);
470
471 /* register our IRQ */
472 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
473 if (sdev->ipc_irq < 0)
474 return sdev->ipc_irq;
475
476 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
477 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
478 bdw_irq_handler, bdw_irq_thread,
479 IRQF_SHARED, "AudioDSP", sdev);
480 if (ret < 0) {
481 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
482 sdev->ipc_irq);
483 return ret;
484 }
485
486 /* enable the DSP SHIM */
487 ret = bdw_set_dsp_D0(sdev);
488 if (ret < 0) {
489 dev_err(sdev->dev, "error: failed to set DSP D0\n");
490 return ret;
491 }
492
493 /* DSP DMA can only access low 31 bits of host memory */
494 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
495 if (ret < 0) {
496 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
497 return ret;
498 }
499
500 /* set default mailbox offset for FW ready message */
501 sdev->dsp_box.offset = MBOX_OFFSET;
502
503 return ret;
504}
505
506static struct snd_soc_acpi_mach *bdw_machine_select(struct snd_sof_dev *sdev)
507{
508 struct snd_sof_pdata *sof_pdata = sdev->pdata;
509 const struct sof_dev_desc *desc = sof_pdata->desc;
510 struct snd_soc_acpi_mach *mach;
511
512 mach = snd_soc_acpi_find_machine(desc->machines);
513 if (!mach) {
514 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
515 return NULL;
516 }
517
518 sof_pdata->tplg_filename = mach->sof_tplg_filename;
519 mach->mach_params.acpi_ipc_irq_index = desc->irqindex_host_ipc;
520
521 return mach;
522}
523
524static void bdw_set_mach_params(struct snd_soc_acpi_mach *mach,
525 struct snd_sof_dev *sdev)
526{
527 struct snd_sof_pdata *pdata = sdev->pdata;
528 const struct sof_dev_desc *desc = pdata->desc;
529 struct snd_soc_acpi_mach_params *mach_params;
530
531 mach_params = &mach->mach_params;
532 mach_params->platform = dev_name(sdev->dev);
533 mach_params->num_dai_drivers = desc->ops->num_drv;
534 mach_params->dai_drivers = desc->ops->drv;
535}
536
537/* Broadwell DAIs */
538static struct snd_soc_dai_driver bdw_dai[] = {
539{
540 .name = "ssp0-port",
541 .playback = {
542 .channels_min = 1,
543 .channels_max = 8,
544 },
545 .capture = {
546 .channels_min = 1,
547 .channels_max = 8,
548 },
549},
550{
551 .name = "ssp1-port",
552 .playback = {
553 .channels_min = 1,
554 .channels_max = 8,
555 },
556 .capture = {
557 .channels_min = 1,
558 .channels_max = 8,
559 },
560},
561};
562
563/* broadwell ops */
564static const struct snd_sof_dsp_ops sof_bdw_ops = {
565 /*Device init */
566 .probe = bdw_probe,
567
568 /* DSP Core Control */
569 .run = bdw_run,
570 .reset = bdw_reset,
571
572 /* Register IO uses direct mmio */
573
574 /* Block IO */
575 .block_read = sof_block_read,
576 .block_write = sof_block_write,
577
578 /* Mailbox IO */
579 .mailbox_read = sof_mailbox_read,
580 .mailbox_write = sof_mailbox_write,
581
582 /* ipc */
583 .send_msg = bdw_send_msg,
584 .get_mailbox_offset = bdw_get_mailbox_offset,
585 .get_window_offset = bdw_get_window_offset,
586
587 .ipc_msg_data = sof_ipc_msg_data,
588 .set_stream_data_offset = sof_set_stream_data_offset,
589
590 /* machine driver */
591 .machine_select = bdw_machine_select,
592 .machine_register = sof_machine_register,
593 .machine_unregister = sof_machine_unregister,
594 .set_mach_params = bdw_set_mach_params,
595
596 /* debug */
597 .debug_map = bdw_debugfs,
598 .debug_map_count = ARRAY_SIZE(bdw_debugfs),
599 .dbg_dump = bdw_dump,
600 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
601
602 /* stream callbacks */
603 .pcm_open = sof_stream_pcm_open,
604 .pcm_close = sof_stream_pcm_close,
605
606 /*Firmware loading */
607 .load_firmware = snd_sof_load_firmware_memcpy,
608
609 /* DAI drivers */
610 .drv = bdw_dai,
611 .num_drv = ARRAY_SIZE(bdw_dai),
612
613 /* ALSA HW info flags */
614 .hw_info = SNDRV_PCM_INFO_MMAP |
615 SNDRV_PCM_INFO_MMAP_VALID |
616 SNDRV_PCM_INFO_INTERLEAVED |
617 SNDRV_PCM_INFO_PAUSE |
618 SNDRV_PCM_INFO_BATCH,
619
620 .dsp_arch_ops = &sof_xtensa_arch_ops,
621};
622
623static const struct sof_intel_dsp_desc bdw_chip_info = {
624 .cores_num = 1,
625 .host_managed_cores_mask = 1,
626 .hw_ip_version = SOF_INTEL_BROADWELL,
627};
628
629static const struct sof_dev_desc sof_acpi_broadwell_desc = {
630 .machines = snd_soc_acpi_intel_broadwell_machines,
631 .resindex_lpe_base = 0,
632 .resindex_pcicfg_base = 1,
633 .resindex_imr_base = -1,
634 .irqindex_host_ipc = 0,
635 .chip_info = &bdw_chip_info,
636 .ipc_supported_mask = BIT(SOF_IPC_TYPE_3),
637 .ipc_default = SOF_IPC_TYPE_3,
638 .default_fw_path = {
639 [SOF_IPC_TYPE_3] = "intel/sof",
640 },
641 .default_tplg_path = {
642 [SOF_IPC_TYPE_3] = "intel/sof-tplg",
643 },
644 .default_fw_filename = {
645 [SOF_IPC_TYPE_3] = "sof-bdw.ri",
646 },
647 .nocodec_tplg_filename = "sof-bdw-nocodec.tplg",
648 .ops = &sof_bdw_ops,
649};
650
651static const struct acpi_device_id sof_broadwell_match[] = {
652 { "INT3438", (unsigned long)&sof_acpi_broadwell_desc },
653 { }
654};
655MODULE_DEVICE_TABLE(acpi, sof_broadwell_match);
656
657static int sof_broadwell_probe(struct platform_device *pdev)
658{
659 struct device *dev = &pdev->dev;
660 const struct acpi_device_id *id;
661 const struct sof_dev_desc *desc;
662 int ret;
663
664 id = acpi_match_device(dev->driver->acpi_match_table, dev);
665 if (!id)
666 return -ENODEV;
667
668 ret = snd_intel_acpi_dsp_driver_probe(dev, id->id);
669 if (ret != SND_INTEL_DSP_DRIVER_ANY && ret != SND_INTEL_DSP_DRIVER_SOF) {
670 dev_dbg(dev, "SOF ACPI driver not selected, aborting probe\n");
671 return -ENODEV;
672 }
673
674 desc = (const struct sof_dev_desc *)id->driver_data;
675 return sof_acpi_probe(pdev, desc);
676}
677
678/* acpi_driver definition */
679static struct platform_driver snd_sof_acpi_intel_bdw_driver = {
680 .probe = sof_broadwell_probe,
681 .remove = sof_acpi_remove,
682 .driver = {
683 .name = "sof-audio-acpi-intel-bdw",
684 .pm = pm_ptr(&sof_acpi_pm),
685 .acpi_match_table = sof_broadwell_match,
686 },
687};
688module_platform_driver(snd_sof_acpi_intel_bdw_driver);
689
690MODULE_LICENSE("Dual BSD/GPL");
691MODULE_DESCRIPTION("SOF support for Broadwell platforms");
692MODULE_IMPORT_NS("SND_SOC_SOF_XTENSA");
693MODULE_IMPORT_NS("SND_SOC_SOF_ACPI_DEV");