projects/linux·blob master · refs

1153 lines · 30.1 KiB

1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// This file is provided under a dual BSD/GPLv2 license. When using or
4// redistributing this file, you may do so under either license.
5//
6// Copyright(c) 2021 Intel Corporation
7//
8//
9
10#include <sound/sof/stream.h>
11#include <sound/sof/control.h>
12#include <trace/events/sof.h>
13#include "sof-priv.h"
14#include "sof-audio.h"
15#include "ipc3-priv.h"
16#include "ops.h"
17
18typedef void (*ipc3_rx_callback)(struct snd_sof_dev *sdev, void *msg_buf);
19
20#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG_VERBOSE_IPC)
21static void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
22{
23 u8 *str;
24 u8 *str2 = NULL;
25 u32 glb;
26 u32 type;
27 bool is_sof_ipc_stream_position = false;
28
29 glb = cmd & SOF_GLB_TYPE_MASK;
30 type = cmd & SOF_CMD_TYPE_MASK;
31
32 switch (glb) {
33 case SOF_IPC_GLB_REPLY:
34 str = "GLB_REPLY"; break;
35 case SOF_IPC_GLB_COMPOUND:
36 str = "GLB_COMPOUND"; break;
37 case SOF_IPC_GLB_TPLG_MSG:
38 str = "GLB_TPLG_MSG";
39 switch (type) {
40 case SOF_IPC_TPLG_COMP_NEW:
41 str2 = "COMP_NEW"; break;
42 case SOF_IPC_TPLG_COMP_FREE:
43 str2 = "COMP_FREE"; break;
44 case SOF_IPC_TPLG_COMP_CONNECT:
45 str2 = "COMP_CONNECT"; break;
46 case SOF_IPC_TPLG_PIPE_NEW:
47 str2 = "PIPE_NEW"; break;
48 case SOF_IPC_TPLG_PIPE_FREE:
49 str2 = "PIPE_FREE"; break;
50 case SOF_IPC_TPLG_PIPE_CONNECT:
51 str2 = "PIPE_CONNECT"; break;
52 case SOF_IPC_TPLG_PIPE_COMPLETE:
53 str2 = "PIPE_COMPLETE"; break;
54 case SOF_IPC_TPLG_BUFFER_NEW:
55 str2 = "BUFFER_NEW"; break;
56 case SOF_IPC_TPLG_BUFFER_FREE:
57 str2 = "BUFFER_FREE"; break;
58 default:
59 str2 = "unknown type"; break;
60 }
61 break;
62 case SOF_IPC_GLB_PM_MSG:
63 str = "GLB_PM_MSG";
64 switch (type) {
65 case SOF_IPC_PM_CTX_SAVE:
66 str2 = "CTX_SAVE"; break;
67 case SOF_IPC_PM_CTX_RESTORE:
68 str2 = "CTX_RESTORE"; break;
69 case SOF_IPC_PM_CTX_SIZE:
70 str2 = "CTX_SIZE"; break;
71 case SOF_IPC_PM_CLK_SET:
72 str2 = "CLK_SET"; break;
73 case SOF_IPC_PM_CLK_GET:
74 str2 = "CLK_GET"; break;
75 case SOF_IPC_PM_CLK_REQ:
76 str2 = "CLK_REQ"; break;
77 case SOF_IPC_PM_CORE_ENABLE:
78 str2 = "CORE_ENABLE"; break;
79 case SOF_IPC_PM_GATE:
80 str2 = "GATE"; break;
81 default:
82 str2 = "unknown type"; break;
83 }
84 break;
85 case SOF_IPC_GLB_COMP_MSG:
86 str = "GLB_COMP_MSG";
87 switch (type) {
88 case SOF_IPC_COMP_SET_VALUE:
89 str2 = "SET_VALUE"; break;
90 case SOF_IPC_COMP_GET_VALUE:
91 str2 = "GET_VALUE"; break;
92 case SOF_IPC_COMP_SET_DATA:
93 str2 = "SET_DATA"; break;
94 case SOF_IPC_COMP_GET_DATA:
95 str2 = "GET_DATA"; break;
96 default:
97 str2 = "unknown type"; break;
98 }
99 break;
100 case SOF_IPC_GLB_STREAM_MSG:
101 str = "GLB_STREAM_MSG";
102 switch (type) {
103 case SOF_IPC_STREAM_PCM_PARAMS:
104 str2 = "PCM_PARAMS"; break;
105 case SOF_IPC_STREAM_PCM_PARAMS_REPLY:
106 str2 = "PCM_REPLY"; break;
107 case SOF_IPC_STREAM_PCM_FREE:
108 str2 = "PCM_FREE"; break;
109 case SOF_IPC_STREAM_TRIG_START:
110 str2 = "TRIG_START"; break;
111 case SOF_IPC_STREAM_TRIG_STOP:
112 str2 = "TRIG_STOP"; break;
113 case SOF_IPC_STREAM_TRIG_PAUSE:
114 str2 = "TRIG_PAUSE"; break;
115 case SOF_IPC_STREAM_TRIG_RELEASE:
116 str2 = "TRIG_RELEASE"; break;
117 case SOF_IPC_STREAM_TRIG_DRAIN:
118 str2 = "TRIG_DRAIN"; break;
119 case SOF_IPC_STREAM_TRIG_XRUN:
120 str2 = "TRIG_XRUN"; break;
121 case SOF_IPC_STREAM_POSITION:
122 is_sof_ipc_stream_position = true;
123 str2 = "POSITION"; break;
124 case SOF_IPC_STREAM_VORBIS_PARAMS:
125 str2 = "VORBIS_PARAMS"; break;
126 case SOF_IPC_STREAM_VORBIS_FREE:
127 str2 = "VORBIS_FREE"; break;
128 default:
129 str2 = "unknown type"; break;
130 }
131 break;
132 case SOF_IPC_FW_READY:
133 str = "FW_READY"; break;
134 case SOF_IPC_GLB_DAI_MSG:
135 str = "GLB_DAI_MSG";
136 switch (type) {
137 case SOF_IPC_DAI_CONFIG:
138 str2 = "CONFIG"; break;
139 case SOF_IPC_DAI_LOOPBACK:
140 str2 = "LOOPBACK"; break;
141 default:
142 str2 = "unknown type"; break;
143 }
144 break;
145 case SOF_IPC_GLB_TRACE_MSG:
146 str = "GLB_TRACE_MSG";
147 switch (type) {
148 case SOF_IPC_TRACE_DMA_PARAMS:
149 str2 = "DMA_PARAMS"; break;
150 case SOF_IPC_TRACE_DMA_POSITION:
151 if (!sof_debug_check_flag(SOF_DBG_PRINT_DMA_POSITION_UPDATE_LOGS))
152 return;
153 str2 = "DMA_POSITION"; break;
154 case SOF_IPC_TRACE_DMA_PARAMS_EXT:
155 str2 = "DMA_PARAMS_EXT"; break;
156 case SOF_IPC_TRACE_FILTER_UPDATE:
157 str2 = "FILTER_UPDATE"; break;
158 case SOF_IPC_TRACE_DMA_FREE:
159 str2 = "DMA_FREE"; break;
160 default:
161 str2 = "unknown type"; break;
162 }
163 break;
164 case SOF_IPC_GLB_TEST_MSG:
165 str = "GLB_TEST_MSG";
166 switch (type) {
167 case SOF_IPC_TEST_IPC_FLOOD:
168 str2 = "IPC_FLOOD"; break;
169 default:
170 str2 = "unknown type"; break;
171 }
172 break;
173 case SOF_IPC_GLB_DEBUG:
174 str = "GLB_DEBUG";
175 switch (type) {
176 case SOF_IPC_DEBUG_MEM_USAGE:
177 str2 = "MEM_USAGE"; break;
178 default:
179 str2 = "unknown type"; break;
180 }
181 break;
182 case SOF_IPC_GLB_PROBE:
183 str = "GLB_PROBE";
184 switch (type) {
185 case SOF_IPC_PROBE_INIT:
186 str2 = "INIT"; break;
187 case SOF_IPC_PROBE_DEINIT:
188 str2 = "DEINIT"; break;
189 case SOF_IPC_PROBE_DMA_ADD:
190 str2 = "DMA_ADD"; break;
191 case SOF_IPC_PROBE_DMA_INFO:
192 str2 = "DMA_INFO"; break;
193 case SOF_IPC_PROBE_DMA_REMOVE:
194 str2 = "DMA_REMOVE"; break;
195 case SOF_IPC_PROBE_POINT_ADD:
196 str2 = "POINT_ADD"; break;
197 case SOF_IPC_PROBE_POINT_INFO:
198 str2 = "POINT_INFO"; break;
199 case SOF_IPC_PROBE_POINT_REMOVE:
200 str2 = "POINT_REMOVE"; break;
201 default:
202 str2 = "unknown type"; break;
203 }
204 break;
205 default:
206 str = "unknown GLB command"; break;
207 }
208
209 if (str2) {
210 if (is_sof_ipc_stream_position)
211 trace_sof_stream_position_ipc_rx(dev);
212 else
213 dev_dbg(dev, "%s: 0x%x: %s: %s\n", text, cmd, str, str2);
214 } else {
215 dev_dbg(dev, "%s: 0x%x: %s\n", text, cmd, str);
216 }
217}
218#else
219static inline void ipc3_log_header(struct device *dev, u8 *text, u32 cmd)
220{
221 if ((cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_TRACE_MSG)
222 dev_dbg(dev, "%s: 0x%x\n", text, cmd);
223}
224#endif
225
226static void sof_ipc3_dump_payload(struct snd_sof_dev *sdev,
227 void *ipc_data, size_t size)
228{
229 dev_dbg(sdev->dev, "Size of payload following the header: %zu\n", size);
230 print_hex_dump_debug("Message payload: ", DUMP_PREFIX_OFFSET,
231 16, 4, ipc_data, size, false);
232}
233
234static int sof_ipc3_get_reply(struct snd_sof_dev *sdev)
235{
236 struct snd_sof_ipc_msg *msg = sdev->msg;
237 struct sof_ipc_reply *reply;
238 int ret = 0;
239
240 /* get the generic reply */
241 reply = msg->reply_data;
242 snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset, reply, sizeof(*reply));
243
244 if (reply->error < 0)
245 return reply->error;
246
247 if (!reply->hdr.size) {
248 /* Reply should always be >= sizeof(struct sof_ipc_reply) */
249 if (msg->reply_size)
250 dev_err(sdev->dev,
251 "empty reply received, expected %zu bytes\n",
252 msg->reply_size);
253 else
254 dev_err(sdev->dev, "empty reply received\n");
255
256 return -EINVAL;
257 }
258
259 if (msg->reply_size > 0) {
260 if (reply->hdr.size == msg->reply_size) {
261 ret = 0;
262 } else if (reply->hdr.size < msg->reply_size) {
263 dev_dbg(sdev->dev,
264 "reply size (%u) is less than expected (%zu)\n",
265 reply->hdr.size, msg->reply_size);
266
267 msg->reply_size = reply->hdr.size;
268 ret = 0;
269 } else {
270 dev_err(sdev->dev,
271 "reply size (%u) exceeds the buffer size (%zu)\n",
272 reply->hdr.size, msg->reply_size);
273 ret = -EINVAL;
274 }
275
276 /*
277 * get the full message if reply->hdr.size <= msg->reply_size
278 * and the reply->hdr.size > sizeof(struct sof_ipc_reply)
279 */
280 if (!ret && msg->reply_size > sizeof(*reply))
281 snd_sof_dsp_mailbox_read(sdev, sdev->host_box.offset,
282 msg->reply_data, msg->reply_size);
283 }
284
285 return ret;
286}
287
288/* wait for IPC message reply */
289static int ipc3_wait_tx_done(struct snd_sof_ipc *ipc, void *reply_data)
290{
291 struct snd_sof_ipc_msg *msg = &ipc->msg;
292 struct sof_ipc_cmd_hdr *hdr = msg->msg_data;
293 struct snd_sof_dev *sdev = ipc->sdev;
294 int ret;
295
296 /* wait for DSP IPC completion */
297 ret = wait_event_timeout(msg->waitq, msg->ipc_complete,
298 msecs_to_jiffies(sdev->ipc_timeout));
299
300 if (ret == 0) {
301 dev_err(sdev->dev,
302 "ipc tx timed out for %#x (msg/reply size: %d/%zu)\n",
303 hdr->cmd, hdr->size, msg->reply_size);
304 snd_sof_handle_fw_exception(ipc->sdev, "IPC timeout");
305 ret = -ETIMEDOUT;
306 } else {
307 ret = msg->reply_error;
308 if (ret < 0) {
309 dev_err(sdev->dev,
310 "ipc tx error for %#x (msg/reply size: %d/%zu): %d\n",
311 hdr->cmd, hdr->size, msg->reply_size, ret);
312 } else {
313 if (sof_debug_check_flag(SOF_DBG_PRINT_IPC_SUCCESS_LOGS))
314 ipc3_log_header(sdev->dev, "ipc tx succeeded", hdr->cmd);
315 if (reply_data && msg->reply_size)
316 /* copy the data returned from DSP */
317 memcpy(reply_data, msg->reply_data,
318 msg->reply_size);
319 }
320
321 /* re-enable dumps after successful IPC tx */
322 if (sdev->ipc_dump_printed) {
323 sdev->dbg_dump_printed = false;
324 sdev->ipc_dump_printed = false;
325 }
326 }
327
328 return ret;
329}
330
331/* send IPC message from host to DSP */
332static int ipc3_tx_msg_unlocked(struct snd_sof_ipc *ipc,
333 void *msg_data, size_t msg_bytes,
334 void *reply_data, size_t reply_bytes)
335{
336 struct sof_ipc_cmd_hdr *hdr = msg_data;
337 struct snd_sof_dev *sdev = ipc->sdev;
338 int ret;
339
340 ipc3_log_header(sdev->dev, "ipc tx", hdr->cmd);
341
342 ret = sof_ipc_send_msg(sdev, msg_data, msg_bytes, reply_bytes);
343
344 if (ret) {
345 dev_err_ratelimited(sdev->dev,
346 "%s: ipc message send for %#x failed: %d\n",
347 __func__, hdr->cmd, ret);
348 return ret;
349 }
350
351 /* now wait for completion */
352 return ipc3_wait_tx_done(ipc, reply_data);
353}
354
355static int sof_ipc3_tx_msg(struct snd_sof_dev *sdev, void *msg_data, size_t msg_bytes,
356 void *reply_data, size_t reply_bytes, bool no_pm)
357{
358 struct snd_sof_ipc *ipc = sdev->ipc;
359 int ret;
360
361 if (!msg_data || msg_bytes < sizeof(struct sof_ipc_cmd_hdr)) {
362 dev_err_ratelimited(sdev->dev, "No IPC message to send\n");
363 return -EINVAL;
364 }
365
366 if (!no_pm) {
367 const struct sof_dsp_power_state target_state = {
368 .state = SOF_DSP_PM_D0,
369 };
370
371 /* ensure the DSP is in D0 before sending a new IPC */
372 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
373 if (ret < 0) {
374 dev_err(sdev->dev, "%s: resuming DSP failed: %d\n",
375 __func__, ret);
376 return ret;
377 }
378 }
379
380 /* Serialise IPC TX */
381 guard(mutex)(&ipc->tx_mutex);
382
383 ret = ipc3_tx_msg_unlocked(ipc, msg_data, msg_bytes, reply_data, reply_bytes);
384
385 if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
386 size_t payload_bytes, header_bytes;
387 char *payload = NULL;
388
389 /* payload is indicated by non zero msg/reply_bytes */
390 if (msg_bytes > sizeof(struct sof_ipc_cmd_hdr)) {
391 payload = msg_data;
392
393 header_bytes = sizeof(struct sof_ipc_cmd_hdr);
394 payload_bytes = msg_bytes - header_bytes;
395 } else if (reply_bytes > sizeof(struct sof_ipc_reply)) {
396 payload = reply_data;
397
398 header_bytes = sizeof(struct sof_ipc_reply);
399 payload_bytes = reply_bytes - header_bytes;
400 }
401
402 if (payload) {
403 payload += header_bytes;
404 sof_ipc3_dump_payload(sdev, payload, payload_bytes);
405 }
406 }
407
408 return ret;
409}
410
411static int sof_ipc3_set_get_data(struct snd_sof_dev *sdev, void *data, size_t data_bytes,
412 bool set)
413{
414 size_t msg_bytes, hdr_bytes, payload_size, send_bytes;
415 struct sof_ipc_ctrl_data *cdata = data;
416 struct sof_ipc_ctrl_data *cdata_chunk;
417 struct snd_sof_ipc *ipc = sdev->ipc;
418 size_t offset = 0;
419 u8 *src, *dst;
420 u32 num_msg;
421 int ret = 0;
422 int i;
423
424 if (!cdata || data_bytes < sizeof(*cdata))
425 return -EINVAL;
426
427 if ((cdata->rhdr.hdr.cmd & SOF_GLB_TYPE_MASK) != SOF_IPC_GLB_COMP_MSG) {
428 dev_err(sdev->dev, "%s: Not supported message type of %#x\n",
429 __func__, cdata->rhdr.hdr.cmd);
430 return -EINVAL;
431 }
432
433 /* send normal size ipc in one part */
434 if (cdata->rhdr.hdr.size <= ipc->max_payload_size)
435 return sof_ipc3_tx_msg(sdev, cdata, cdata->rhdr.hdr.size,
436 cdata, cdata->rhdr.hdr.size, false);
437
438 cdata_chunk = kzalloc(ipc->max_payload_size, GFP_KERNEL);
439 if (!cdata_chunk)
440 return -ENOMEM;
441
442 switch (cdata->type) {
443 case SOF_CTRL_TYPE_VALUE_CHAN_GET:
444 case SOF_CTRL_TYPE_VALUE_CHAN_SET:
445 hdr_bytes = sizeof(struct sof_ipc_ctrl_data);
446 if (set) {
447 src = (u8 *)cdata->chanv;
448 dst = (u8 *)cdata_chunk->chanv;
449 } else {
450 src = (u8 *)cdata_chunk->chanv;
451 dst = (u8 *)cdata->chanv;
452 }
453 break;
454 case SOF_CTRL_TYPE_DATA_GET:
455 case SOF_CTRL_TYPE_DATA_SET:
456 hdr_bytes = sizeof(struct sof_ipc_ctrl_data) + sizeof(struct sof_abi_hdr);
457 if (set) {
458 src = (u8 *)cdata->data->data;
459 dst = (u8 *)cdata_chunk->data->data;
460 } else {
461 src = (u8 *)cdata_chunk->data->data;
462 dst = (u8 *)cdata->data->data;
463 }
464 break;
465 default:
466 kfree(cdata_chunk);
467 return -EINVAL;
468 }
469
470 msg_bytes = cdata->rhdr.hdr.size - hdr_bytes;
471 payload_size = ipc->max_payload_size - hdr_bytes;
472 num_msg = DIV_ROUND_UP(msg_bytes, payload_size);
473
474 /* copy the header data */
475 memcpy(cdata_chunk, cdata, hdr_bytes);
476
477 /* Serialise IPC TX */
478 guard(mutex)(&ipc->tx_mutex);
479
480 /* copy the payload data in a loop */
481 for (i = 0; i < num_msg; i++) {
482 send_bytes = min(msg_bytes, payload_size);
483 cdata_chunk->num_elems = send_bytes;
484 cdata_chunk->rhdr.hdr.size = hdr_bytes + send_bytes;
485 cdata_chunk->msg_index = i;
486 msg_bytes -= send_bytes;
487 cdata_chunk->elems_remaining = msg_bytes;
488
489 if (set)
490 memcpy(dst, src + offset, send_bytes);
491
492 ret = ipc3_tx_msg_unlocked(sdev->ipc,
493 cdata_chunk, cdata_chunk->rhdr.hdr.size,
494 cdata_chunk, cdata_chunk->rhdr.hdr.size);
495 if (ret < 0)
496 break;
497
498 if (!set)
499 memcpy(dst + offset, src, send_bytes);
500
501 offset += payload_size;
502 }
503
504 if (sof_debug_check_flag(SOF_DBG_DUMP_IPC_MESSAGE_PAYLOAD)) {
505 size_t header_bytes = sizeof(struct sof_ipc_reply);
506 char *payload = (char *)cdata;
507
508 payload += header_bytes;
509 sof_ipc3_dump_payload(sdev, payload, data_bytes - header_bytes);
510 }
511
512 kfree(cdata_chunk);
513
514 return ret;
515}
516
517int sof_ipc3_get_ext_windows(struct snd_sof_dev *sdev,
518 const struct sof_ipc_ext_data_hdr *ext_hdr)
519{
520 const struct sof_ipc_window *w =
521 container_of(ext_hdr, struct sof_ipc_window, ext_hdr);
522
523 if (w->num_windows == 0 || w->num_windows > SOF_IPC_MAX_ELEMS)
524 return -EINVAL;
525
526 if (sdev->info_window) {
527 if (memcmp(sdev->info_window, w, ext_hdr->hdr.size)) {
528 dev_err(sdev->dev, "mismatch between window descriptor from extended manifest and mailbox");
529 return -EINVAL;
530 }
531 return 0;
532 }
533
534 /* keep a local copy of the data */
535 sdev->info_window = devm_kmemdup(sdev->dev, w, ext_hdr->hdr.size, GFP_KERNEL);
536 if (!sdev->info_window)
537 return -ENOMEM;
538
539 return 0;
540}
541
542int sof_ipc3_get_cc_info(struct snd_sof_dev *sdev,
543 const struct sof_ipc_ext_data_hdr *ext_hdr)
544{
545 int ret;
546
547 const struct sof_ipc_cc_version *cc =
548 container_of(ext_hdr, struct sof_ipc_cc_version, ext_hdr);
549
550 if (sdev->cc_version) {
551 if (memcmp(sdev->cc_version, cc, cc->ext_hdr.hdr.size)) {
552 dev_err(sdev->dev,
553 "Receive diverged cc_version descriptions");
554 return -EINVAL;
555 }
556 return 0;
557 }
558
559 dev_dbg(sdev->dev,
560 "Firmware info: used compiler %s %d:%d:%d%s used optimization flags %s\n",
561 cc->name, cc->major, cc->minor, cc->micro, cc->desc, cc->optim);
562
563 /* create read-only cc_version debugfs to store compiler version info */
564 /* use local copy of the cc_version to prevent data corruption */
565 if (sdev->first_boot) {
566 sdev->cc_version = devm_kmemdup(sdev->dev, cc, cc->ext_hdr.hdr.size, GFP_KERNEL);
567 if (!sdev->cc_version)
568 return -ENOMEM;
569
570 ret = snd_sof_debugfs_buf_item(sdev, sdev->cc_version,
571 cc->ext_hdr.hdr.size,
572 "cc_version", 0444);
573
574 /* errors are only due to memory allocation, not debugfs */
575 if (ret < 0) {
576 dev_err(sdev->dev, "snd_sof_debugfs_buf_item failed\n");
577 return ret;
578 }
579 }
580
581 return 0;
582}
583
584/* parse the extended FW boot data structures from FW boot message */
585static int ipc3_fw_parse_ext_data(struct snd_sof_dev *sdev, u32 offset)
586{
587 struct sof_ipc_ext_data_hdr *ext_hdr;
588 void *ext_data;
589 int ret = 0;
590
591 ext_data = kzalloc(PAGE_SIZE, GFP_KERNEL);
592 if (!ext_data)
593 return -ENOMEM;
594
595 /* get first header */
596 snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
597 sizeof(*ext_hdr));
598 ext_hdr = ext_data;
599
600 while (ext_hdr->hdr.cmd == SOF_IPC_FW_READY) {
601 /* read in ext structure */
602 snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM,
603 offset + sizeof(*ext_hdr),
604 (void *)((u8 *)ext_data + sizeof(*ext_hdr)),
605 ext_hdr->hdr.size - sizeof(*ext_hdr));
606
607 dev_dbg(sdev->dev, "found ext header type %d size 0x%x\n",
608 ext_hdr->type, ext_hdr->hdr.size);
609
610 /* process structure data */
611 switch (ext_hdr->type) {
612 case SOF_IPC_EXT_WINDOW:
613 ret = sof_ipc3_get_ext_windows(sdev, ext_hdr);
614 break;
615 case SOF_IPC_EXT_CC_INFO:
616 ret = sof_ipc3_get_cc_info(sdev, ext_hdr);
617 break;
618 case SOF_IPC_EXT_UNUSED:
619 case SOF_IPC_EXT_PROBE_INFO:
620 case SOF_IPC_EXT_USER_ABI_INFO:
621 /* They are supported but we don't do anything here */
622 break;
623 default:
624 dev_info(sdev->dev, "unknown ext header type %d size 0x%x\n",
625 ext_hdr->type, ext_hdr->hdr.size);
626 ret = 0;
627 break;
628 }
629
630 if (ret < 0) {
631 dev_err(sdev->dev, "Failed to parse ext data type %d\n",
632 ext_hdr->type);
633 break;
634 }
635
636 /* move to next header */
637 offset += ext_hdr->hdr.size;
638 snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, ext_data,
639 sizeof(*ext_hdr));
640 ext_hdr = ext_data;
641 }
642
643 kfree(ext_data);
644 return ret;
645}
646
647static void ipc3_get_windows(struct snd_sof_dev *sdev)
648{
649 struct sof_ipc_window_elem *elem;
650 u32 outbox_offset = 0;
651 u32 stream_offset = 0;
652 u32 inbox_offset = 0;
653 u32 outbox_size = 0;
654 u32 stream_size = 0;
655 u32 inbox_size = 0;
656 u32 debug_size = 0;
657 u32 debug_offset = 0;
658 int window_offset;
659 int i;
660
661 if (!sdev->info_window) {
662 dev_err(sdev->dev, "%s: No window info present\n", __func__);
663 return;
664 }
665
666 for (i = 0; i < sdev->info_window->num_windows; i++) {
667 elem = &sdev->info_window->window[i];
668
669 window_offset = snd_sof_dsp_get_window_offset(sdev, elem->id);
670 if (window_offset < 0) {
671 dev_warn(sdev->dev, "No offset for window %d\n", elem->id);
672 continue;
673 }
674
675 switch (elem->type) {
676 case SOF_IPC_REGION_UPBOX:
677 inbox_offset = window_offset + elem->offset;
678 inbox_size = elem->size;
679 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
680 inbox_offset,
681 elem->size, "inbox",
682 SOF_DEBUGFS_ACCESS_D0_ONLY);
683 break;
684 case SOF_IPC_REGION_DOWNBOX:
685 outbox_offset = window_offset + elem->offset;
686 outbox_size = elem->size;
687 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
688 outbox_offset,
689 elem->size, "outbox",
690 SOF_DEBUGFS_ACCESS_D0_ONLY);
691 break;
692 case SOF_IPC_REGION_TRACE:
693 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
694 window_offset + elem->offset,
695 elem->size, "etrace",
696 SOF_DEBUGFS_ACCESS_D0_ONLY);
697 break;
698 case SOF_IPC_REGION_DEBUG:
699 debug_offset = window_offset + elem->offset;
700 debug_size = elem->size;
701 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
702 window_offset + elem->offset,
703 elem->size, "debug",
704 SOF_DEBUGFS_ACCESS_D0_ONLY);
705 break;
706 case SOF_IPC_REGION_STREAM:
707 stream_offset = window_offset + elem->offset;
708 stream_size = elem->size;
709 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
710 stream_offset,
711 elem->size, "stream",
712 SOF_DEBUGFS_ACCESS_D0_ONLY);
713 break;
714 case SOF_IPC_REGION_REGS:
715 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
716 window_offset + elem->offset,
717 elem->size, "regs",
718 SOF_DEBUGFS_ACCESS_D0_ONLY);
719 break;
720 case SOF_IPC_REGION_EXCEPTION:
721 sdev->dsp_oops_offset = window_offset + elem->offset;
722 snd_sof_debugfs_add_region_item(sdev, SOF_FW_BLK_TYPE_SRAM,
723 window_offset + elem->offset,
724 elem->size, "exception",
725 SOF_DEBUGFS_ACCESS_D0_ONLY);
726 break;
727 default:
728 dev_err(sdev->dev, "%s: Illegal window info: %u\n",
729 __func__, elem->type);
730 return;
731 }
732 }
733
734 if (outbox_size == 0 || inbox_size == 0) {
735 dev_err(sdev->dev, "%s: Illegal mailbox window\n", __func__);
736 return;
737 }
738
739 sdev->dsp_box.offset = inbox_offset;
740 sdev->dsp_box.size = inbox_size;
741
742 sdev->host_box.offset = outbox_offset;
743 sdev->host_box.size = outbox_size;
744
745 sdev->stream_box.offset = stream_offset;
746 sdev->stream_box.size = stream_size;
747
748 sdev->debug_box.offset = debug_offset;
749 sdev->debug_box.size = debug_size;
750
751 dev_dbg(sdev->dev, " mailbox upstream 0x%x - size 0x%x\n",
752 inbox_offset, inbox_size);
753 dev_dbg(sdev->dev, " mailbox downstream 0x%x - size 0x%x\n",
754 outbox_offset, outbox_size);
755 dev_dbg(sdev->dev, " stream region 0x%x - size 0x%x\n",
756 stream_offset, stream_size);
757 dev_dbg(sdev->dev, " debug region 0x%x - size 0x%x\n",
758 debug_offset, debug_size);
759}
760
761static int ipc3_init_reply_data_buffer(struct snd_sof_dev *sdev)
762{
763 struct snd_sof_ipc_msg *msg = &sdev->ipc->msg;
764
765 msg->reply_data = devm_kzalloc(sdev->dev, SOF_IPC_MSG_MAX_SIZE, GFP_KERNEL);
766 if (!msg->reply_data)
767 return -ENOMEM;
768
769 sdev->ipc->max_payload_size = SOF_IPC_MSG_MAX_SIZE;
770
771 return 0;
772}
773
774int sof_ipc3_validate_fw_version(struct snd_sof_dev *sdev)
775{
776 struct sof_ipc_fw_ready *ready = &sdev->fw_ready;
777 struct sof_ipc_fw_version *v = &ready->version;
778
779 dev_info(sdev->dev,
780 "Firmware info: version %d:%d:%d-%s\n", v->major, v->minor,
781 v->micro, v->tag);
782 dev_info(sdev->dev,
783 "Firmware: ABI %d:%d:%d Kernel ABI %d:%d:%d\n",
784 SOF_ABI_VERSION_MAJOR(v->abi_version),
785 SOF_ABI_VERSION_MINOR(v->abi_version),
786 SOF_ABI_VERSION_PATCH(v->abi_version),
787 SOF_ABI_MAJOR, SOF_ABI_MINOR, SOF_ABI_PATCH);
788
789 if (SOF_ABI_VERSION_INCOMPATIBLE(SOF_ABI_VERSION, v->abi_version)) {
790 dev_err(sdev->dev, "incompatible FW ABI version\n");
791 return -EINVAL;
792 }
793
794 if (IS_ENABLED(CONFIG_SND_SOC_SOF_STRICT_ABI_CHECKS) &&
795 SOF_ABI_VERSION_MINOR(v->abi_version) > SOF_ABI_MINOR) {
796 dev_err(sdev->dev, "FW ABI is more recent than kernel\n");
797 return -EINVAL;
798 }
799
800 if (ready->flags & SOF_IPC_INFO_BUILD)
801 dev_info(sdev->dev,
802 "Firmware debug build %d on %s-%s - options:\n"
803 " GDB: %s\n"
804 " lock debug: %s\n"
805 " lock vdebug: %s\n",
806 v->build, v->date, v->time,
807 str_enabled_disabled(ready->flags & SOF_IPC_INFO_GDB),
808 str_enabled_disabled(ready->flags & SOF_IPC_INFO_LOCKS),
809 str_enabled_disabled(ready->flags & SOF_IPC_INFO_LOCKSV));
810
811 /* copy the fw_version into debugfs at first boot */
812 memcpy(&sdev->fw_version, v, sizeof(*v));
813
814 return 0;
815}
816
817static int ipc3_fw_ready(struct snd_sof_dev *sdev, u32 cmd)
818{
819 struct sof_ipc_fw_ready *fw_ready = &sdev->fw_ready;
820 int offset;
821 int ret;
822
823 /* mailbox must be on 4k boundary */
824 offset = snd_sof_dsp_get_mailbox_offset(sdev);
825 if (offset < 0) {
826 dev_err(sdev->dev, "%s: no mailbox offset\n", __func__);
827 return offset;
828 }
829
830 dev_dbg(sdev->dev, "DSP is ready 0x%8.8x offset 0x%x\n", cmd, offset);
831
832 /* no need to re-check version/ABI for subsequent boots */
833 if (!sdev->first_boot)
834 return 0;
835
836 /*
837 * copy data from the DSP FW ready offset
838 * Subsequent error handling is not needed for BLK_TYPE_SRAM
839 */
840 ret = snd_sof_dsp_block_read(sdev, SOF_FW_BLK_TYPE_SRAM, offset, fw_ready,
841 sizeof(*fw_ready));
842 if (ret) {
843 dev_err(sdev->dev,
844 "Unable to read fw_ready, read from TYPE_SRAM failed\n");
845 return ret;
846 }
847
848 /* make sure ABI version is compatible */
849 ret = sof_ipc3_validate_fw_version(sdev);
850 if (ret < 0)
851 return ret;
852
853 /* now check for extended data */
854 ipc3_fw_parse_ext_data(sdev, offset + sizeof(struct sof_ipc_fw_ready));
855
856 ipc3_get_windows(sdev);
857
858 return ipc3_init_reply_data_buffer(sdev);
859}
860
861/* IPC stream position. */
862static void ipc3_period_elapsed(struct snd_sof_dev *sdev, u32 msg_id)
863{
864 struct snd_soc_component *scomp = sdev->component;
865 struct snd_sof_pcm_stream *stream;
866 struct sof_ipc_stream_posn posn;
867 struct snd_sof_pcm *spcm;
868 int direction, ret;
869
870 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
871 if (!spcm) {
872 dev_err(sdev->dev, "period elapsed for unknown stream, msg_id %d\n",
873 msg_id);
874 return;
875 }
876
877 stream = &spcm->stream[direction];
878 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
879 if (ret < 0) {
880 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
881 return;
882 }
883
884 trace_sof_ipc3_period_elapsed_position(sdev, &posn);
885
886 memcpy(&stream->posn, &posn, sizeof(posn));
887
888 if (spcm->pcm.compress)
889 snd_sof_compr_fragment_elapsed(stream->cstream);
890 else if (stream->substream->runtime &&
891 !stream->substream->runtime->no_period_wakeup)
892 /* only inform ALSA for period_wakeup mode */
893 snd_sof_pcm_period_elapsed(stream->substream);
894}
895
896/* DSP notifies host of an XRUN within FW */
897static void ipc3_xrun(struct snd_sof_dev *sdev, u32 msg_id)
898{
899 struct snd_soc_component *scomp = sdev->component;
900 struct snd_sof_pcm_stream *stream;
901 struct sof_ipc_stream_posn posn;
902 struct snd_sof_pcm *spcm;
903 int direction, ret;
904
905 spcm = snd_sof_find_spcm_comp(scomp, msg_id, &direction);
906 if (!spcm) {
907 dev_err(sdev->dev, "XRUN for unknown stream, msg_id %d\n",
908 msg_id);
909 return;
910 }
911
912 stream = &spcm->stream[direction];
913 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
914 if (ret < 0) {
915 dev_warn(sdev->dev, "failed to read overrun position: %d\n", ret);
916 return;
917 }
918
919 dev_dbg(sdev->dev, "posn XRUN: host %llx comp %d size %d\n",
920 posn.host_posn, posn.xrun_comp_id, posn.xrun_size);
921
922#if defined(CONFIG_SND_SOC_SOF_DEBUG_XRUN_STOP)
923 /* stop PCM on XRUN - used for pipeline debug */
924 memcpy(&stream->posn, &posn, sizeof(posn));
925 snd_pcm_stop_xrun(stream->substream);
926#endif
927}
928
929/* stream notifications from firmware */
930static void ipc3_stream_message(struct snd_sof_dev *sdev, void *msg_buf)
931{
932 struct sof_ipc_cmd_hdr *hdr = msg_buf;
933 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
934 u32 msg_id = SOF_IPC_MESSAGE_ID(hdr->cmd);
935
936 switch (msg_type) {
937 case SOF_IPC_STREAM_POSITION:
938 ipc3_period_elapsed(sdev, msg_id);
939 break;
940 case SOF_IPC_STREAM_TRIG_XRUN:
941 ipc3_xrun(sdev, msg_id);
942 break;
943 default:
944 dev_err(sdev->dev, "unhandled stream message %#x\n",
945 msg_id);
946 break;
947 }
948}
949
950/* component notifications from firmware */
951static void ipc3_comp_notification(struct snd_sof_dev *sdev, void *msg_buf)
952{
953 const struct sof_ipc_tplg_ops *tplg_ops = sdev->ipc->ops->tplg;
954 struct sof_ipc_cmd_hdr *hdr = msg_buf;
955 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
956
957 switch (msg_type) {
958 case SOF_IPC_COMP_GET_VALUE:
959 case SOF_IPC_COMP_GET_DATA:
960 break;
961 default:
962 dev_err(sdev->dev, "unhandled component message %#x\n", msg_type);
963 return;
964 }
965
966 if (tplg_ops->control->update)
967 tplg_ops->control->update(sdev, msg_buf);
968}
969
970static void ipc3_trace_message(struct snd_sof_dev *sdev, void *msg_buf)
971{
972 struct sof_ipc_cmd_hdr *hdr = msg_buf;
973 u32 msg_type = hdr->cmd & SOF_CMD_TYPE_MASK;
974
975 switch (msg_type) {
976 case SOF_IPC_TRACE_DMA_POSITION:
977 ipc3_dtrace_posn_update(sdev, msg_buf);
978 break;
979 default:
980 dev_err(sdev->dev, "unhandled trace message %#x\n", msg_type);
981 break;
982 }
983}
984
985void sof_ipc3_do_rx_work(struct snd_sof_dev *sdev, struct sof_ipc_cmd_hdr *hdr, void *msg_buf)
986{
987 ipc3_rx_callback rx_callback = NULL;
988 u32 cmd;
989 int err;
990
991 ipc3_log_header(sdev->dev, "ipc rx", hdr->cmd);
992
993 if (hdr->size < sizeof(*hdr) || hdr->size > SOF_IPC_MSG_MAX_SIZE) {
994 dev_err(sdev->dev, "The received message size is invalid: %u\n",
995 hdr->size);
996 return;
997 }
998
999 cmd = hdr->cmd & SOF_GLB_TYPE_MASK;
1000
1001 /* check message type */
1002 switch (cmd) {
1003 case SOF_IPC_GLB_REPLY:
1004 dev_err(sdev->dev, "ipc reply unknown\n");
1005 break;
1006 case SOF_IPC_FW_READY:
1007 /* check for FW boot completion */
1008 if (sdev->fw_state == SOF_FW_BOOT_IN_PROGRESS) {
1009 err = ipc3_fw_ready(sdev, cmd);
1010 if (err < 0)
1011 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_FAILED);
1012 else
1013 sof_set_fw_state(sdev, SOF_FW_BOOT_READY_OK);
1014
1015 /* wake up firmware loader */
1016 wake_up(&sdev->boot_wait);
1017 }
1018 break;
1019 case SOF_IPC_GLB_COMPOUND:
1020 case SOF_IPC_GLB_TPLG_MSG:
1021 case SOF_IPC_GLB_PM_MSG:
1022 break;
1023 case SOF_IPC_GLB_COMP_MSG:
1024 rx_callback = ipc3_comp_notification;
1025 break;
1026 case SOF_IPC_GLB_STREAM_MSG:
1027 rx_callback = ipc3_stream_message;
1028 break;
1029 case SOF_IPC_GLB_TRACE_MSG:
1030 rx_callback = ipc3_trace_message;
1031 break;
1032 default:
1033 dev_err(sdev->dev, "%s: Unknown DSP message: 0x%x\n", __func__, cmd);
1034 break;
1035 }
1036
1037 /* Call local handler for the message */
1038 if (rx_callback)
1039 rx_callback(sdev, msg_buf);
1040
1041 /* Notify registered clients */
1042 sof_client_ipc_rx_dispatcher(sdev, msg_buf);
1043
1044 ipc3_log_header(sdev->dev, "ipc rx done", hdr->cmd);
1045}
1046EXPORT_SYMBOL(sof_ipc3_do_rx_work);
1047
1048/* DSP firmware has sent host a message */
1049static void sof_ipc3_rx_msg(struct snd_sof_dev *sdev)
1050{
1051 struct sof_ipc_cmd_hdr hdr;
1052 void *msg_buf;
1053 int err;
1054
1055 /* read back header */
1056 err = snd_sof_ipc_msg_data(sdev, NULL, &hdr, sizeof(hdr));
1057 if (err < 0) {
1058 dev_warn(sdev->dev, "failed to read IPC header: %d\n", err);
1059 return;
1060 }
1061
1062 if (hdr.size < sizeof(hdr) || hdr.size > SOF_IPC_MSG_MAX_SIZE) {
1063 dev_err(sdev->dev, "The received message size is invalid\n");
1064 return;
1065 }
1066
1067 /* read the full message */
1068 msg_buf = kmalloc(hdr.size, GFP_KERNEL);
1069 if (!msg_buf)
1070 return;
1071
1072 err = snd_sof_ipc_msg_data(sdev, NULL, msg_buf, hdr.size);
1073 if (err < 0) {
1074 dev_err(sdev->dev, "%s: Failed to read message: %d\n", __func__, err);
1075 kfree(msg_buf);
1076 return;
1077 }
1078
1079 sof_ipc3_do_rx_work(sdev, &hdr, msg_buf);
1080
1081 kfree(msg_buf);
1082}
1083
1084static int sof_ipc3_set_core_state(struct snd_sof_dev *sdev, int core_idx, bool on)
1085{
1086 struct sof_ipc_pm_core_config core_cfg = {
1087 .hdr.size = sizeof(core_cfg),
1088 .hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
1089 };
1090
1091 if (on)
1092 core_cfg.enable_mask = sdev->enabled_cores_mask | BIT(core_idx);
1093 else
1094 core_cfg.enable_mask = sdev->enabled_cores_mask & ~BIT(core_idx);
1095
1096 return sof_ipc3_tx_msg(sdev, &core_cfg, sizeof(core_cfg), NULL, 0, false);
1097}
1098
1099static int sof_ipc3_ctx_ipc(struct snd_sof_dev *sdev, int cmd)
1100{
1101 struct sof_ipc_pm_ctx pm_ctx = {
1102 .hdr.size = sizeof(pm_ctx),
1103 .hdr.cmd = SOF_IPC_GLB_PM_MSG | cmd,
1104 };
1105
1106 /* send ctx save ipc to dsp */
1107 return sof_ipc3_tx_msg(sdev, &pm_ctx, sizeof(pm_ctx), NULL, 0, false);
1108}
1109
1110static int sof_ipc3_ctx_save(struct snd_sof_dev *sdev)
1111{
1112 return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_SAVE);
1113}
1114
1115static int sof_ipc3_ctx_restore(struct snd_sof_dev *sdev)
1116{
1117 return sof_ipc3_ctx_ipc(sdev, SOF_IPC_PM_CTX_RESTORE);
1118}
1119
1120static int sof_ipc3_set_pm_gate(struct snd_sof_dev *sdev, u32 flags)
1121{
1122 struct sof_ipc_pm_gate pm_gate;
1123
1124 memset(&pm_gate, 0, sizeof(pm_gate));
1125
1126 /* configure pm_gate ipc message */
1127 pm_gate.hdr.size = sizeof(pm_gate);
1128 pm_gate.hdr.cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_GATE;
1129 pm_gate.flags = flags;
1130
1131 /* send pm_gate ipc to dsp */
1132 return sof_ipc_tx_message_no_pm_no_reply(sdev->ipc, &pm_gate, sizeof(pm_gate));
1133}
1134
1135static const struct sof_ipc_pm_ops ipc3_pm_ops = {
1136 .ctx_save = sof_ipc3_ctx_save,
1137 .ctx_restore = sof_ipc3_ctx_restore,
1138 .set_core_state = sof_ipc3_set_core_state,
1139 .set_pm_gate = sof_ipc3_set_pm_gate,
1140};
1141
1142const struct sof_ipc_ops ipc3_ops = {
1143 .tplg = &ipc3_tplg_ops,
1144 .pm = &ipc3_pm_ops,
1145 .pcm = &ipc3_pcm_ops,
1146 .fw_loader = &ipc3_loader_ops,
1147 .fw_tracing = &ipc3_dtrace_ops,
1148
1149 .tx_msg = sof_ipc3_tx_msg,
1150 .rx_msg = sof_ipc3_rx_msg,
1151 .set_get_data = sof_ipc3_set_get_data,
1152 .get_reply = sof_ipc3_get_reply,
1153};