projects/linux·blob master · refs

209 lines · 7.2 KiB

1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 * Copyright (C) 2013 Cavium, Inc.
9 * Authors: Sanjay Lal <[email protected]>
10 */
11
12#ifndef __LINUX_KVM_MIPS_H
13#define __LINUX_KVM_MIPS_H
14
15#include <linux/types.h>
16
17/*
18 * KVM MIPS specific structures and definitions.
19 *
20 * Some parts derived from the x86 version of this file.
21 */
22
23/*
24 * for KVM_GET_REGS and KVM_SET_REGS
25 *
26 * If Config[AT] is zero (32-bit CPU), the register contents are
27 * stored in the lower 32-bits of the struct kvm_regs fields and sign
28 * extended to 64-bits.
29 */
30struct kvm_regs {
31 /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
32 __u64 gpr[32];
33 __u64 hi;
34 __u64 lo;
35 __u64 pc;
36};
37
38/*
39 * for KVM_GET_FPU and KVM_SET_FPU
40 */
41struct kvm_fpu {
42};
43
44
45/*
46 * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
47 * registers. The id field is broken down as follows:
48 *
49 * bits[63..52] - As per linux/kvm.h
50 * bits[51..32] - Must be zero.
51 * bits[31..16] - Register set.
52 *
53 * Register set = 0: GP registers from kvm_regs (see definitions below).
54 *
55 * Register set = 1: CP0 registers.
56 * bits[15..8] - Must be zero.
57 * bits[7..3] - Register 'rd' index.
58 * bits[2..0] - Register 'sel' index.
59 *
60 * Register set = 2: KVM specific registers (see definitions below).
61 *
62 * Register set = 3: FPU / MSA registers (see definitions below).
63 *
64 * Other sets registers may be added in the future. Each set would
65 * have its own identifier in bits[31..16].
66 */
67
68#define KVM_REG_MIPS_GP (KVM_REG_MIPS | 0x0000000000000000ULL)
69#define KVM_REG_MIPS_CP0 (KVM_REG_MIPS | 0x0000000000010000ULL)
70#define KVM_REG_MIPS_KVM (KVM_REG_MIPS | 0x0000000000020000ULL)
71#define KVM_REG_MIPS_FPU (KVM_REG_MIPS | 0x0000000000030000ULL)
72
73
74/*
75 * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
76 */
77
78#define KVM_REG_MIPS_R0 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 0)
79#define KVM_REG_MIPS_R1 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 1)
80#define KVM_REG_MIPS_R2 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 2)
81#define KVM_REG_MIPS_R3 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 3)
82#define KVM_REG_MIPS_R4 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 4)
83#define KVM_REG_MIPS_R5 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 5)
84#define KVM_REG_MIPS_R6 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 6)
85#define KVM_REG_MIPS_R7 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 7)
86#define KVM_REG_MIPS_R8 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 8)
87#define KVM_REG_MIPS_R9 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 9)
88#define KVM_REG_MIPS_R10 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
89#define KVM_REG_MIPS_R11 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
90#define KVM_REG_MIPS_R12 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
91#define KVM_REG_MIPS_R13 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
92#define KVM_REG_MIPS_R14 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
93#define KVM_REG_MIPS_R15 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
94#define KVM_REG_MIPS_R16 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
95#define KVM_REG_MIPS_R17 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
96#define KVM_REG_MIPS_R18 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
97#define KVM_REG_MIPS_R19 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
98#define KVM_REG_MIPS_R20 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
99#define KVM_REG_MIPS_R21 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
100#define KVM_REG_MIPS_R22 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
101#define KVM_REG_MIPS_R23 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
102#define KVM_REG_MIPS_R24 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
103#define KVM_REG_MIPS_R25 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
104#define KVM_REG_MIPS_R26 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
105#define KVM_REG_MIPS_R27 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
106#define KVM_REG_MIPS_R28 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
107#define KVM_REG_MIPS_R29 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
108#define KVM_REG_MIPS_R30 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
109#define KVM_REG_MIPS_R31 (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
110
111#define KVM_REG_MIPS_HI (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
112#define KVM_REG_MIPS_LO (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
113#define KVM_REG_MIPS_PC (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
114
115
116/*
117 * KVM_REG_MIPS_KVM - KVM specific control registers.
118 */
119
120/*
121 * CP0_Count control
122 * DC: Set 0: Master disable CP0_Count and set COUNT_RESUME to now
123 * Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
124 * interrupts since COUNT_RESUME
125 * This can be used to freeze the timer to get a consistent snapshot of
126 * the CP0_Count and timer interrupt pending state, while also resuming
127 * safely without losing time or guest timer interrupts.
128 * Other: Reserved, do not change.
129 */
130#define KVM_REG_MIPS_COUNT_CTL (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
131#define KVM_REG_MIPS_COUNT_CTL_DC 0x00000001
132
133/*
134 * CP0_Count resume monotonic nanoseconds
135 * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
136 * disable). Any reads and writes of Count related registers while
137 * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
138 * cleared again (master enable) any timer interrupts since this time will be
139 * emulated.
140 * Modifications to times in the future are rejected.
141 */
142#define KVM_REG_MIPS_COUNT_RESUME (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
143/*
144 * CP0_Count rate in Hz
145 * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
146 * discontinuities in CP0_Count.
147 */
148#define KVM_REG_MIPS_COUNT_HZ (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
149
150
151/*
152 * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
153 *
154 * bits[15..8] - Register subset (see definitions below).
155 * bits[7..5] - Must be zero.
156 * bits[4..0] - Register number within register subset.
157 */
158
159#define KVM_REG_MIPS_FPR (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
160#define KVM_REG_MIPS_FCR (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
161#define KVM_REG_MIPS_MSACR (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
162
163/*
164 * KVM_REG_MIPS_FPR - Floating point / Vector registers.
165 */
166#define KVM_REG_MIPS_FPR_32(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32 | (n))
167#define KVM_REG_MIPS_FPR_64(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64 | (n))
168#define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
169
170/*
171 * KVM_REG_MIPS_FCR - Floating point control registers.
172 */
173#define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 0)
174#define KVM_REG_MIPS_FCR_CSR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
175
176/*
177 * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
178 */
179#define KVM_REG_MIPS_MSA_IR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 0)
180#define KVM_REG_MIPS_MSA_CSR (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 | 1)
181
182
183/*
184 * KVM MIPS specific structures and definitions
185 *
186 */
187struct kvm_debug_exit_arch {
188 __u64 epc;
189};
190
191/* for KVM_SET_GUEST_DEBUG */
192struct kvm_guest_debug_arch {
193};
194
195/* definition of registers in kvm_run */
196struct kvm_sync_regs {
197};
198
199/* dummy definition */
200struct kvm_sregs {
201};
202
203struct kvm_mips_interrupt {
204 /* in */
205 __u32 cpu;
206 __u32 irq;
207};
208
209#endif /* __LINUX_KVM_MIPS_H */