| 1 | {
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| 2 | "add+sub+mul",
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| 3 | .insns = {
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| 4 | BPF_MOV64_IMM(BPF_REG_1, 1),
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| 5 | BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, 2),
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| 6 | BPF_MOV64_IMM(BPF_REG_2, 3),
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| 7 | BPF_ALU64_REG(BPF_SUB, BPF_REG_1, BPF_REG_2),
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| 8 | BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, -1),
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| 9 | BPF_ALU64_IMM(BPF_MUL, BPF_REG_1, 3),
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| 10 | BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
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| 11 | BPF_EXIT_INSN(),
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| 12 | },
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| 13 | .result = ACCEPT,
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| 14 | .retval = -3,
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| 15 | },
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| 16 | {
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| 17 | "xor32 zero extend check",
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| 18 | .insns = {
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| 19 | BPF_MOV32_IMM(BPF_REG_2, -1),
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| 20 | BPF_ALU64_IMM(BPF_LSH, BPF_REG_2, 32),
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| 21 | BPF_ALU64_IMM(BPF_OR, BPF_REG_2, 0xffff),
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| 22 | BPF_ALU32_REG(BPF_XOR, BPF_REG_2, BPF_REG_2),
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| 23 | BPF_MOV32_IMM(BPF_REG_0, 2),
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| 24 | BPF_JMP_IMM(BPF_JNE, BPF_REG_2, 0, 1),
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| 25 | BPF_MOV32_IMM(BPF_REG_0, 1),
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| 26 | BPF_EXIT_INSN(),
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| 27 | },
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| 28 | .prog_type = BPF_PROG_TYPE_SCHED_CLS,
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| 29 | .result = ACCEPT,
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| 30 | .retval = 1,
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| 31 | },
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| 32 | {
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| 33 | "arsh32 on imm",
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| 34 | .insns = {
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| 35 | BPF_MOV64_IMM(BPF_REG_0, 1),
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| 36 | BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5),
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| 37 | BPF_EXIT_INSN(),
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| 38 | },
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| 39 | .result = ACCEPT,
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| 40 | .retval = 0,
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| 41 | },
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| 42 | {
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| 43 | "arsh32 on imm 2",
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| 44 | .insns = {
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| 45 | BPF_LD_IMM64(BPF_REG_0, 0x1122334485667788),
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| 46 | BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 7),
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| 47 | BPF_EXIT_INSN(),
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| 48 | },
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| 49 | .result = ACCEPT,
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| 50 | .retval = -16069393,
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| 51 | },
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| 52 | {
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| 53 | "arsh32 on reg",
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| 54 | .insns = {
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| 55 | BPF_MOV64_IMM(BPF_REG_0, 1),
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| 56 | BPF_MOV64_IMM(BPF_REG_1, 5),
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| 57 | BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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| 58 | BPF_EXIT_INSN(),
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| 59 | },
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| 60 | .result = ACCEPT,
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| 61 | .retval = 0,
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| 62 | },
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| 63 | {
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| 64 | "arsh32 on reg 2",
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| 65 | .insns = {
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| 66 | BPF_LD_IMM64(BPF_REG_0, 0xffff55667788),
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| 67 | BPF_MOV64_IMM(BPF_REG_1, 15),
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| 68 | BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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| 69 | BPF_EXIT_INSN(),
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| 70 | },
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| 71 | .result = ACCEPT,
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| 72 | .retval = 43724,
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| 73 | },
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| 74 | {
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| 75 | "arsh64 on imm",
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| 76 | .insns = {
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| 77 | BPF_MOV64_IMM(BPF_REG_0, 1),
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| 78 | BPF_ALU64_IMM(BPF_ARSH, BPF_REG_0, 5),
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| 79 | BPF_EXIT_INSN(),
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| 80 | },
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| 81 | .result = ACCEPT,
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| 82 | },
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| 83 | {
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| 84 | "arsh64 on reg",
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| 85 | .insns = {
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| 86 | BPF_MOV64_IMM(BPF_REG_0, 1),
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| 87 | BPF_MOV64_IMM(BPF_REG_1, 5),
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| 88 | BPF_ALU64_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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| 89 | BPF_EXIT_INSN(),
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| 90 | },
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| 91 | .result = ACCEPT,
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| 92 | },
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| 93 | {
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| 94 | "lsh64 by 0 imm",
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| 95 | .insns = {
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| 96 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 97 | BPF_LD_IMM64(BPF_REG_1, 1),
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| 98 | BPF_ALU64_IMM(BPF_LSH, BPF_REG_1, 0),
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| 99 | BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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| 100 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 101 | BPF_EXIT_INSN(),
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| 102 | },
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| 103 | .result = ACCEPT,
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| 104 | .retval = 1,
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| 105 | },
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| 106 | {
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| 107 | "rsh64 by 0 imm",
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| 108 | .insns = {
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| 109 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 110 | BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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| 111 | BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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| 112 | BPF_ALU64_IMM(BPF_RSH, BPF_REG_1, 0),
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| 113 | BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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| 114 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 115 | BPF_EXIT_INSN(),
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| 116 | },
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| 117 | .result = ACCEPT,
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| 118 | .retval = 1,
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| 119 | },
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| 120 | {
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| 121 | "arsh64 by 0 imm",
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| 122 | .insns = {
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| 123 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 124 | BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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| 125 | BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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| 126 | BPF_ALU64_IMM(BPF_ARSH, BPF_REG_1, 0),
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| 127 | BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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| 128 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 129 | BPF_EXIT_INSN(),
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| 130 | },
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| 131 | .result = ACCEPT,
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| 132 | .retval = 1,
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| 133 | },
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| 134 | {
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| 135 | "lsh64 by 0 reg",
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| 136 | .insns = {
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| 137 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 138 | BPF_LD_IMM64(BPF_REG_1, 1),
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| 139 | BPF_LD_IMM64(BPF_REG_2, 0),
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| 140 | BPF_ALU64_REG(BPF_LSH, BPF_REG_1, BPF_REG_2),
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| 141 | BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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| 142 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 143 | BPF_EXIT_INSN(),
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| 144 | },
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| 145 | .result = ACCEPT,
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| 146 | .retval = 1,
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| 147 | },
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| 148 | {
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| 149 | "rsh64 by 0 reg",
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| 150 | .insns = {
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| 151 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 152 | BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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| 153 | BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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| 154 | BPF_LD_IMM64(BPF_REG_3, 0),
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| 155 | BPF_ALU64_REG(BPF_RSH, BPF_REG_1, BPF_REG_3),
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| 156 | BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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| 157 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 158 | BPF_EXIT_INSN(),
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| 159 | },
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| 160 | .result = ACCEPT,
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| 161 | .retval = 1,
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| 162 | },
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| 163 | {
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| 164 | "arsh64 by 0 reg",
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| 165 | .insns = {
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| 166 | BPF_LD_IMM64(BPF_REG_0, 1),
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| 167 | BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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| 168 | BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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| 169 | BPF_LD_IMM64(BPF_REG_3, 0),
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| 170 | BPF_ALU64_REG(BPF_ARSH, BPF_REG_1, BPF_REG_3),
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| 171 | BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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| 172 | BPF_MOV64_IMM(BPF_REG_0, 2),
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| 173 | BPF_EXIT_INSN(),
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| 174 | },
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| 175 | .result = ACCEPT,
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| 176 | .retval = 1,
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| 177 | },
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| 178 | {
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| 179 | "invalid 64-bit BPF_END with BPF_TO_BE",
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| 180 | .insns = {
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| 181 | BPF_MOV32_IMM(BPF_REG_0, 0),
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| 182 | {
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| 183 | .code = BPF_ALU64 | BPF_END | BPF_TO_BE,
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| 184 | .dst_reg = BPF_REG_0,
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| 185 | .src_reg = 0,
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| 186 | .off = 0,
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| 187 | .imm = 32,
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| 188 | },
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| 189 | BPF_EXIT_INSN(),
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| 190 | },
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| 191 | .errstr = "unknown opcode df",
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| 192 | .result = REJECT,
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| 193 | },
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| 194 | {
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| 195 | "mov64 src == dst",
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| 196 | .insns = {
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| 197 | BPF_MOV64_IMM(BPF_REG_2, 0),
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| 198 | BPF_MOV64_REG(BPF_REG_2, BPF_REG_2),
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| 199 | |
| 200 | BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
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| 201 | BPF_MOV64_IMM(BPF_REG_0, 0),
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| 202 | BPF_EXIT_INSN(),
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| 203 | },
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| 204 | .prog_type = BPF_PROG_TYPE_SCHED_CLS,
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| 205 | .result = ACCEPT,
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| 206 | },
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| 207 | {
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| 208 | "mov64 src != dst",
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| 209 | .insns = {
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| 210 | BPF_MOV64_IMM(BPF_REG_3, 0),
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| 211 | BPF_MOV64_REG(BPF_REG_2, BPF_REG_3),
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| 212 | |
| 213 | BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
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| 214 | BPF_MOV64_IMM(BPF_REG_0, 0),
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| 215 | BPF_EXIT_INSN(),
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| 216 | },
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| 217 | .prog_type = BPF_PROG_TYPE_SCHED_CLS,
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| 218 | .result = ACCEPT,
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| 219 | },
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