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| 3 | |
| 4 | * Copyright 2018 IBM Corporation.
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| 7 | #ifndef _SELFTESTS_POWERPC_SECURITY_FLUSH_UTILS_H
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| 8 | #define _SELFTESTS_POWERPC_SECURITY_FLUSH_UTILS_H
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| 9 |
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| 10 | #define CACHELINE_SIZE 128
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| 11 |
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| 12 | #define PERF_L1D_READ_MISS_CONFIG ((PERF_COUNT_HW_CACHE_L1D) | \
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| 13 | (PERF_COUNT_HW_CACHE_OP_READ << 8) | \
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| 14 | (PERF_COUNT_HW_CACHE_RESULT_MISS << 16))
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| 15 |
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| 16 | void syscall_loop(char *p, unsigned long iterations,
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| 17 | unsigned long zero_size);
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| 18 |
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| 19 | void syscall_loop_uaccess(char *p, unsigned long iterations,
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| 20 | unsigned long zero_size);
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| 21 |
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| 22 | void set_dscr(unsigned long val);
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| 23 |
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| 24 | #endif
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