projects/linux·blob uaccess-cleanups · refs

2399 lines · 68.6 KiB

1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <[email protected]>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34#define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36#include <linux/delay.h>
37#include <linux/iopoll.h>
38#include <linux/ktime.h>
39#include <linux/rwsem.h>
40#include <linux/wait.h>
41#include <linux/topology.h>
42#include <linux/dmi.h>
43#include <linux/units.h>
44#include <linux/unaligned.h>
45
46#include <acpi/cppc_acpi.h>
47
48struct cppc_pcc_data {
49 struct pcc_mbox_chan *pcc_channel;
50 bool pcc_channel_acquired;
51 unsigned int deadline_us;
52 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
53
54 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
55 bool platform_owns_pcc; /* Ownership of PCC subspace */
56 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
57
58 /*
59 * Lock to provide controlled access to the PCC channel.
60 *
61 * For performance critical usecases(currently cppc_set_perf)
62 * We need to take read_lock and check if channel belongs to OSPM
63 * before reading or writing to PCC subspace
64 * We need to take write_lock before transferring the channel
65 * ownership to the platform via a Doorbell
66 * This allows us to batch a number of CPPC requests if they happen
67 * to originate in about the same time
68 *
69 * For non-performance critical usecases(init)
70 * Take write_lock for all purposes which gives exclusive access
71 */
72 struct rw_semaphore pcc_lock;
73
74 /* Wait queue for CPUs whose requests were batched */
75 wait_queue_head_t pcc_write_wait_q;
76 ktime_t last_cmd_cmpl_time;
77 ktime_t last_mpar_reset;
78 int mpar_count;
79 int refcount;
80};
81
82/* Array to represent the PCC channel per subspace ID */
83static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
84/* The cpu_pcc_subspace_idx contains per CPU subspace ID */
85static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
86
87/*
88 * The cpc_desc structure contains the ACPI register details
89 * as described in the per CPU _CPC tables. The details
90 * include the type of register (e.g. PCC, System IO, FFH etc.)
91 * and destination addresses which lets us READ/WRITE CPU performance
92 * information using the appropriate I/O methods.
93 */
94static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
95
96/* pcc mapped address + header size + offset within PCC subspace */
97#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_channel->shmem + \
98 0x8 + (offs))
99
100/* Check if a CPC register is in PCC */
101#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
102 (cpc)->cpc_entry.reg.space_id == \
103 ACPI_ADR_SPACE_PLATFORM_COMM)
104
105/* Check if a CPC register is in FFH */
106#define CPC_IN_FFH(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
107 (cpc)->cpc_entry.reg.space_id == \
108 ACPI_ADR_SPACE_FIXED_HARDWARE)
109
110/* Check if a CPC register is in SystemMemory */
111#define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
112 (cpc)->cpc_entry.reg.space_id == \
113 ACPI_ADR_SPACE_SYSTEM_MEMORY)
114
115/* Check if a CPC register is in SystemIo */
116#define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
117 (cpc)->cpc_entry.reg.space_id == \
118 ACPI_ADR_SPACE_SYSTEM_IO)
119
120/* Evaluates to True if reg is a NULL register descriptor */
121#define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
122 (reg)->address == 0 && \
123 (reg)->bit_width == 0 && \
124 (reg)->bit_offset == 0 && \
125 (reg)->access_width == 0)
126
127/* Evaluates to True if an optional cpc field is supported */
128#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
129 !!(cpc)->cpc_entry.int_value : \
130 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
131
132/*
133 * Each bit indicates the optionality of the register in per-cpu
134 * cpc_regs[] with the corresponding index. 0 means mandatory and 1
135 * means optional.
136 */
137#define REG_OPTIONAL (0x7FC7D0)
138
139/*
140 * Use the index of the register in per-cpu cpc_regs[] to check if
141 * it's an optional one.
142 */
143#define IS_OPTIONAL_CPC_REG(reg_idx) (REG_OPTIONAL & (1U << (reg_idx)))
144
145/*
146 * Arbitrary Retries in case the remote processor is slow to respond
147 * to PCC commands. Keeping it high enough to cover emulators where
148 * the processors run painfully slow.
149 */
150#define NUM_RETRIES 500ULL
151
152#define OVER_16BTS_MASK ~0xFFFFULL
153
154#define define_one_cppc_ro(_name) \
155static struct kobj_attribute _name = \
156__ATTR(_name, 0444, show_##_name, NULL)
157
158#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
159
160#define show_cppc_data(access_fn, struct_name, member_name) \
161 static ssize_t show_##member_name(struct kobject *kobj, \
162 struct kobj_attribute *attr, char *buf) \
163 { \
164 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
165 struct struct_name st_name = {0}; \
166 int ret; \
167 \
168 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
169 if (ret) \
170 return ret; \
171 \
172 return sysfs_emit(buf, "%llu\n", \
173 (u64)st_name.member_name); \
174 } \
175 define_one_cppc_ro(member_name)
176
177show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
178show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
179show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
180show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, reference_perf);
181show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
182show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guaranteed_perf);
183show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
184show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
185
186show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
187
188/*
189 * PCC reuses the access_width field as the subspace id, so only decode access
190 * size for non-PCC registers. Otherwise, use the bit_width.
191 */
192#define GET_BIT_WIDTH(reg) (((reg)->access_width && \
193 (reg)->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) ? \
194 (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
195
196/* Shift and apply the mask for CPC reads/writes */
197#define MASK_VAL_READ(reg, val) (((val) >> (reg)->bit_offset) & \
198 GENMASK(((reg)->bit_width) - 1, 0))
199#define MASK_VAL_WRITE(reg, prev_val, val) \
200 ((((val) & GENMASK(((reg)->bit_width) - 1, 0)) << (reg)->bit_offset) | \
201 ((prev_val) & ~(GENMASK(((reg)->bit_width) - 1, 0) << (reg)->bit_offset))) \
202
203static u64 cpc_sysmem_access_size(const struct cpc_register_resource *reg)
204{
205 const struct cpc_reg *gas = &reg->cpc_entry.reg;
206 unsigned int width;
207
208 if (gas->access_width > 4)
209 return 0;
210
211 width = GET_BIT_WIDTH(gas);
212
213 if (width != 8 && width != 16 && width != 32 && width != 64)
214 return 0;
215
216 return width / 8;
217}
218
219static bool cpc_sysmem_access_units_overlap(const struct cpc_register_resource *a,
220 const struct cpc_register_resource *b)
221{
222 const struct cpc_reg *a_gas = &a->cpc_entry.reg;
223 const struct cpc_reg *b_gas = &b->cpc_entry.reg;
224 u64 a_size = cpc_sysmem_access_size(a);
225 u64 b_size = cpc_sysmem_access_size(b);
226
227 /* Keep the conservative locking path for malformed access widths. */
228 if (!a_size || !b_size)
229 return true;
230
231 if (a_gas->address < b_gas->address)
232 return b_gas->address - a_gas->address < a_size;
233
234 return a_gas->address - b_gas->address < b_size;
235}
236
237static void cpc_mark_rmw_lock_users(struct cpc_desc *cpc_desc)
238{
239 int i, j;
240
241 for (i = 0; i < cpc_desc->num_entries - 2; i++) {
242 struct cpc_register_resource *a = &cpc_desc->cpc_regs[i];
243 struct cpc_reg *gas;
244 u64 access_size;
245
246 if (!CPC_SUPPORTED(a) || !CPC_IN_SYSTEM_MEMORY(a))
247 continue;
248
249 gas = &a->cpc_entry.reg;
250 access_size = cpc_sysmem_access_size(a);
251 if (gas->bit_offset || !access_size ||
252 gas->bit_width != access_size * 8)
253 a->cpc_entry.use_rmw_lock = true;
254
255 for (j = i + 1; j < cpc_desc->num_entries - 2; j++) {
256 struct cpc_register_resource *b = &cpc_desc->cpc_regs[j];
257
258 if (!CPC_SUPPORTED(b) || !CPC_IN_SYSTEM_MEMORY(b))
259 continue;
260 if (!cpc_sysmem_access_units_overlap(a, b))
261 continue;
262
263 a->cpc_entry.use_rmw_lock = true;
264 b->cpc_entry.use_rmw_lock = true;
265 }
266 }
267}
268
269static ssize_t show_feedback_ctrs(struct kobject *kobj,
270 struct kobj_attribute *attr, char *buf)
271{
272 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
273 struct cppc_perf_fb_ctrs fb_ctrs = {0};
274 int ret;
275
276 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
277 if (ret)
278 return ret;
279
280 return sysfs_emit(buf, "ref:%llu del:%llu\n",
281 fb_ctrs.reference, fb_ctrs.delivered);
282}
283define_one_cppc_ro(feedback_ctrs);
284
285static struct attribute *cppc_attrs[] = {
286 &feedback_ctrs.attr,
287 &reference_perf.attr,
288 &wraparound_time.attr,
289 &highest_perf.attr,
290 &lowest_perf.attr,
291 &lowest_nonlinear_perf.attr,
292 &guaranteed_perf.attr,
293 &nominal_perf.attr,
294 &nominal_freq.attr,
295 &lowest_freq.attr,
296 NULL
297};
298ATTRIBUTE_GROUPS(cppc);
299
300static const struct kobj_type cppc_ktype = {
301 .sysfs_ops = &kobj_sysfs_ops,
302 .default_groups = cppc_groups,
303};
304
305static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
306{
307 int ret, status;
308 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
309 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
310 pcc_ss_data->pcc_channel->shmem;
311
312 if (!pcc_ss_data->platform_owns_pcc)
313 return 0;
314
315 /*
316 * Poll PCC status register every 3us(delay_us) for maximum of
317 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
318 */
319 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
320 status & PCC_CMD_COMPLETE_MASK, 3,
321 pcc_ss_data->deadline_us);
322
323 if (likely(!ret)) {
324 pcc_ss_data->platform_owns_pcc = false;
325 if (chk_err_bit && (status & PCC_ERROR_MASK))
326 ret = -EIO;
327 }
328
329 if (unlikely(ret))
330 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
331 pcc_ss_id, ret);
332
333 return ret;
334}
335
336/*
337 * This function transfers the ownership of the PCC to the platform
338 * So it must be called while holding write_lock(pcc_lock)
339 */
340static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
341{
342 int ret = -EIO, i;
343 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
344 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
345 pcc_ss_data->pcc_channel->shmem;
346 unsigned int time_delta;
347
348 /*
349 * For CMD_WRITE we know for a fact the caller should have checked
350 * the channel before writing to PCC space
351 */
352 if (cmd == CMD_READ) {
353 /*
354 * If there are pending cpc_writes, then we stole the channel
355 * before write completion, so first send a WRITE command to
356 * platform
357 */
358 if (pcc_ss_data->pending_pcc_write_cmd)
359 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
360
361 ret = check_pcc_chan(pcc_ss_id, false);
362 if (ret)
363 goto end;
364 } else /* CMD_WRITE */
365 pcc_ss_data->pending_pcc_write_cmd = FALSE;
366
367 /*
368 * Handle the Minimum Request Turnaround Time(MRTT)
369 * "The minimum amount of time that OSPM must wait after the completion
370 * of a command before issuing the next command, in microseconds"
371 */
372 if (pcc_ss_data->pcc_mrtt) {
373 time_delta = ktime_us_delta(ktime_get(),
374 pcc_ss_data->last_cmd_cmpl_time);
375 if (pcc_ss_data->pcc_mrtt > time_delta)
376 udelay(pcc_ss_data->pcc_mrtt - time_delta);
377 }
378
379 /*
380 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
381 * "The maximum number of periodic requests that the subspace channel can
382 * support, reported in commands per minute. 0 indicates no limitation."
383 *
384 * This parameter should be ideally zero or large enough so that it can
385 * handle maximum number of requests that all the cores in the system can
386 * collectively generate. If it is not, we will follow the spec and just
387 * not send the request to the platform after hitting the MPAR limit in
388 * any 60s window
389 */
390 if (pcc_ss_data->pcc_mpar) {
391 if (pcc_ss_data->mpar_count == 0) {
392 time_delta = ktime_ms_delta(ktime_get(),
393 pcc_ss_data->last_mpar_reset);
394 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
395 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
396 pcc_ss_id);
397 ret = -EIO;
398 goto end;
399 }
400 pcc_ss_data->last_mpar_reset = ktime_get();
401 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
402 }
403 pcc_ss_data->mpar_count--;
404 }
405
406 /* Write to the shared comm region. */
407 writew_relaxed(cmd, &generic_comm_base->command);
408
409 /* Flip CMD COMPLETE bit */
410 writew_relaxed(0, &generic_comm_base->status);
411
412 pcc_ss_data->platform_owns_pcc = true;
413
414 /* Ring doorbell */
415 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
416 if (ret < 0) {
417 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
418 pcc_ss_id, cmd, ret);
419 goto end;
420 }
421
422 /* wait for completion and check for PCC error bit */
423 ret = check_pcc_chan(pcc_ss_id, true);
424
425 if (pcc_ss_data->pcc_mrtt)
426 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
427
428 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
429 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
430 else
431 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
432
433end:
434 if (cmd == CMD_WRITE) {
435 if (unlikely(ret)) {
436 for_each_possible_cpu(i) {
437 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
438
439 if (!desc)
440 continue;
441
442 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
443 desc->write_cmd_status = ret;
444 }
445 }
446 pcc_ss_data->pcc_write_cnt++;
447 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
448 }
449
450 return ret;
451}
452
453static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
454{
455 if (ret < 0)
456 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
457 *(u16 *)msg, ret);
458 else
459 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
460 *(u16 *)msg, ret);
461}
462
463static struct mbox_client cppc_mbox_cl = {
464 .tx_done = cppc_chan_tx_done,
465 .knows_txdone = true,
466};
467
468static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
469{
470 int result = -EFAULT;
471 acpi_status status = AE_OK;
472 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
473 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
474 struct acpi_buffer state = {0, NULL};
475 union acpi_object *psd = NULL;
476 struct acpi_psd_package *pdomain;
477
478 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
479 &buffer, ACPI_TYPE_PACKAGE);
480 if (status == AE_NOT_FOUND) /* _PSD is optional */
481 return 0;
482 if (ACPI_FAILURE(status))
483 return -ENODEV;
484
485 psd = buffer.pointer;
486 if (!psd || psd->package.count != 1) {
487 pr_debug("Invalid _PSD data\n");
488 goto end;
489 }
490
491 pdomain = &(cpc_ptr->domain_info);
492
493 state.length = sizeof(struct acpi_psd_package);
494 state.pointer = pdomain;
495
496 status = acpi_extract_package(&(psd->package.elements[0]),
497 &format, &state);
498 if (ACPI_FAILURE(status)) {
499 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
500 goto end;
501 }
502
503 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
504 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
505 goto end;
506 }
507
508 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
509 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
510 goto end;
511 }
512
513 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
514 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
515 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
516 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
517 goto end;
518 }
519
520 result = 0;
521end:
522 kfree(buffer.pointer);
523 return result;
524}
525
526bool acpi_cpc_valid(void)
527{
528 struct cpc_desc *cpc_ptr;
529 int cpu;
530
531 if (acpi_disabled)
532 return false;
533
534 for_each_online_cpu(cpu) {
535 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
536 if (!cpc_ptr)
537 return false;
538 }
539
540 return true;
541}
542EXPORT_SYMBOL_GPL(acpi_cpc_valid);
543
544bool cppc_allow_fast_switch(const struct cpumask *cpus)
545{
546 struct cpc_register_resource *desired_reg, *min_reg, *max_reg;
547 struct cpc_desc *cpc_ptr;
548 int cpu;
549
550 for_each_cpu(cpu, cpus) {
551 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
552 if (!cpc_ptr)
553 return false;
554 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
555 min_reg = &cpc_ptr->cpc_regs[MIN_PERF];
556 max_reg = &cpc_ptr->cpc_regs[MAX_PERF];
557
558 if (!CPC_SUPPORTED(desired_reg) ||
559 (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
560 !CPC_IN_SYSTEM_IO(desired_reg)) ||
561 (CPC_SUPPORTED(min_reg) &&
562 !CPC_IN_SYSTEM_MEMORY(min_reg) &&
563 !CPC_IN_SYSTEM_IO(min_reg)) ||
564 (CPC_SUPPORTED(max_reg) &&
565 !CPC_IN_SYSTEM_MEMORY(max_reg) &&
566 !CPC_IN_SYSTEM_IO(max_reg)))
567 return false;
568 }
569
570 return true;
571}
572EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
573
574/**
575 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
576 * @cpu: Find all CPUs that share a domain with cpu.
577 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
578 *
579 * Return: 0 for success or negative value for err.
580 */
581int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
582{
583 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
584 struct acpi_psd_package *match_pdomain;
585 struct acpi_psd_package *pdomain;
586 int count_target, i;
587
588 /*
589 * Now that we have _PSD data from all CPUs, let's setup P-state
590 * domain info.
591 */
592 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
593 if (!cpc_ptr)
594 return -EFAULT;
595
596 pdomain = &(cpc_ptr->domain_info);
597 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
598 if (pdomain->num_processors <= 1)
599 return 0;
600
601 /* Validate the Domain info */
602 count_target = pdomain->num_processors;
603 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
604 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
605 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
606 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
607 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
608 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
609
610 for_each_possible_cpu(i) {
611 if (i == cpu)
612 continue;
613
614 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
615 if (!match_cpc_ptr)
616 continue;
617
618 match_pdomain = &(match_cpc_ptr->domain_info);
619 if (match_pdomain->domain != pdomain->domain)
620 continue;
621
622 /* Here i and cpu are in the same domain */
623 if (match_pdomain->num_processors != count_target)
624 goto err_fault;
625
626 if (pdomain->coord_type != match_pdomain->coord_type)
627 goto err_fault;
628
629 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
630 }
631
632 return 0;
633
634err_fault:
635 /* Assume no coordination on any error parsing domain info */
636 cpumask_clear(cpu_data->shared_cpu_map);
637 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
638 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
639
640 return -EFAULT;
641}
642EXPORT_SYMBOL_GPL(acpi_get_psd_map);
643
644static int register_pcc_channel(int pcc_ss_idx)
645{
646 struct pcc_mbox_chan *pcc_chan;
647 u64 usecs_lat;
648
649 if (pcc_ss_idx >= 0) {
650 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
651
652 if (IS_ERR(pcc_chan)) {
653 pr_err("Failed to find PCC channel for subspace %d\n",
654 pcc_ss_idx);
655 return -ENODEV;
656 }
657
658 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
659 /*
660 * cppc_ss->latency is just a Nominal value. In reality
661 * the remote processor could be much slower to reply.
662 * So add an arbitrary amount of wait on top of Nominal.
663 */
664 usecs_lat = NUM_RETRIES * pcc_chan->latency;
665 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
666 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
667 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
668 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
669
670 /* Set flag so that we don't come here for each CPU. */
671 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
672 }
673
674 return 0;
675}
676
677/**
678 * cpc_ffh_supported() - check if FFH reading supported
679 *
680 * Check if the architecture has support for functional fixed hardware
681 * read/write capability.
682 *
683 * Return: true for supported, false for not supported
684 */
685bool __weak cpc_ffh_supported(void)
686{
687 return false;
688}
689
690/**
691 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
692 *
693 * Check if the architectural support for CPPC is present even
694 * if the _OSC hasn't prescribed it
695 *
696 * Return: true for supported, false for not supported
697 */
698bool __weak cpc_supported_by_cpu(void)
699{
700 return false;
701}
702
703/**
704 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
705 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
706 *
707 * Check and allocate the cppc_pcc_data memory.
708 * In some processor configurations it is possible that same subspace
709 * is shared between multiple CPUs. This is seen especially in CPUs
710 * with hardware multi-threading support.
711 *
712 * Return: 0 for success, errno for failure
713 */
714static int pcc_data_alloc(int pcc_ss_id)
715{
716 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
717 return -EINVAL;
718
719 if (pcc_data[pcc_ss_id]) {
720 pcc_data[pcc_ss_id]->refcount++;
721 } else {
722 pcc_data[pcc_ss_id] = kzalloc_obj(struct cppc_pcc_data);
723 if (!pcc_data[pcc_ss_id])
724 return -ENOMEM;
725 pcc_data[pcc_ss_id]->refcount++;
726 }
727
728 return 0;
729}
730
731/*
732 * An example CPC table looks like the following.
733 *
734 * Name (_CPC, Package() {
735 * 17, // NumEntries
736 * 1, // Revision
737 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
738 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
739 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
740 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
741 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
742 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
743 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
744 * ...
745 * ...
746 * ...
747 * }
748 * Each Register() encodes how to access that specific register.
749 * e.g. a sample PCC entry has the following encoding:
750 *
751 * Register (
752 * PCC, // AddressSpaceKeyword
753 * 8, // RegisterBitWidth
754 * 8, // RegisterBitOffset
755 * 0x30, // RegisterAddress
756 * 9, // AccessSize (subspace ID)
757 * )
758 */
759
760/**
761 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
762 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
763 *
764 * Return: 0 for success or negative value for err.
765 */
766int acpi_cppc_processor_probe(struct acpi_processor *pr)
767{
768 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
769 union acpi_object *out_obj, *cpc_obj;
770 struct cpc_desc *cpc_ptr;
771 struct cpc_reg *gas_t;
772 struct device *cpu_dev;
773 acpi_handle handle = pr->handle;
774 unsigned int num_ent, i, cpc_rev;
775 int pcc_subspace_id = -1;
776 acpi_status status;
777 int ret = -ENODATA;
778
779 if (!osc_sb_cppc2_support_acked) {
780 pr_debug("CPPC v2 _OSC not acked\n");
781 if (!cpc_supported_by_cpu()) {
782 pr_debug("CPPC is not supported by the CPU\n");
783 return -ENODEV;
784 }
785 }
786
787 /* Parse the ACPI _CPC table for this CPU. */
788 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
789 ACPI_TYPE_PACKAGE);
790 if (ACPI_FAILURE(status)) {
791 ret = -ENODEV;
792 goto out_buf_free;
793 }
794
795 out_obj = (union acpi_object *) output.pointer;
796
797 cpc_ptr = kzalloc_obj(struct cpc_desc);
798 if (!cpc_ptr) {
799 ret = -ENOMEM;
800 goto out_buf_free;
801 }
802
803 /* First entry is NumEntries. */
804 cpc_obj = &out_obj->package.elements[0];
805 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
806 num_ent = cpc_obj->integer.value;
807 if (num_ent <= 1) {
808 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
809 num_ent, pr->id);
810 goto out_free;
811 }
812 } else {
813 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
814 cpc_obj->type, pr->id);
815 goto out_free;
816 }
817
818 /* Second entry should be revision. */
819 cpc_obj = &out_obj->package.elements[1];
820 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
821 cpc_rev = cpc_obj->integer.value;
822 } else {
823 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
824 cpc_obj->type, pr->id);
825 goto out_free;
826 }
827
828 if (cpc_rev < CPPC_V2_REV) {
829 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
830 pr->id);
831 goto out_free;
832 }
833
834 /*
835 * Disregard _CPC if the number of entries in the return package is not
836 * as expected, but support future revisions being proper supersets of
837 * the v4 and only causing more entries to be returned by _CPC.
838 */
839 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
840 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
841 (cpc_rev == CPPC_V4_REV && num_ent != CPPC_V4_NUM_ENT) ||
842 (cpc_rev > CPPC_V4_REV && num_ent <= CPPC_V4_NUM_ENT)) {
843 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
844 num_ent, pr->id);
845 goto out_free;
846 }
847 if (cpc_rev > CPPC_V4_REV) {
848 num_ent = CPPC_V4_NUM_ENT;
849 cpc_rev = CPPC_V4_REV;
850 }
851
852 cpc_ptr->num_entries = num_ent;
853 cpc_ptr->version = cpc_rev;
854
855 /* Iterate through remaining entries in _CPC */
856 for (i = 2; i < num_ent; i++) {
857 cpc_obj = &out_obj->package.elements[i];
858
859 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
860 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
861 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
862 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
863 gas_t = (struct cpc_reg *)
864 cpc_obj->buffer.pointer;
865
866 /*
867 * The PCC Subspace index is encoded inside
868 * the CPC table entries. The same PCC index
869 * will be used for all the PCC entries,
870 * so extract it only once.
871 */
872 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
873 if (pcc_subspace_id < 0) {
874 pcc_subspace_id = gas_t->access_width;
875 if (pcc_data_alloc(pcc_subspace_id))
876 goto out_free;
877 } else if (pcc_subspace_id != gas_t->access_width) {
878 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
879 pr->id);
880 goto out_free;
881 }
882 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
883 if (gas_t->address) {
884 void __iomem *addr;
885 size_t access_width;
886
887 if (!osc_cpc_flexible_adr_space_confirmed) {
888 pr_debug("Flexible address space capability not supported\n");
889 if (!cpc_supported_by_cpu())
890 goto out_free;
891 }
892
893 access_width = GET_BIT_WIDTH(gas_t) / 8;
894 addr = ioremap(gas_t->address, access_width);
895 if (!addr)
896 goto out_free;
897 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
898 }
899 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
900 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
901 /*
902 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
903 * SystemIO doesn't implement 64-bit
904 * registers.
905 */
906 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
907 gas_t->access_width);
908 goto out_free;
909 }
910 if (gas_t->address & OVER_16BTS_MASK) {
911 /* SystemIO registers use 16-bit integer addresses */
912 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
913 gas_t->address);
914 goto out_free;
915 }
916 if (!osc_cpc_flexible_adr_space_confirmed) {
917 pr_debug("Flexible address space capability not supported\n");
918 if (!cpc_supported_by_cpu())
919 goto out_free;
920 }
921 } else {
922 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
923 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
924 pr_debug("Unsupported register type (%d) in _CPC\n",
925 gas_t->space_id);
926 goto out_free;
927 }
928 }
929
930 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
931 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
932 } else if (cpc_obj->type == ACPI_TYPE_PACKAGE && (i - 2) == RESOURCE_PRIORITY) {
933 /*
934 * ACPI 6.6, s8.4.6.1.2.7 defines Resource Priority as a
935 * Package of Resource Priority Register Descriptor sub-packages.
936 * Parsing the full structure is not yet supported.
937 * Mark the register as unsupported for now.
938 */
939 pr_debug("CPU:%d Resource Priority not supported\n", pr->id);
940 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
941 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = 0;
942 } else {
943 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
944 i, pr->id);
945 goto out_free;
946 }
947 }
948 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
949
950 /*
951 * In CPPC v1, DESIRED_PERF is mandatory. In CPPC v2, it is optional
952 * only when AUTO_SEL_ENABLE is supported.
953 */
954 if (!CPC_SUPPORTED(&cpc_ptr->cpc_regs[DESIRED_PERF]) &&
955 (!osc_sb_cppc2_support_acked ||
956 !CPC_SUPPORTED(&cpc_ptr->cpc_regs[AUTO_SEL_ENABLE])))
957 pr_warn("Desired perf. register is mandatory if CPPC v2 is not supported "
958 "or autonomous selection is disabled\n");
959
960 /*
961 * Initialize the remaining cpc_regs as unsupported.
962 * Example: In case FW exposes CPPC v2, the below loop will initialize
963 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
964 */
965 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
966 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
967 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
968 }
969
970
971 /* Store CPU Logical ID */
972 cpc_ptr->cpu_id = pr->id;
973 cpc_mark_rmw_lock_users(cpc_ptr);
974 raw_spin_lock_init(&cpc_ptr->rmw_lock);
975
976 /* Parse PSD data for this CPU */
977 ret = acpi_get_psd(cpc_ptr, handle);
978 if (ret)
979 goto out_free;
980
981 /* Register PCC channel once for all PCC subspace ID. */
982 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
983 ret = register_pcc_channel(pcc_subspace_id);
984 if (ret)
985 goto out_free;
986
987 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
988 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
989 }
990
991 /* Everything looks okay */
992 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
993
994 /* Add per logical CPU nodes for reading its feedback counters. */
995 cpu_dev = get_cpu_device(pr->id);
996 if (!cpu_dev) {
997 ret = -EINVAL;
998 goto out_free;
999 }
1000
1001 /* Plug PSD data into this CPU's CPC descriptor. */
1002 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
1003
1004 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
1005 "acpi_cppc");
1006 if (ret) {
1007 per_cpu(cpc_desc_ptr, pr->id) = NULL;
1008 kobject_put(&cpc_ptr->kobj);
1009 goto out_free;
1010 }
1011
1012 kfree(output.pointer);
1013 return 0;
1014
1015out_free:
1016 /* Free all the mapped sys mem areas for this CPU */
1017 for (i = 2; i < cpc_ptr->num_entries; i++) {
1018 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
1019
1020 if (addr)
1021 iounmap(addr);
1022 }
1023 kfree(cpc_ptr);
1024
1025out_buf_free:
1026 kfree(output.pointer);
1027 return ret;
1028}
1029EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
1030
1031/**
1032 * acpi_cppc_processor_exit - Cleanup CPC structs.
1033 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
1034 *
1035 * Return: Void
1036 */
1037void acpi_cppc_processor_exit(struct acpi_processor *pr)
1038{
1039 struct cpc_desc *cpc_ptr;
1040 unsigned int i;
1041 void __iomem *addr;
1042 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
1043
1044 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
1045 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
1046 pcc_data[pcc_ss_id]->refcount--;
1047 if (!pcc_data[pcc_ss_id]->refcount) {
1048 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
1049 kfree(pcc_data[pcc_ss_id]);
1050 pcc_data[pcc_ss_id] = NULL;
1051 }
1052 }
1053 }
1054
1055 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
1056 if (!cpc_ptr)
1057 return;
1058
1059 /* Free all the mapped sys mem areas for this CPU */
1060 for (i = 2; i < cpc_ptr->num_entries; i++) {
1061 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
1062 if (addr)
1063 iounmap(addr);
1064 }
1065
1066 kobject_put(&cpc_ptr->kobj);
1067 kfree(cpc_ptr);
1068}
1069EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
1070
1071/**
1072 * cpc_read_ffh() - Read FFH register
1073 * @cpunum: CPU number to read
1074 * @reg: cppc register information
1075 * @val: place holder for return value
1076 *
1077 * Read bit_width bits from a specified address and bit_offset
1078 *
1079 * Return: 0 for success and error code
1080 */
1081int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
1082{
1083 return -ENOTSUPP;
1084}
1085
1086/**
1087 * cpc_read_ffh_fb_ctrs() - Read FFH feedback counters together
1088 * @cpunum: Target CPU
1089 * @reg1: first CPPC register information
1090 * @val1: place holder for first return value
1091 * @reg2: second CPPC register information
1092 * @val2: place holder for second return value
1093 *
1094 * Return: 0 on success, error code otherwise
1095 */
1096int __weak cpc_read_ffh_fb_ctrs(int cpunum, struct cpc_reg *reg1,
1097 u64 *val1, struct cpc_reg *reg2, u64 *val2)
1098{
1099 return -EOPNOTSUPP;
1100}
1101
1102/**
1103 * cpc_write_ffh() - Write FFH register
1104 * @cpunum: CPU number to write
1105 * @reg: cppc register information
1106 * @val: value to write
1107 *
1108 * Write value of bit_width bits to a specified address and bit_offset
1109 *
1110 * Return: 0 for success and error code
1111 */
1112int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
1113{
1114 return -ENOTSUPP;
1115}
1116
1117/*
1118 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
1119 * as fast as possible. We have already mapped the PCC subspace during init, so
1120 * we can directly write to it.
1121 */
1122
1123static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
1124{
1125 void __iomem *vaddr = NULL;
1126 int size;
1127 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1128 struct cpc_reg *reg = &reg_res->cpc_entry.reg;
1129
1130 if (reg_res->type == ACPI_TYPE_INTEGER) {
1131 *val = reg_res->cpc_entry.int_value;
1132 return 0;
1133 }
1134
1135 *val = 0;
1136 size = GET_BIT_WIDTH(reg);
1137
1138 if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
1139 reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1140 u32 val_u32;
1141 acpi_status status;
1142
1143 status = acpi_os_read_port((acpi_io_address)reg->address,
1144 &val_u32, size);
1145 if (ACPI_FAILURE(status)) {
1146 pr_debug("Error: Failed to read SystemIO port %llx\n",
1147 reg->address);
1148 return -EFAULT;
1149 }
1150
1151 *val = val_u32;
1152 return 0;
1153 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1154 /*
1155 * For registers in PCC space, the register size is determined
1156 * by the bit width field; the access size is used to indicate
1157 * the PCC subspace id.
1158 */
1159 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1160 }
1161 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1162 vaddr = reg_res->sys_mem_vaddr;
1163 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1164 return cpc_read_ffh(cpu, reg, val);
1165 else
1166 return acpi_os_read_memory((acpi_physical_address)reg->address,
1167 val, size);
1168
1169 switch (size) {
1170 case 8:
1171 *val = readb_relaxed(vaddr);
1172 break;
1173 case 16:
1174 *val = readw_relaxed(vaddr);
1175 break;
1176 case 32:
1177 *val = readl_relaxed(vaddr);
1178 break;
1179 case 64:
1180 *val = readq_relaxed(vaddr);
1181 break;
1182 default:
1183 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1184 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1185 size, reg->address);
1186 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1187 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1188 size, pcc_ss_id);
1189 }
1190 return -EFAULT;
1191 }
1192
1193 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1194 *val = MASK_VAL_READ(reg, *val);
1195
1196 return 0;
1197}
1198
1199static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1200{
1201 int ret_val = 0;
1202 int size;
1203 u64 prev_val;
1204 void __iomem *vaddr = NULL;
1205 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1206 struct cpc_reg *reg = &reg_res->cpc_entry.reg;
1207 struct cpc_desc *cpc_desc;
1208 unsigned long flags;
1209 bool locked = false;
1210
1211 size = GET_BIT_WIDTH(reg);
1212
1213 if (IS_ENABLED(CONFIG_HAS_IOPORT) &&
1214 reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1215 acpi_status status;
1216
1217 status = acpi_os_write_port((acpi_io_address)reg->address,
1218 (u32)val, size);
1219 if (ACPI_FAILURE(status)) {
1220 pr_debug("Error: Failed to write SystemIO port %llx\n",
1221 reg->address);
1222 return -EFAULT;
1223 }
1224
1225 return 0;
1226 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1227 /*
1228 * For registers in PCC space, the register size is determined
1229 * by the bit width field; the access size is used to indicate
1230 * the PCC subspace id.
1231 */
1232 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1233 }
1234 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1235 vaddr = reg_res->sys_mem_vaddr;
1236 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1237 return cpc_write_ffh(cpu, reg, val);
1238 else
1239 return acpi_os_write_memory((acpi_physical_address)reg->address,
1240 val, size);
1241
1242 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1243 /*
1244 * The _CPC layout is immutable after probe. The precomputed flag
1245 * retains serialization for partial fields or overlapping access
1246 * units; standalone full-width registers avoid the lock.
1247 */
1248 locked = reg_res->cpc_entry.use_rmw_lock;
1249 if (locked) {
1250 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1251 if (!cpc_desc) {
1252 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1253 return -ENODEV;
1254 }
1255 raw_spin_lock_irqsave(&cpc_desc->rmw_lock, flags);
1256 }
1257
1258 if (reg->bit_offset || reg->bit_width != size) {
1259 switch (size) {
1260 case 8:
1261 prev_val = readb_relaxed(vaddr);
1262 break;
1263 case 16:
1264 prev_val = readw_relaxed(vaddr);
1265 break;
1266 case 32:
1267 prev_val = readl_relaxed(vaddr);
1268 break;
1269 case 64:
1270 prev_val = readq_relaxed(vaddr);
1271 break;
1272 default:
1273 if (locked)
1274 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock,
1275 flags);
1276 return -EFAULT;
1277 }
1278 val = MASK_VAL_WRITE(reg, prev_val, val);
1279 }
1280 }
1281
1282 switch (size) {
1283 case 8:
1284 writeb_relaxed(val, vaddr);
1285 break;
1286 case 16:
1287 writew_relaxed(val, vaddr);
1288 break;
1289 case 32:
1290 writel_relaxed(val, vaddr);
1291 break;
1292 case 64:
1293 writeq_relaxed(val, vaddr);
1294 break;
1295 default:
1296 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1297 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1298 size, reg->address);
1299 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1300 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1301 size, pcc_ss_id);
1302 }
1303 ret_val = -EFAULT;
1304 break;
1305 }
1306
1307 if (locked)
1308 raw_spin_unlock_irqrestore(&cpc_desc->rmw_lock, flags);
1309
1310 return ret_val;
1311}
1312
1313static int cppc_get_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 *val)
1314{
1315 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1316 struct cppc_pcc_data *pcc_ss_data = NULL;
1317 int ret;
1318
1319 if (pcc_ss_id < 0) {
1320 pr_debug("Invalid pcc_ss_id\n");
1321 return -ENODEV;
1322 }
1323
1324 pcc_ss_data = pcc_data[pcc_ss_id];
1325
1326 down_write(&pcc_ss_data->pcc_lock);
1327
1328 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1329 ret = cpc_read(cpu, reg, val);
1330 else
1331 ret = -EIO;
1332
1333 up_write(&pcc_ss_data->pcc_lock);
1334
1335 return ret;
1336}
1337
1338static int cppc_get_reg_val(int cpu, enum cppc_regs reg_idx, u64 *val)
1339{
1340 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1341 struct cpc_register_resource *reg;
1342
1343 if (val == NULL)
1344 return -EINVAL;
1345
1346 if (!cpc_desc) {
1347 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1348 return -ENODEV;
1349 }
1350
1351 reg = &cpc_desc->cpc_regs[reg_idx];
1352
1353 if ((reg->type == ACPI_TYPE_INTEGER && IS_OPTIONAL_CPC_REG(reg_idx) &&
1354 !reg->cpc_entry.int_value) || (reg->type != ACPI_TYPE_INTEGER &&
1355 IS_NULL_REG(&reg->cpc_entry.reg))) {
1356 pr_debug("CPC register is not supported\n");
1357 return -EOPNOTSUPP;
1358 }
1359
1360 if (CPC_IN_PCC(reg))
1361 return cppc_get_reg_val_in_pcc(cpu, reg, val);
1362
1363 return cpc_read(cpu, reg, val);
1364}
1365
1366static int cppc_set_reg_val_in_pcc(int cpu, struct cpc_register_resource *reg, u64 val)
1367{
1368 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1369 struct cppc_pcc_data *pcc_ss_data = NULL;
1370 int ret;
1371
1372 if (pcc_ss_id < 0) {
1373 pr_debug("Invalid pcc_ss_id\n");
1374 return -ENODEV;
1375 }
1376
1377 ret = cpc_write(cpu, reg, val);
1378 if (ret)
1379 return ret;
1380
1381 pcc_ss_data = pcc_data[pcc_ss_id];
1382
1383 down_write(&pcc_ss_data->pcc_lock);
1384 /* after writing CPC, transfer the ownership of PCC to platform */
1385 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1386 up_write(&pcc_ss_data->pcc_lock);
1387
1388 return ret;
1389}
1390
1391static int cppc_set_reg_val(int cpu, enum cppc_regs reg_idx, u64 val)
1392{
1393 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1394 struct cpc_register_resource *reg;
1395
1396 if (!cpc_desc) {
1397 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1398 return -ENODEV;
1399 }
1400
1401 reg = &cpc_desc->cpc_regs[reg_idx];
1402
1403 /* if a register is writeable, it must be a buffer and not null */
1404 if ((reg->type != ACPI_TYPE_BUFFER) || IS_NULL_REG(&reg->cpc_entry.reg)) {
1405 pr_debug("CPC register is not supported\n");
1406 return -EOPNOTSUPP;
1407 }
1408
1409 if (CPC_IN_PCC(reg))
1410 return cppc_set_reg_val_in_pcc(cpu, reg, val);
1411
1412 return cpc_write(cpu, reg, val);
1413}
1414
1415static bool cppc_desired_perf_readable(const struct cpc_desc *cpc_desc)
1416{
1417 return cpc_desc->version < CPPC_V4_REV;
1418}
1419
1420/**
1421 * cppc_get_desired_perf - Get the desired performance register value.
1422 * @cpunum: CPU from which to get desired performance.
1423 * @desired_perf: Return address.
1424 *
1425 * Return: 0 for success, -EOPNOTSUPP for _CPC revision 4 or later, and a
1426 * negative errno otherwise.
1427 */
1428int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1429{
1430 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1431
1432 if (!cpc_desc)
1433 return -ENODEV;
1434
1435 /* _CPC revision 4 no longer specifies Desired Performance as readable. */
1436 if (!cppc_desired_perf_readable(cpc_desc))
1437 return -EOPNOTSUPP;
1438
1439 return cppc_get_reg_val(cpunum, DESIRED_PERF, desired_perf);
1440}
1441EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1442
1443/**
1444 * cppc_get_nominal_perf - Get the nominal performance register value.
1445 * @cpunum: CPU from which to get nominal performance.
1446 * @nominal_perf: Return address.
1447 *
1448 * Return: 0 for success, -EIO otherwise.
1449 */
1450int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1451{
1452 return cppc_get_reg_val(cpunum, NOMINAL_PERF, nominal_perf);
1453}
1454
1455/**
1456 * cppc_get_highest_perf - Get the highest performance register value.
1457 * @cpunum: CPU from which to get highest performance.
1458 * @highest_perf: Return address.
1459 *
1460 * Return: 0 for success, -EIO otherwise.
1461 */
1462int cppc_get_highest_perf(int cpunum, u64 *highest_perf)
1463{
1464 return cppc_get_reg_val(cpunum, HIGHEST_PERF, highest_perf);
1465}
1466EXPORT_SYMBOL_GPL(cppc_get_highest_perf);
1467
1468/**
1469 * cppc_get_epp_perf - Get the epp register value.
1470 * @cpunum: CPU from which to get epp preference value.
1471 * @epp_perf: Return address.
1472 *
1473 * Return: 0 for success, -EIO otherwise.
1474 */
1475int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1476{
1477 return cppc_get_reg_val(cpunum, ENERGY_PERF, epp_perf);
1478}
1479EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1480
1481/**
1482 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1483 * @cpunum: CPU from which to get capabilities info.
1484 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1485 *
1486 * Return: 0 for success with perf_caps populated else -ERRNO.
1487 */
1488int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1489{
1490 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1491 struct cpc_register_resource *highest_reg, *lowest_reg,
1492 *lowest_non_linear_reg, *nominal_reg, *reference_reg,
1493 *guaranteed_reg, *low_freq_reg = NULL, *nom_freq_reg = NULL;
1494 u64 high, low, guaranteed, nom, ref, min_nonlinear,
1495 low_f = 0, nom_f = 0;
1496 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1497 struct cppc_pcc_data *pcc_ss_data = NULL;
1498 int ret = 0, regs_in_pcc = 0;
1499
1500 if (!cpc_desc) {
1501 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1502 return -ENODEV;
1503 }
1504
1505 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1506 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1507 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1508 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1509 reference_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1510 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1511 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1512 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1513
1514 /* Are any of the regs PCC ?*/
1515 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1516 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1517 (CPC_SUPPORTED(reference_reg) && CPC_IN_PCC(reference_reg)) ||
1518 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg) ||
1519 CPC_IN_PCC(guaranteed_reg)) {
1520 if (pcc_ss_id < 0) {
1521 pr_debug("Invalid pcc_ss_id\n");
1522 return -ENODEV;
1523 }
1524 pcc_ss_data = pcc_data[pcc_ss_id];
1525 regs_in_pcc = 1;
1526 down_write(&pcc_ss_data->pcc_lock);
1527 /* Ring doorbell once to update PCC subspace */
1528 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1529 ret = -EIO;
1530 goto out_err;
1531 }
1532 }
1533
1534 ret = cpc_read(cpunum, highest_reg, &high);
1535 if (ret)
1536 goto out_err;
1537 perf_caps->highest_perf = high;
1538
1539 ret = cpc_read(cpunum, lowest_reg, &low);
1540 if (ret)
1541 goto out_err;
1542 perf_caps->lowest_perf = low;
1543
1544 ret = cpc_read(cpunum, nominal_reg, &nom);
1545 if (ret)
1546 goto out_err;
1547 perf_caps->nominal_perf = nom;
1548
1549 /*
1550 * If reference perf register is not supported then we should
1551 * use the nominal perf value
1552 */
1553 if (CPC_SUPPORTED(reference_reg)) {
1554 ret = cpc_read(cpunum, reference_reg, &ref);
1555 if (ret)
1556 goto out_err;
1557 } else {
1558 ref = nom;
1559 }
1560 perf_caps->reference_perf = ref;
1561
1562 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1563 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1564 perf_caps->guaranteed_perf = 0;
1565 } else {
1566 ret = cpc_read(cpunum, guaranteed_reg, &guaranteed);
1567 if (ret)
1568 goto out_err;
1569 perf_caps->guaranteed_perf = guaranteed;
1570 }
1571
1572 ret = cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1573 if (ret)
1574 goto out_err;
1575 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1576
1577 if (!high || !low || !nom || !ref || !min_nonlinear) {
1578 ret = -EFAULT;
1579 goto out_err;
1580 }
1581
1582 /* Read optional lowest and nominal frequencies if present */
1583 if (CPC_SUPPORTED(low_freq_reg)) {
1584 ret = cpc_read(cpunum, low_freq_reg, &low_f);
1585 if (ret)
1586 goto out_err;
1587 }
1588
1589 if (CPC_SUPPORTED(nom_freq_reg)) {
1590 ret = cpc_read(cpunum, nom_freq_reg, &nom_f);
1591 if (ret)
1592 goto out_err;
1593 }
1594
1595 perf_caps->lowest_freq = low_f;
1596 perf_caps->nominal_freq = nom_f;
1597
1598
1599out_err:
1600 if (regs_in_pcc)
1601 up_write(&pcc_ss_data->pcc_lock);
1602 return ret;
1603}
1604EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1605
1606/**
1607 * cppc_perf_ctrs_in_pcc_cpu - Check if any perf counters of a CPU are in PCC.
1608 * @cpu: CPU on which to check perf counters.
1609 *
1610 * Return: true if any of the counters are in PCC regions, false otherwise
1611 */
1612bool cppc_perf_ctrs_in_pcc_cpu(unsigned int cpu)
1613{
1614 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1615
1616 return CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1617 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1618 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]);
1619}
1620EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc_cpu);
1621
1622static int cppc_read_fb_ctrs(int cpunum,
1623 struct cpc_register_resource *delivered_reg,
1624 struct cpc_register_resource *reference_reg,
1625 u64 *delivered, u64 *reference)
1626{
1627 int ret;
1628
1629 /*
1630 * For FFH feedback counters, try a paired read first to reduce
1631 * sampling skew between delivered and reference counters. Fall
1632 * back to the existing per-register reads if unsupported.
1633 */
1634 if (CPC_IN_FFH(delivered_reg) && CPC_IN_FFH(reference_reg)) {
1635 ret = cpc_read_ffh_fb_ctrs(cpunum,
1636 &delivered_reg->cpc_entry.reg, delivered,
1637 &reference_reg->cpc_entry.reg, reference);
1638 if (ret != -EOPNOTSUPP)
1639 return ret;
1640 }
1641
1642 ret = cpc_read(cpunum, delivered_reg, delivered);
1643 if (ret)
1644 return ret;
1645
1646 return cpc_read(cpunum, reference_reg, reference);
1647}
1648
1649/**
1650 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1651 *
1652 * CPPC has flexibility about how CPU performance counters are accessed.
1653 * One of the choices is PCC regions, which can have a high access latency. This
1654 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1655 *
1656 * Return: true if any of the counters are in PCC regions, false otherwise
1657 */
1658bool cppc_perf_ctrs_in_pcc(void)
1659{
1660 int cpu;
1661
1662 for_each_online_cpu(cpu) {
1663 if (cppc_perf_ctrs_in_pcc_cpu(cpu))
1664 return true;
1665 }
1666
1667 return false;
1668}
1669EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1670
1671/**
1672 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1673 * @cpunum: CPU from which to read counters.
1674 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1675 *
1676 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1677 */
1678int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1679{
1680 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1681 struct cpc_register_resource *delivered_reg, *reference_reg,
1682 *ctr_wrap_reg;
1683 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1684 struct cppc_pcc_data *pcc_ss_data = NULL;
1685 u64 delivered, reference, ctr_wrap_time;
1686 int ret = 0, regs_in_pcc = 0;
1687
1688 if (!cpc_desc) {
1689 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1690 return -ENODEV;
1691 }
1692
1693 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1694 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1695 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1696
1697 /* Are any of the regs PCC ?*/
1698 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1699 CPC_IN_PCC(ctr_wrap_reg)) {
1700 if (pcc_ss_id < 0) {
1701 pr_debug("Invalid pcc_ss_id\n");
1702 return -ENODEV;
1703 }
1704 pcc_ss_data = pcc_data[pcc_ss_id];
1705 down_write(&pcc_ss_data->pcc_lock);
1706 regs_in_pcc = 1;
1707 /* Ring doorbell once to update PCC subspace */
1708 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1709 ret = -EIO;
1710 goto out_err;
1711 }
1712 }
1713
1714 ret = cppc_read_fb_ctrs(cpunum, delivered_reg, reference_reg,
1715 &delivered, &reference);
1716 if (ret)
1717 goto out_err;
1718
1719 /*
1720 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1721 * performance counters are assumed to never wrap during the lifetime of
1722 * platform
1723 */
1724 ctr_wrap_time = (u64)(~((u64)0));
1725 if (CPC_SUPPORTED(ctr_wrap_reg)) {
1726 ret = cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1727 if (ret)
1728 goto out_err;
1729 }
1730
1731 if (!delivered || !reference) {
1732 ret = -EFAULT;
1733 goto out_err;
1734 }
1735
1736 perf_fb_ctrs->delivered = delivered;
1737 perf_fb_ctrs->reference = reference;
1738 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1739out_err:
1740 if (regs_in_pcc)
1741 up_write(&pcc_ss_data->pcc_lock);
1742 return ret;
1743}
1744EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1745
1746/*
1747 * Set Energy Performance Preference Register value through
1748 * Performance Controls Interface
1749 */
1750int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1751{
1752 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1753 struct cpc_register_resource *epp_set_reg;
1754 struct cpc_register_resource *auto_sel_reg;
1755 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1756 struct cppc_pcc_data *pcc_ss_data = NULL;
1757 bool autosel_ffh_sysmem;
1758 bool epp_ffh_sysmem;
1759 int ret;
1760
1761 if (!cpc_desc) {
1762 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1763 return -ENODEV;
1764 }
1765
1766 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1767 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1768
1769 epp_ffh_sysmem = CPC_SUPPORTED(epp_set_reg) &&
1770 (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg));
1771 autosel_ffh_sysmem = CPC_SUPPORTED(auto_sel_reg) &&
1772 (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg));
1773
1774 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1775 if (pcc_ss_id < 0) {
1776 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1777 return -ENODEV;
1778 }
1779
1780 if (CPC_SUPPORTED(auto_sel_reg)) {
1781 ret = cpc_write(cpu, auto_sel_reg, enable);
1782 if (ret)
1783 return ret;
1784 }
1785
1786 if (CPC_SUPPORTED(epp_set_reg)) {
1787 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1788 if (ret)
1789 return ret;
1790 }
1791
1792 pcc_ss_data = pcc_data[pcc_ss_id];
1793
1794 down_write(&pcc_ss_data->pcc_lock);
1795 /* after writing CPC, transfer the ownership of PCC to platform */
1796 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1797 up_write(&pcc_ss_data->pcc_lock);
1798 } else if (osc_cpc_flexible_adr_space_confirmed &&
1799 (epp_ffh_sysmem || autosel_ffh_sysmem)) {
1800 if (autosel_ffh_sysmem) {
1801 ret = cpc_write(cpu, auto_sel_reg, enable);
1802 if (ret)
1803 return ret;
1804 }
1805
1806 if (epp_ffh_sysmem) {
1807 ret = cpc_write(cpu, epp_set_reg,
1808 perf_ctrls->energy_perf);
1809 if (ret)
1810 return ret;
1811 }
1812 } else {
1813 ret = -ENOTSUPP;
1814 pr_debug("_CPC in PCC/FFH/SystemMemory are not supported\n");
1815 }
1816
1817 return ret;
1818}
1819EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1820
1821/**
1822 * cppc_set_epp() - Write the EPP register.
1823 * @cpu: CPU on which to write register.
1824 * @epp_val: Value to write to the EPP register.
1825 */
1826int cppc_set_epp(int cpu, u64 epp_val)
1827{
1828 if (epp_val > CPPC_EPP_ENERGY_EFFICIENCY_PREF)
1829 return -EINVAL;
1830
1831 return cppc_set_reg_val(cpu, ENERGY_PERF, epp_val);
1832}
1833EXPORT_SYMBOL_GPL(cppc_set_epp);
1834
1835/**
1836 * cppc_get_auto_act_window() - Read autonomous activity window register.
1837 * @cpu: CPU from which to read register.
1838 * @auto_act_window: Return address.
1839 *
1840 * According to ACPI 6.5, s8.4.6.1.6, the value read from the autonomous
1841 * activity window register consists of two parts: a 7 bits value indicate
1842 * significand and a 3 bits value indicate exponent.
1843 */
1844int cppc_get_auto_act_window(int cpu, u64 *auto_act_window)
1845{
1846 unsigned int exp;
1847 u64 val, sig;
1848 int ret;
1849
1850 if (auto_act_window == NULL)
1851 return -EINVAL;
1852
1853 ret = cppc_get_reg_val(cpu, AUTO_ACT_WINDOW, &val);
1854 if (ret)
1855 return ret;
1856
1857 sig = val & CPPC_AUTO_ACT_WINDOW_MAX_SIG;
1858 exp = (val >> CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) & CPPC_AUTO_ACT_WINDOW_MAX_EXP;
1859 *auto_act_window = sig * int_pow(10, exp);
1860
1861 return 0;
1862}
1863EXPORT_SYMBOL_GPL(cppc_get_auto_act_window);
1864
1865/**
1866 * cppc_set_auto_act_window() - Write autonomous activity window register.
1867 * @cpu: CPU on which to write register.
1868 * @auto_act_window: usec value to write to the autonomous activity window register.
1869 *
1870 * According to ACPI 6.5, s8.4.6.1.6, the value to write to the autonomous
1871 * activity window register consists of two parts: a 7 bits value indicate
1872 * significand and a 3 bits value indicate exponent.
1873 */
1874int cppc_set_auto_act_window(int cpu, u64 auto_act_window)
1875{
1876 /* The max value to store is 1270000000 */
1877 u64 max_val = CPPC_AUTO_ACT_WINDOW_MAX_SIG * int_pow(10, CPPC_AUTO_ACT_WINDOW_MAX_EXP);
1878 int exp = 0;
1879 u64 val;
1880
1881 if (auto_act_window > max_val)
1882 return -EINVAL;
1883
1884 /*
1885 * The max significand is 127, when auto_act_window is larger than
1886 * 129, discard the precision of the last digit and increase the
1887 * exponent by 1.
1888 */
1889 while (auto_act_window > CPPC_AUTO_ACT_WINDOW_SIG_CARRY_THRESH) {
1890 auto_act_window /= 10;
1891 exp += 1;
1892 }
1893
1894 /* For 128 and 129, cut it to 127. */
1895 if (auto_act_window > CPPC_AUTO_ACT_WINDOW_MAX_SIG)
1896 auto_act_window = CPPC_AUTO_ACT_WINDOW_MAX_SIG;
1897
1898 val = (exp << CPPC_AUTO_ACT_WINDOW_SIG_BIT_SIZE) + auto_act_window;
1899
1900 return cppc_set_reg_val(cpu, AUTO_ACT_WINDOW, val);
1901}
1902EXPORT_SYMBOL_GPL(cppc_set_auto_act_window);
1903
1904/**
1905 * cppc_get_auto_sel() - Read autonomous selection register.
1906 * @cpu: CPU from which to read register.
1907 * @enable: Return address.
1908 */
1909int cppc_get_auto_sel(int cpu, bool *enable)
1910{
1911 u64 auto_sel;
1912 int ret;
1913
1914 if (enable == NULL)
1915 return -EINVAL;
1916
1917 ret = cppc_get_reg_val(cpu, AUTO_SEL_ENABLE, &auto_sel);
1918 if (ret)
1919 return ret;
1920
1921 *enable = (bool)auto_sel;
1922
1923 return 0;
1924}
1925EXPORT_SYMBOL_GPL(cppc_get_auto_sel);
1926
1927/**
1928 * cppc_set_auto_sel - Write autonomous selection register.
1929 * @cpu : CPU to which to write register.
1930 * @enable : the desired value of autonomous selection resiter to be updated.
1931 */
1932int cppc_set_auto_sel(int cpu, bool enable)
1933{
1934 return cppc_set_reg_val(cpu, AUTO_SEL_ENABLE, enable);
1935}
1936EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1937
1938/**
1939 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1940 * Continuous Performance Control package EnableRegister field.
1941 * @cpu: CPU for which to enable CPPC register.
1942 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1943 *
1944 * Return: 0 for success, -ERRNO or -EIO otherwise.
1945 */
1946int cppc_set_enable(int cpu, bool enable)
1947{
1948 return cppc_set_reg_val(cpu, ENABLE, enable);
1949}
1950EXPORT_SYMBOL_GPL(cppc_set_enable);
1951
1952/**
1953 * cppc_get_perf - Get a CPU's performance controls.
1954 * @cpu: CPU for which to get performance controls.
1955 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1956 *
1957 * Desired Performance is not read and is returned as 0.
1958 *
1959 * Return: 0 for success with perf_ctrls, -ERRNO otherwise.
1960 */
1961int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1962{
1963 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1964 struct cpc_register_resource *min_perf_reg, *max_perf_reg,
1965 *energy_perf_reg, *auto_sel_reg;
1966 u64 min = 0, max = 0, energy_perf = 0, auto_sel = 0;
1967 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1968 struct cppc_pcc_data *pcc_ss_data = NULL;
1969 int ret = 0, regs_in_pcc = 0;
1970
1971 if (!cpc_desc) {
1972 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1973 return -ENODEV;
1974 }
1975
1976 if (!perf_ctrls) {
1977 pr_debug("Invalid perf_ctrls pointer\n");
1978 return -EINVAL;
1979 }
1980
1981 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1982 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1983 energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1984 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1985
1986 /* Are any of the regs PCC ?*/
1987 if (CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg) ||
1988 CPC_IN_PCC(energy_perf_reg) ||
1989 CPC_IN_PCC(auto_sel_reg)) {
1990 if (pcc_ss_id < 0) {
1991 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1992 return -ENODEV;
1993 }
1994 pcc_ss_data = pcc_data[pcc_ss_id];
1995 regs_in_pcc = 1;
1996 down_write(&pcc_ss_data->pcc_lock);
1997 /* Ring doorbell once to update PCC subspace */
1998 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1999 ret = -EIO;
2000 goto out_err;
2001 }
2002 }
2003
2004 /* Read optional elements if present */
2005 if (CPC_SUPPORTED(max_perf_reg)) {
2006 ret = cpc_read(cpu, max_perf_reg, &max);
2007 if (ret)
2008 goto out_err;
2009 }
2010 perf_ctrls->max_perf = max;
2011
2012 if (CPC_SUPPORTED(min_perf_reg)) {
2013 ret = cpc_read(cpu, min_perf_reg, &min);
2014 if (ret)
2015 goto out_err;
2016 }
2017 perf_ctrls->min_perf = min;
2018
2019 perf_ctrls->desired_perf = 0;
2020
2021 if (CPC_SUPPORTED(energy_perf_reg)) {
2022 ret = cpc_read(cpu, energy_perf_reg, &energy_perf);
2023 if (ret)
2024 goto out_err;
2025 }
2026 perf_ctrls->energy_perf = energy_perf;
2027
2028 if (CPC_SUPPORTED(auto_sel_reg)) {
2029 ret = cpc_read(cpu, auto_sel_reg, &auto_sel);
2030 if (ret)
2031 goto out_err;
2032 }
2033 perf_ctrls->auto_sel = (bool)auto_sel;
2034
2035out_err:
2036 if (regs_in_pcc)
2037 up_write(&pcc_ss_data->pcc_lock);
2038 return ret;
2039}
2040EXPORT_SYMBOL_GPL(cppc_get_perf);
2041
2042/**
2043 * cppc_set_perf - Set a CPU's performance controls.
2044 * @cpu: CPU for which to set performance controls.
2045 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
2046 *
2047 * Return: 0 for success, -ERRNO otherwise.
2048 */
2049int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
2050{
2051 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
2052 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
2053 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
2054 struct cppc_pcc_data *pcc_ss_data = NULL;
2055 bool regs_in_pcc;
2056 int ret = 0;
2057
2058 if (!cpc_desc) {
2059 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
2060 return -ENODEV;
2061 }
2062
2063 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
2064 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
2065 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
2066 regs_in_pcc = CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) ||
2067 CPC_IN_PCC(max_perf_reg);
2068
2069 /*
2070 * This is Phase-I where we want to write to CPC registers
2071 * -> We want all CPUs to be able to execute this phase in parallel
2072 *
2073 * Since read_lock can be acquired by multiple CPUs simultaneously we
2074 * achieve that goal here
2075 */
2076 if (regs_in_pcc) {
2077 if (pcc_ss_id < 0) {
2078 pr_debug("Invalid pcc_ss_id\n");
2079 return -ENODEV;
2080 }
2081 pcc_ss_data = pcc_data[pcc_ss_id];
2082 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
2083 if (pcc_ss_data->platform_owns_pcc) {
2084 ret = check_pcc_chan(pcc_ss_id, false);
2085 if (ret) {
2086 up_read(&pcc_ss_data->pcc_lock);
2087 return ret;
2088 }
2089 }
2090 /*
2091 * Update the pending_write to make sure a PCC CMD_READ will not
2092 * arrive and steal the channel during the switch to write lock
2093 */
2094 pcc_ss_data->pending_pcc_write_cmd = true;
2095 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
2096 cpc_desc->write_cmd_status = 0;
2097 }
2098
2099 if (CPC_SUPPORTED(desired_reg))
2100 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
2101
2102 /*
2103 * Only write if min_perf and max_perf not zero. Some drivers pass zero
2104 * value to min and max perf, but they don't mean to set the zero value,
2105 * they just don't want to write to those registers.
2106 */
2107 if (perf_ctrls->min_perf && CPC_SUPPORTED(min_perf_reg))
2108 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
2109 if (perf_ctrls->max_perf && CPC_SUPPORTED(max_perf_reg))
2110 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
2111
2112 if (regs_in_pcc)
2113 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
2114 /*
2115 * This is Phase-II where we transfer the ownership of PCC to Platform
2116 *
2117 * Short Summary: Basically if we think of a group of cppc_set_perf
2118 * requests that happened in short overlapping interval. The last CPU to
2119 * come out of Phase-I will enter Phase-II and ring the doorbell.
2120 *
2121 * We have the following requirements for Phase-II:
2122 * 1. We want to execute Phase-II only when there are no CPUs
2123 * currently executing in Phase-I
2124 * 2. Once we start Phase-II we want to avoid all other CPUs from
2125 * entering Phase-I.
2126 * 3. We want only one CPU among all those who went through Phase-I
2127 * to run phase-II
2128 *
2129 * If write_trylock fails to get the lock and doesn't transfer the
2130 * PCC ownership to the platform, then one of the following will be TRUE
2131 * 1. There is at-least one CPU in Phase-I which will later execute
2132 * write_trylock, so the CPUs in Phase-I will be responsible for
2133 * executing the Phase-II.
2134 * 2. Some other CPU has beaten this CPU to successfully execute the
2135 * write_trylock and has already acquired the write_lock. We know for a
2136 * fact it (other CPU acquiring the write_lock) couldn't have happened
2137 * before this CPU's Phase-I as we held the read_lock.
2138 * 3. Some other CPU executing pcc CMD_READ has stolen the
2139 * down_write, in which case, send_pcc_cmd will check for pending
2140 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
2141 * So this CPU can be certain that its request will be delivered
2142 * So in all cases, this CPU knows that its request will be delivered
2143 * by another CPU and can return
2144 *
2145 * After getting the down_write we still need to check for
2146 * pending_pcc_write_cmd to take care of the following scenario
2147 * The thread running this code could be scheduled out between
2148 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
2149 * could have delivered the request to Platform by triggering the
2150 * doorbell and transferred the ownership of PCC to platform. So this
2151 * avoids triggering an unnecessary doorbell and more importantly before
2152 * triggering the doorbell it makes sure that the PCC channel ownership
2153 * is still with OSPM.
2154 * pending_pcc_write_cmd can also be cleared by a different CPU, if
2155 * there was a pcc CMD_READ waiting on down_write and it steals the lock
2156 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
2157 * case during a CMD_READ and if there are pending writes it delivers
2158 * the write command before servicing the read command
2159 */
2160 if (regs_in_pcc) {
2161 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
2162 /* Update only if there are pending write commands */
2163 if (pcc_ss_data->pending_pcc_write_cmd)
2164 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
2165 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
2166 } else
2167 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
2168 wait_event(pcc_ss_data->pcc_write_wait_q,
2169 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
2170
2171 /* send_pcc_cmd updates the status in case of failure */
2172 ret = cpc_desc->write_cmd_status;
2173 }
2174 return ret;
2175}
2176EXPORT_SYMBOL_GPL(cppc_set_perf);
2177
2178/**
2179 * cppc_get_perf_limited - Get the Performance Limited register value.
2180 * @cpu: CPU from which to get Performance Limited register.
2181 * @perf_limited: Pointer to store the Performance Limited value.
2182 *
2183 * The returned value contains sticky status bits indicating platform-imposed
2184 * performance limitations.
2185 *
2186 * Return: 0 for success, -EIO on failure, -EOPNOTSUPP if not supported.
2187 */
2188int cppc_get_perf_limited(int cpu, u64 *perf_limited)
2189{
2190 return cppc_get_reg_val(cpu, PERF_LIMITED, perf_limited);
2191}
2192EXPORT_SYMBOL_GPL(cppc_get_perf_limited);
2193
2194/**
2195 * cppc_set_perf_limited() - Clear bits in the Performance Limited register.
2196 * @cpu: CPU on which to write register.
2197 * @bits_to_clear: Bitmask of bits to clear in the perf_limited register.
2198 *
2199 * The Performance Limited register contains two sticky bits set by platform:
2200 * - Bit 0 (Desired_Excursion): Set when delivered performance is constrained
2201 * below desired performance. Not used when Autonomous Selection is enabled.
2202 * - Bit 1 (Minimum_Excursion): Set when delivered performance is constrained
2203 * below minimum performance.
2204 *
2205 * These bits are sticky and remain set until OSPM explicitly clears them.
2206 * This function only allows clearing bits (the platform sets them).
2207 *
2208 * Return: 0 for success, -EINVAL for invalid bits, -EIO on register
2209 * access failure, -EOPNOTSUPP if not supported.
2210 */
2211int cppc_set_perf_limited(int cpu, u64 bits_to_clear)
2212{
2213 u64 current_val, new_val;
2214 int ret;
2215
2216 /* Only bits 0 and 1 are valid */
2217 if (bits_to_clear & ~CPPC_PERF_LIMITED_MASK)
2218 return -EINVAL;
2219
2220 if (!bits_to_clear)
2221 return 0;
2222
2223 ret = cppc_get_perf_limited(cpu, &current_val);
2224 if (ret)
2225 return ret;
2226
2227 /* Clear the specified bits */
2228 new_val = current_val & ~bits_to_clear;
2229
2230 return cppc_set_reg_val(cpu, PERF_LIMITED, new_val);
2231}
2232EXPORT_SYMBOL_GPL(cppc_set_perf_limited);
2233
2234/**
2235 * cppc_get_transition_latency - returns frequency transition latency in ns
2236 * @cpu_num: CPU number for per_cpu().
2237 *
2238 * ACPI CPPC does not explicitly specify how a platform can specify the
2239 * transition latency for performance change requests. The closest we have
2240 * is the timing information from the PCCT tables which provides the info
2241 * on the number and frequency of PCC commands the platform can handle.
2242 *
2243 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
2244 * then assume there is no latency.
2245 */
2246int cppc_get_transition_latency(int cpu_num)
2247{
2248 /*
2249 * Expected transition latency is based on the PCCT timing values
2250 * Below are definition from ACPI spec:
2251 * pcc_nominal- Expected latency to process a command, in microseconds
2252 * pcc_mpar - The maximum number of periodic requests that the subspace
2253 * channel can support, reported in commands per minute. 0
2254 * indicates no limitation.
2255 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
2256 * completion of a command before issuing the next command,
2257 * in microseconds.
2258 */
2259 struct cpc_desc *cpc_desc;
2260 struct cpc_register_resource *desired_reg;
2261 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
2262 struct cppc_pcc_data *pcc_ss_data;
2263 int latency_ns = 0;
2264
2265 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
2266 if (!cpc_desc)
2267 return -ENODATA;
2268
2269 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
2270 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
2271 return 0;
2272
2273 if (!CPC_IN_PCC(desired_reg) || pcc_ss_id < 0)
2274 return -ENODATA;
2275
2276 pcc_ss_data = pcc_data[pcc_ss_id];
2277 if (pcc_ss_data->pcc_mpar)
2278 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
2279
2280 latency_ns = max_t(int, latency_ns, pcc_ss_data->pcc_nominal * 1000);
2281 latency_ns = max_t(int, latency_ns, pcc_ss_data->pcc_mrtt * 1000);
2282
2283 return latency_ns;
2284}
2285EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
2286
2287/* Minimum struct length needed for the DMI processor entry we want */
2288#define DMI_ENTRY_PROCESSOR_MIN_LENGTH 48
2289
2290/* Offset in the DMI processor structure for the max frequency */
2291#define DMI_PROCESSOR_MAX_SPEED 0x14
2292
2293/* Callback function used to retrieve the max frequency from DMI */
2294static void cppc_find_dmi_mhz(const struct dmi_header *dm, void *private)
2295{
2296 const u8 *dmi_data = (const u8 *)dm;
2297 u16 *mhz = (u16 *)private;
2298
2299 if (dm->type == DMI_ENTRY_PROCESSOR &&
2300 dm->length >= DMI_ENTRY_PROCESSOR_MIN_LENGTH) {
2301 u16 val = (u16)get_unaligned((const u16 *)
2302 (dmi_data + DMI_PROCESSOR_MAX_SPEED));
2303 *mhz = umax(val, *mhz);
2304 }
2305}
2306
2307/* Look up the max frequency in DMI */
2308u64 cppc_get_dmi_max_khz(void)
2309{
2310 u16 mhz = 0;
2311
2312 dmi_walk(cppc_find_dmi_mhz, &mhz);
2313
2314 /*
2315 * Real stupid fallback value, just in case there is no
2316 * actual value set.
2317 */
2318 mhz = mhz ? mhz : 1;
2319
2320 return KHZ_PER_MHZ * mhz;
2321}
2322EXPORT_SYMBOL_GPL(cppc_get_dmi_max_khz);
2323
2324/*
2325 * If CPPC lowest_freq and nominal_freq registers are exposed then we can
2326 * use them to convert perf to freq and vice versa. The conversion is
2327 * extrapolated as an affine function passing by the 2 points:
2328 * - (Low perf, Low freq)
2329 * - (Nominal perf, Nominal freq)
2330 */
2331unsigned int cppc_perf_to_khz(struct cppc_perf_caps *caps, unsigned int perf)
2332{
2333 s64 retval, offset = 0;
2334 static u64 max_khz;
2335 u64 mul, div;
2336
2337 if (caps->lowest_freq && caps->nominal_freq) {
2338 /* Avoid special case when nominal_freq is equal to lowest_freq */
2339 if (caps->lowest_freq == caps->nominal_freq) {
2340 mul = caps->nominal_freq;
2341 div = caps->nominal_perf;
2342 } else {
2343 mul = caps->nominal_freq - caps->lowest_freq;
2344 div = caps->nominal_perf - caps->lowest_perf;
2345 }
2346 mul *= KHZ_PER_MHZ;
2347 offset = caps->nominal_freq * KHZ_PER_MHZ -
2348 div64_u64(caps->nominal_perf * mul, div);
2349 } else {
2350 if (!max_khz)
2351 max_khz = cppc_get_dmi_max_khz();
2352 mul = max_khz;
2353 div = caps->highest_perf;
2354 }
2355
2356 retval = offset + div64_u64(perf * mul, div);
2357 if (retval >= 0)
2358 return retval;
2359 return 0;
2360}
2361EXPORT_SYMBOL_GPL(cppc_perf_to_khz);
2362
2363unsigned int cppc_khz_to_perf(struct cppc_perf_caps *caps, unsigned int freq)
2364{
2365 s64 retval, offset = 0;
2366 static u64 max_khz;
2367 u64 mul, div;
2368
2369 if (caps->lowest_freq && caps->nominal_freq) {
2370 /* Avoid special case when nominal_freq is equal to lowest_freq */
2371 if (caps->lowest_freq == caps->nominal_freq) {
2372 mul = caps->nominal_perf;
2373 div = caps->nominal_freq;
2374 } else {
2375 mul = caps->nominal_perf - caps->lowest_perf;
2376 div = caps->nominal_freq - caps->lowest_freq;
2377 }
2378 /*
2379 * We don't need to convert to kHz for computing offset and can
2380 * directly use nominal_freq and lowest_freq as the div64_u64
2381 * will remove the frequency unit.
2382 */
2383 offset = caps->nominal_perf -
2384 div64_u64(caps->nominal_freq * mul, div);
2385 /* But we need it for computing the perf level. */
2386 div *= KHZ_PER_MHZ;
2387 } else {
2388 if (!max_khz)
2389 max_khz = cppc_get_dmi_max_khz();
2390 mul = caps->highest_perf;
2391 div = max_khz;
2392 }
2393
2394 retval = offset + div64_u64(freq * mul, div);
2395 if (retval >= 0)
2396 return retval;
2397 return 0;
2398}
2399EXPORT_SYMBOL_GPL(cppc_khz_to_perf);